FemtoClock® LVDS Programmable
Delay Line
ICS854S296I-33
DATA SHEET
General Description
Features
The ICS854S296I-33 is a high performance LVDS Programmable
Delay Line. The delay can vary from 2.2ns to 12.5ns in 10ps steps.
The ICS854S296I-33 is characterized to operate from a 3.3V power
supply and is guaranteed over industrial temperature range.
•
•
•
One LVDS level output
The delay of the device varies in discrete steps based on a control
word. A 10-bit long control word sets the delay in 10ps increments.
Also, the input pins IN and nIN default to an equivalent low state
when left floating. The control register can accept CMOS or TTL
level signals.
•
•
•
•
•
•
Maximum frequency: 1.2GHz
One differential clock input pair
Differential input clock (IN, nIN) can accept the following signaling
levels: LVPECL, LVDS, CML
Programmable Delay Range: 2.2ns to 12.5ns in 10ps steps
D[9:0] can accept LVPECL, LVCMOS or LVTTL levels
Full 3.3V supply voltages
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
D1
D2
D3
GND
D4
D5
D7
D6
Pin Assignment
32 31 30 29 28 27 26 25
D8
1
24
GND
D9
2
23
D0
RESERVED
3
22
VDD
IN
4
21
Q
nIN
5
20
nQ
VBB
6
19
VDD
VEF
7
18
VDD
VCF
8
17
FTUNE
nEN
RESERVED
RESERVED
VDD
SETMIN
SETMAX
10 11 12 13 14 15 16
LEN
GND
9
ICS854S296I-33
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm EPad
K Package
Top View
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Block Diagram
IN
0
nIN
0
1
512
GD
nEN
0
1
256
GD
0
1
0
1
128
GD
64
GD
1
32
GD
GD = Gate Delay
16
GD
0
0
0
0
1
1
1
1
8
GD
4
GD
2
GD
0
1
1
GD
FTUNE
D[9:0]
LEN
SETMIN
0
10- bit
Latch
1
1
GD
SETMAX
Q
nQ
VBB
VCF
VEF
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2, 23, 25,
26, 27, 29, 30,
31, 32
D8, D9, D0, D1,
D2, D3, D4, D5,
D6, D7
Input
3, 14, 15
RESERVED
Reserved
4
IN
Input
Pulldown
Non-inverting LVPECL differential input.
5
nIN
Input
Pullup/
Pulldown
Inverting LVPECL differential input.
6
VBB
Output
Reference voltage output. This pin can be used to rebias AC-coupled inputs
to IN and nIN. When used, de-couple to VDD using a 0.01PF capacitor. If not
used, leave floating.
7
VEF
Output
Reference voltage output. See Table 3C.
8
VCF
Input
Reference voltage input. The voltage driven on VCF sets the logic transition
threshold for D[9:0].
9, 24, 28
GND
Power
Power supply ground
10
LEN
Input
Pulldown
D inputs LOAD and HOLD control input. When HIGH, latches the D[9:0] bits.
When LOW, the D[9:0] latches are transparent. Single-ended LVPECL
interface levels. See Table 3B.
11
SETMIN
Input
Pulldown
Minimum delay set logic input. When HIGH, D[9:0] registers are reset. When
LOW, the delay is set by SETMAX or D[9:0]. Default is LOW when left
floating. Single-ended LVPECL interface levels. See Table 3D.
Pulldown
Maximum delay set logic input. When SETMAX is set HIGH and SETMIN is
set LOW, D[9:0] = 1111111111. When SETMAX is LOW, the delay is set by
SETMIN or D[9:0]. Default is low when left floating. Single-ended LVPECL
interface levels. See Table 3D.
Pulldown
Parallel data input D[9:0].
Single-ended LVCMOS, LVTTL, LVPECL interface levels.
Reserved pins.
12
SETMAX
Input
13, 18, 19, 22
VDD
Power
16
nEN
Input
17
FTUNE
Analog
Input
Fine tune delay control input. By varying the input voltage, it provides an
additional delay finer than the 10ps digital resolution.
20, 21
nQ, Q
Output
Differential output pair. LVDS interface levels.
Positive supply pins.
Pulldown
Single-ended control enable pin. When LOW, Q is delayed from IN.
When HIGH, Q is a differential LOW. Default is LOW when left floating.
Single-ended LVPECL interface levels. See Table 3A.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
50
k:
RPULLDOWN
Input Pulldown Resistor
50
k:
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
Test Conditions
3
Minimum
Typical
Maximum
Units
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Propagation Delay vs. FTUNE Voltage Graph
Function Tables
Table 3A. Delay Enable
nEN
Table 3D. Theoretical Delta Delay Values
D[9:0] Value
SETMIN
SETMAX
Programmable
DelayNOTE 1 (ps)
XXXXXXXXXX
H
L
0
0000000000
L
L
0 (default)
0000000001
L
L
10
0000000010
L
L
20
0000000011
L
L
30
0000000100
L
L
40
0000000101
L
L
50
0000000110
L
L
60
0000000111
L
L
70
0000001000
L
L
80
0000010000
L
L
160
0000100000
L
L
320
0001000000
L
L
640
0010000000
L
L
1280
0100000000
L
L
2560
1000000000
L
L
5120
1111111111
L
L
10230
XXXXXXXXXX
L
H
10240
Q, nQ
0 (default)
IN, nIN delayed
1
Q = LOW, nQ = HIGH
Table 3B. Digital Control Latch
LEN
Latch Action
0 (default)
Pass Through D[9:0]
1
Latched D[9:0]
Table 3C. VCF Connection for D[9:0] Logic Interface
Input
VCF Connection
D[9:0] Logic Interface
VCF
VEF (NOTE 1)
LVPECL
VCF
No Connect
LVCMOS
VCF
1.5V source
LVTTL
NOTE 1: Short VCF (pin 8) to VEF (pin 7).
NOTE 1: Fixed minimum delay not included.
NOTE: Refer to Table 6, AC Characteristics, for typical Step Delay
values.
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, TJA
39.5qC/W (0 mps)
Storage Temperature, TSTG
-65qC to 150qC
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VDD
Positive Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
150
mA
Maximum
Units
No load, max VDD
Table 5B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
2.2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
D[9:0]
VDD = VIN = 3.6V
150
μA
IIL
Input Low Current
D[9:0]
VDD = 3.6V, VIN = 0V
-10
μA
Table 5C. LVPECL Differential DC Characteristics, VDD = 3.3V ± 0.3V, GND = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Voltage
VCMR
IN, nIN
Minimum
Typical
VDD = VIN = 3.6V
Maximum
Units
150
μA
IN
VDD = 3.6V, VIN = 0V
-10
μA
nIN
VDD = 3.6V, VIN = 0V
-150
μA
0.15
1.3
V
Common Mode Range; NOTE 1
GND + 1.2
VDD
V
VBB
Output Voltage Reference
VDD – 1.55
VDD – 1.35
VDD – 1.15
V
VEF
Mode Connection
VDD – 1.40
VDD – 1.30
VDD – 1.20
V
NOTE 1: Common mode input voltage is defined as VIH.
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Table 5D. LVPECL Single-Ended DC Characteristics, VDD = 3.3V ± 0.3V, GND = 0V, TA = -40°C to to 85°C
Symbol
Parameter
Test Conditions
VIH
Input
High Voltage;
NOTE 1
IN, nIN, LEN, D[9:0],
nEN, SETMIN, SETMAX
VIL
Input
Low Voltage;
NOTE 1
IN, nIN, LEN, D[9:0],
nEN, SETMIN, SETMAX
IIH
Input
High Current
IN, nIN, LEN, D[9:0],
nEN, SETMIN, SETMAX
IIL
Input
Low Current
Minimum
Typical
Maximum
Units
VDD – 1.3
VDD – 0.940
V
VDD – 1.870
VDD – 1.45
V
150
μA
VDD = VIN = 3.6V
SETMIN, SETMAX,
IN, LEN, D[9:0], nEN
VDD = 3.6V, VIN = 0V
-10
μA
nIN
VDD = 3.6V, VIN = 0V
-150
μA
NOTE 1: To enable LVPECL interface levels on pins D[9:0], pin 7 must be shorted to pin 8. See Table 3C.
Table 5E. LVDS DC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
'VOD
VOD Magnitude Change
VOS
Offset Voltage
'VOS
VOS Magnitude Change
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
Test Conditions
Minimum
350
1.10
6
Typical
Maximum
Units
650
mV
50
mV
1.30
V
50
mV
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
tPD
Propagation Delay
Test Conditions
't
INL
tS
tH
tR
Maximum
Units
1.2
GHz
Dx = 0
1800
2200
2700
ps
IN to Q, nQ
Dx = 1023
10000
12500
15000
ps
Dx = 0
1900
2200
2700
ps
tPD_MAX – tPD_MIN
8200
Programmable Propagation Range
ps
D0 = HIGH
15
ps
D1 = HIGH
25
ps
D2 = HIGH
45
ps
D3 = HIGH
85
ps
D4 = HIGH
165
ps
D5 = HIGH
330
ps
D6 = HIGH
645
ps
D7 = HIGH
1270
ps
D8 = HIGH
2540
ps
D9 = HIGH
5075
ps
D[9:0] = HIGH
10135
ps
±10
ps
D to LEN
-185
ps
D to IN, nIN
-200
ps
nEN to IN, IN
-360
ps
LEN to D
-275
ps
IN, nIN to nEN
-875
ps
nEN to IN, nIN
465
ps
SETMAX to LEN
735
ps
SETMIN to LEN
775
ps
Step Delay
Integral Non-Linearity; NOTE 1
Setup Time
Typical
IN to Q, nQ
nEN to Q, nQ
tPD_RANGE
Minimum
Hold Time
Release Time
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Q, nQ
20% to 80% at 100MHz
70
300
ps
fOUT d 625MHz
40
60
%
NOTE: Characterized up to fOUT = 1.2GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Deviation from a linear delay (actual Min. to Max.) in the 1024 programmable steps.
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Parameter Measurement Information
VDD
SCOPE
Qx
VDD
3.3V±0.3V
POWER SUPPLY
+ Float GND –
nIN
V
PP
Cross Points
V
CMR
IN
nQx
GND
Differential Input Level
LVDS Output Load Test Circuit
nQ
nIN
Q
IN
nQ
Q
tPD
Propagation Delay
Output Duty Cycle/Pulse Width/Period
nQ
80%
80%
VOD
Q
20%
20%
tR
tF
Output Rise/Fall Time
Differential Output Voltage Setup
Offset Voltage Setup
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pulldown resistors; additional resistance
is not required but can be added for additional protection. A 1k:
resistor can be used.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VDD are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50: applications, R3 and R4 can be 100:. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
LVPECL Clock Input Interface
The IN/nIN accepts LVPECL, CML, LVDS and other differential
signals. Both differential signals must meet the VPP and VCMR input
requirements. Figures 2A to 2E show interface examples for the
IN/nIN input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
Zo = 50Ω
R2
50
IN
Zo = 50Ω
R1
100
IN
Zo = 50Ω
nIN
Zo = 50Ω
nIN
LVPECL
Differential
Inputs
CML
LVPECL
Differential
Inputs
CML Built-In Pullup
Figure 2B. IN/nIN Input Driven by a
Built-In Pullup CML Driver
Figure 2A. IN/nIN Input Driven by a CML Driver
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V LVPECL
Zo = 50Ω
Zo = 50Ω
C1
Zo = 50Ω
C2
IN
IN
VBB
Zo = 50Ω
nIN
nIN
LVPECL
Differential
Inputs
LVPECL
R1
84
R2
84
R5
100 - 200
R6
100 - 200
R1
50
R2
50
LVPECL
Differential
Inputs
Figure 2D. IN/nIN Input Driven by a
3.3V LVPECL Driver with AC Couple
Figure 2C. IN/nIN Input Driven by a 3.3V LVPECL Driver
3.3V
3.3V
Zo = 50Ω
C1
IN
R5
100
VBB
C2
nIN
Zo = 50Ω
LVDS
R1
1k
R2
1k
LVPECL
Differential
Inputs
C3
0.1μF
Figure 2E. IN/nIN Input Driven by a 3.3V LVDS Driver
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 3. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90: and 132:. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100: parallel resistor at the receiver and a 100: differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 4A can be used
with either type of output structure. Figure 4B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO | Z T
ZT
LVDS
Receiver
Figure 4A. Standard Termination
LVDS
Driver
ZO | ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 4B. Optional Termination
LVDS Termination
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Schematic Layout
known beforehand, but use of a DAC, as shown in the schematic
allows for finer control of the delay. For lower frequency clocks this pin
can instead be pulled to ground to set the analog delay to zero.
Figure 5 (next page) shows an example ICS854S296I-33 application
schematic. The schematic focuses on functional connections and is
not configuration specific. Input and output terminations shown are
intended as examples only and may not represent the exact user
configuration. Refer to the pin description and functional tables in the
datasheet to ensure the logic control inputs are properly set.
To achieve optimum jitter performance, device power supply isolation
from the board supply is required. The ICS854S296I-33 provides
separate VDD and GND pins for optimum power filtering across the
device.
In this example schematic, the input is driven by a 3.3V LVPECL
driver but HCSL or LVDS inputs will work as well. VCF is depicted as
a No Connect, which selects LVCMOS levels for pins D[9:0]. D[9:0],
nEN, LEN, SETMIN and SETMAX are set by pull up and pull down
resistors for compensation of a static delay, the most common
application. LEN can hardwired to a logic low so that D[9:0] pin values
are not latched, but instead directly set the internal logic values. This
allows pin strapping to avoid the need for an external control of the
LEN latch pin.
In order to achieve the best possible filtering, it is highly
recommended that the 0.1uF capacitors directly connected to the
power and FTUNE pins be placed on the device side of the PCB as
close to their corresponding pins as possible. This is represented by
the placement of these capacitors in the schematic. If space is
limited, the ferrite beads, 10uf and 0.1uF capacitor connected to 3.3V
can be placed on the opposite side of the PCB. If space permits,
place all filter components on the device side of the board.
All the control pins can be defined with an FPGA, rather than pull up
and pull down resistors as shown in the schematic, if the delay is
determined after board fabrication or if the delay requirement is
dependant on the exact system configuration. Note that nEN, LEN,
SETMIN, SETMAX are LVPECL levels by design but can be
overdriven by LVCMOS input levels, as is done with the external pull
ups and pull downs in this example.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
FTUNE allows for interpolation of the total path delay between the
resolution of the D[9:0] step size for higher frequency clocks. This pin
has an RC low pass filter to suppress any noise coupled onto FTUNE.
FTUNE can also be set with a voltage divider if the required delay is
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Logic Control Input Examples
VD D
Set Logic
Input to '1'
Set Logic
Input to '0'
VD D
3. 3V
RU1
1K
RU2
N ot In st all
To Lo gic
Inpu t
pins
VD D
C2
1
BL M18BB22 1SN 1
C1
0 .1u F
10u F
RD2
1K
23
25
26
27
29
30
31
32
1
2
SE TMIN 11
SE TMAX 12
n EN
Z o = 5 0 Oh m
R 1 50
16
4
C5
0 .1u F
C7
0 .1u F
C6
0 .1u F
VD D
VD D
VD D
VD D
U1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
C4
0. 1u F
13
18
19
22
RD1
N ot I nst all
FB 1
2
To Logic
Input
pins
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
SETMI N
SETMAX
nEN
IN
Q
Z o = 50 Ohm
21
+
Z o = 5 0 Oh m
5
R 2 50
3. 3V PEC L D riv er
nQ
6
R3
50
L EN
nI N
10
L VD S R ec eiv er
LEN
R eserv ed
R 5 1k
DAC
17
-
VBB
R eserv ed
7
8
Z o = 50 Ohm
20
R4
1 00
VEF
VC F
R eserv ed
3
14
15
FTU N E
ePAD
33
9
24
28
DAC Voltage
set for
required
analog delay
GN D
GN D
GN D
C8
0.1 uF
Figure 5. ICS854S296I-33 Application Schematic
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS854S296I-33.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS854S296I-33 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results.
The maximum current at 85°C is as follows:
IDD_MAX = 150mA
•
Power_MAX = VDD_MAX * IDD_MAX = 3.6V * 150mA = 540mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = TJA * Pd_total + TA
Tj = Junction Temperature
TJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance TJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 39.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.540W * 39.5°C/W = 106.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance TJA for 32 Lead VFQFN, Forced Convection
TJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
0
1
2.5
39.5°C/W
34.5°C/W
31.0°C/W
15
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Reliability Information
Table 8. TJA vs. Air Flow Table for a 32 Lead VFQFN
TJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
39.5°C/W
34.5°C/W
31.0°C/W
Transistor Count
The transistor count for ICS854S296I-33 is: 8686
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
L
A3
N
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
0. 08
C
Th er mal
Ba se
D2
C
Bottom View w/Type C ID
2
1
2
1
4
D2
2
N &N
Odd
Bottom View w/Type A ID
CHAMFER
e
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
NOTE: The mechanical package drawing is a generic drawing that
applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device.
The pin count and pinout are shown on the front page. The package
dimensions are in Table 9.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
854S296DKI-33LF
ICS296DI33L
Lead-Free, 32 Lead VFQFN
Tray
-40qC to +85qC
854S296DKI-33LFT
ICS296DI33L
Lead-Free, 32 Lead VFQFN
Tape & Reel
-40qC to +85qC
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
Revision History Sheet
Rev
Table
Page
A
T1
T5D
3
6
Description of Change
Date
Pin Description Table, corrected Pin 6, VBB description.
LVPECL Single-ended DC Characteristics Table - deleted Note 2.
ICS854S296DKI-33 REVISION A JANUARY 15, 2014
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1/15/2014
©2014 Integrated Device Technology, Inc.
ICS854S296I-33 Data Sheet
FEMTOCLOCK® LVDS PROGRAMMABLE DELAY LINE
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