854S54AKILF

Dual 2:1 and 1:2 Differential-to-LVDS Multiplexer ICS854S54I DATA SHEET General Description Features The ICS854S54I is a dual 2:1 and 1:2 Multiplexer. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to one of two outputs. This device is useful for multiplexing multi-rate Ethernet PHYs which have 100M bit and 1000M bit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. See Application Section for further information. • • • Three differential LVDS output pairs • • • Maximum output frequency: 2.5GHz • • • • Part-to-part skew: 200ps (maximum) The ICS854S54I is optimized for applications requiring very high performance and has a maximum operating frequency of 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. Three differential LVPECL clock input pairs PCLKx pair can accept the following differential input levels: LVPECL, LVDS, CML Additive phase jitter, RMS: 0.053ps (typical) Propagation delay: 480ps (maximum), QA/nQA 445ps (maximum), QBx/nQBx Full 2.5V supply mode -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package PCLKA0 Pulldown nPCLKA0 Pullup/Pulldown PCLKA1 Pulldown nPCLKA1 Pullup/Pulldown 0 QB0 1 QA nQA nQB0 VDD nQA QA CLK_SELA Pulldown CLK_SELA Pin Assignment Block Diagram 16 15 14 13 12 PCLKA0 2 11 nPCLKA0 QB1 3 1 10 PCLKA1 nQB1 4 7 8 PCLKB CLK_SELB GND QB0 nQB0 6 nPCLKB PCLKB Pulldown nPCLKB Pullup/Pulldown 9 nPCLKA1 5 ICS854S54I CLK_SELB Pulldown ICS854S54AKI REVISION A OCTOBER 30, 2012 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View QB1 nQB1 1 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Table 1. Pin Descriptions Number Name 1, 2 QB0, nQB0 Output Type Differential output pair. LVDS interface levels. Description 3, 4 QB1, nQB1 Output Differential output pair. LVDS interface levels. 5 PCLKB Input Pulldown Non-inverting LVPECL differential clock input. 6 nPCLKB Input Pullup/ Pulldown Inverting LVPECL differential clock input. VDD/2 default when left floating. 7 CLK_SELB Input Pulldown Clock select pin for QBx outputs. When HIGH, selects QB1, nQB1 outputs. When LOW, selects QB0, nQB0 outputs. See Table 3B. LVCMOS/LVTTL interface levels. 8 GND Power 9 nPCLKA1 Input Pullup/ Pulldown Inverting LVPECL differential clock input. VDD/2 default when left floating. 10 PCLKA1 Input Pulldown Non-inverting LVPECL differential clock input. 11 nPCLKA0 Input Pullup/ Pulldown Inverting LVPECL differential clock input. VDD/2 default when left floating. 12 PCLKA0 Input Pulldown Non-inverting LVPECL differential clock input. 13 VDD Power 14 CLK_SELA Input 15, 16 nQA, QA Output Power supply ground. Power supply pin. Pulldown Clock select pin for PCLKA inputs. When HIGH, selects PCLKA1/nPCLKA1 inputs. When LOW, selects PCLKA0/nPCLKA0 inputs. See Table 3A. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance RPULLDOWN RVDD/2 Minimum Typical Maximum Units 2 pF Input Pullup Resistor 37.5 k RPullup/Pulldown Resistor 37.5 k Function Tables Table 3A. Control Input Function Table, Bank A Table 3B. Control Input Function Table, Bank B Bank A Bank B Control Input Outputs Control Input CLK_SELA QA, nQA CLK_SELB 0 (default) Selects PCLKA0, nPCLKA0 0 (default) 1 Selects PCLKA1, nPCLKA1 1 ICS854S54AKI REVISION A OCTOBER 30, 2012 2 Outputs QB0, nQB0 QB1, nQB1 Follows PCLKB input Logic Low Logic Low Follows PCLKB input ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 74.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 82 mA Maximum Units Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage 1.7 VDD + 0.3 V VIL Input Low Voltage -0.3 0.7 V IIH Input High Current CLK_SELA, CLK_SELB VDD = VIN = 2.625V 150 µA IIL Input Low Current CLK_SELA, CLK_SELB VDD = 2.625V, VIN = 0V ICS854S54AKI REVISION A OCTOBER 30, 2012 3 Minimum -10 Typical µA ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Table 4C. DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C -40°C Min Typ 25°C Max Min Typ 85°C Symbol Parameter IIH Input High Current PCLKAx, PCLKB, nPCLKx, nPCLKB IIL Input Low Current PCLKAx, PCLKB, nPCLKAx, nPCLKB VPP Peak-to-peak Input Voltage; NOTE 1 0.15 1.2 0.15 1.2 0.15 1.2 V VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 VDD 1.2 VDD 1.2 VDD V 150 Max Min Typ 150 -10 -10 Max Units 150 µA -10 µA NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C -40°C 25°C 85°C Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Units VOD Differential Output Voltage 350 450 550 350 450 550 350 450 550 mV VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.4 V VOS VOS Magnitude Change 50 mV 50 0.95 1.2 50 1.4 0.95 1.2 50 1.4 50 0.95 1.2 NOTE: Refer to Parameter Measurement Information, 2.5V Output Load Test Circuit diagram. ICS854S54AKI REVISION A OCTOBER 30, 2012 4 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER AC Electrical Characteristics Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions fOUT Output Frequency tPD Propagation Delay; NOTE 1 QA, nQA 225 480 ps QBx, nQBx 200 445 ps QA, nQA 622.08MHz, Integration Range: 12kHz - 20MHz 0.053 ps tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section; NOTE 2 QBx, nQBx 622.08MHz, Integration Range: 12kHz - 20MHz 0.045 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle MUX_ISOLATION MUX Isolation; NOTE 5 20% to 80% Minimum Typical 55 Maximum Units 2.5 GHz 200 ps 265 ps QA, nQA 47 53 % QBx, nQBx 47 53 % ƒOUT = 622.08MHz, VPP = 400mV 65 dB NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at  1.35GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Measured using clock input at 622.08MHz. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Q, nQ outputs measured differentially. See MUX Isolation diagram in Parameter Measurement Information section. ICS854S54AKI REVISION A OCTOBER 30, 2012 5 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter @ 622.08MHz 12kHz to 20MHz = 0.045ps (typical), SSB Phase Noise dBc/Hz QBx, nQBx Outputs Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS854S54AKI REVISION A OCTOBER 30, 2012 The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal Generator as external input to an Agilent 8133A 3GHz Pulse Generator". 6 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Parameter Measurement Information VDD SCOPE 2.5V±5% POWER SUPPLY + Float GND – Qx nPCLKA[0:1], nPCLKB nQx PCLKA[0:1], PCLKB VDD V Cross Points PP V CMR GND LVDS Output Load AC Test Circuit Differential Input Level Spectrum of Output Signal Q MUX selects active input clock signal A0 Amplitude (dB) Par t 1 nQx Qx nQy Par t 2 MUX_ISOL = A0 – A1 MUX selects static input A1 Qy tsk(pp) ƒ (fundamental) Part-to-Part Skew MUX Isolation nPCLKA[0:1], nPCLKB nQA, nQBx 80% 80% PCLKA[0:1], PCLKB VOD QA, QBx Frequency nQA, nQBx 20% 20% tR tF QA, QBx tPD Output Rise/Fall Time ICS854S54AKI REVISION A OCTOBER 30, 2012 Propagation Delay 7 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Parameter Measurement Information, continued nQA, nQBx VDD QA, QBx out t PW t PERIOD DC Input odc = t PW LVDS 100 x 100% out t PERIOD Output Duty Cycle/Pulse Width/Period Differential Output Voltage Setup VDD out DC Input LVDS out VOS/Δ VOS ä Offset Voltage Setup ICS854S54AKI REVISION A OCTOBER 30, 2012 8 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. VDD R1 1K CLK_IN PCLKx V_REF nPCLKx C1 0.1uF R2 1K Figure 1. Single-Ended Signal Driving Differential Input Recommendations for Unused Input and Output Pins Inputs: OUTputs: PCLK/nPCLK Inputs: LVDS Outputs For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached. LVCMOS Control Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. ICS854S54AKI REVISION A OCTOBER 30, 2012 9 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, LVDS and other differential signals. The differential signal must meet the VPP and VCMR input requirements. Figures 2A to 2D show interface examples for the PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V 2.5V R3 120Ω 2.5V Zo = 50Ω R4 120Ω Zo = 60Ω PCLK PCLK R1 100Ω Zo = 60Ω nPCLK nPCLK Zo = 50Ω SSTL LVPECL Input LVDS R1 120Ω Figure 2A. PCLK/nPCLK Input Driven by a 2.5V LVDS Driver R2 120Ω LVPECL Input Figure 2B. PCLK/nPCLK Input Driven by an SSTL Driver 2.5V 2.5V 2.5V 2.5V R3 250Ω 2.5V R4 250Ω C1 Zo = 50 Ω Zo = 50Ω R1 100Ω PCLK R3 100Ω PCLK Zo = 50Ω nPCLK R1 62.5Ω nPCLK C2 Zo = 50 Ω LVPECL Input LVPECL R2 62.5Ω 2.5V LVPECL Driv er R6 100Ω-180Ω Figure 2C. PCLK/nPCLK Input Driven by a 2.5V LVPECL Driver R7 100Ω-180Ω R2 100Ω Figure 2D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple 3.3V 3.3V 3.3V 3.3V 3.3V R1 50Ω Zo = 50Ω R2 50Ω Zo = 50Ω PCLK PCLK R1 100Ω Zo = 50Ω LVPECL Input LVPECL CML Built-In Pullup Input Figure 2E. PCLK/nPCLK Input Driven by a CML Driver ICS854S54AKI REVISION A OCTOBER 30, 2012 nPCLK Zo = 50Ω nPCLK CML R4 100Ω Figure 2F. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver 10 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER A Typical Application for the ICS854S54I Used to connect a multi-rate PHY with the Tx/Rx pins of an SFP Module. Problem Addressed: How to map the 2 Tx/Rx pairs of the multi-rate PHY to the single Tx/Rx pair on the SFP Module. MULTI-RATE PHY SFP MODULE Tx 100BaseFX Rx Rx ? Tx Tx 1000BaseX Rx Mode 1, 100BaseX Connected to SFP All lines are differential pairs, but drawn as single-ended to simplify the drawing. Bold red lines are active connections highlighting the signal path. . CLK_SELA = 0 MULTI-RATE PHY Tx PCLKA0 SFP MODULE 0 QA Rx PCLKA1 1 100BaseFX Rx PCLKB QB0 Tx QB1 CLK_SELB = 0 Tx ICS854S54I 1000BaseX Rx ICS854S54AKI REVISION A OCTOBER 30, 2012 11 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Mode 2, 100BaseX Connected to SFP All lines are differential pairs, but drawn as single-ended to simplify the drawing. Bold red lines . are active connections highlighting the signal path. CLK_SELA = 1 MULTI-RATE PHY SFP MODULE Tx PCLKA0 PCLKA1 100BaseFX Rx 0 QA Rx PCLKB Tx 1 QB0 QB1 CLK_SELB = 1 Tx ICS854S54I 1000BaseX Rx ICS854S54AKI REVISION A OCTOBER 30, 2012 12 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 3. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 3. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS854S54AKI REVISION A OCTOBER 30, 2012 13 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER 2.5V LVDS Driver Termination Figure 4 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LVDS driver, it is recommended to terminate the unused outputs. 2.5V 50Ω 2.5V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ICS854S54AKI REVISION A OCTOBER 30, 2012 14 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Power Considerations This section provides information on power dissipation and junction temperature for the ICS854S54I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S54I is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. • Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 82mA = 215.25mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature for is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.215W * 74.7°C/W = 101.1°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS854S54AKI REVISION A OCTOBER 30, 2012 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W 15 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Reliability Information Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W Transistor Count The transistor count for ICS854S54I is: 299 This device is pin and function compatible and a suggested replacement for ICS85454. ICS854S54AKI REVISION A OCTOBER 30, 2012 16 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Package Outline and Package Dimensions Package Outline - K Suffix for 16 Lead VFQFN Seating Plane (R ef.) A1 Index Area A3 N Anvil Singulation or Sawn Singulation Top View (Ref.) ND & NE Even (ND-1)x e L N e (Typ.) 2 If ND & NE are Even 1 2 E2 (NE -1)x e (Re f.) E2 2 b A D 0. 08 Chamfer 4x 0.6 x 0.6 max OPTIONAL (Ref.) e ND & NE Odd C Thermal Base D2 2 D2 C Bottom View w/Type A ID Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 RADIUS N N-1 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS854S54AKI REVISION A OCTOBER 30, 2012 17 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Ordering Information Table 9. Ordering Information Part/Order Number 854S54AKILF 854S54AKILFT Marking 454A 454A Package “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS854S54AKI REVISION A OCTOBER 30, 2012 18 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER Revision History Sheet Rev Table Page T9 1 10 18 A Description of Change Date Deleted HiperClockS Logo. Added CML to 3rd bullet. Added figures 2E and 2F. Deleted quantity from tape and reel. ICS854S54AKI REVISION A OCTOBER 30, 2012 19 10/30/12 ©2012 Integrated Device Technology, Inc. ICS854S54I Data Sheet DUAL 2:1 and 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. All rights reserved.