8633AF-01LF

ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER GENERAL DESCRIPTION FEATURES The ICS8633-01 is a high performance 1-to-3 Differential-to-3.3V LVPECL Zero Delay Buffer. The ICS8633-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. Utilizing one of the outputs as feedback to the PLL, output frequencies up to 700MHz can be regenerated with zero delay with respect to the input. Dual reference clock inputs support redundant clock or multiple reference applications. • Three differential 3.3V LVPECL outputs • Selectable differential clock inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • External feedback for “zero delay” clock regeneration • Cycle-to-cycle jitter: 25ps (maximum) • Output skew: 25ps (maximum) • PLL reference zero delay: 50ps ± 100ps • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request • Available in both standard and lead-free RoHs-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT PLL_SEL CLK0 nCLK0 CLK1 nCLK1 ÷4, ÷8 Q0 nQ0 PLL_SEL VCC SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR VCC nFB_IN FB_IN VEE 0 Q1 nQ1 0 1 Q2 nQ2 1 PLL CLK_SEL FB_IN nFB_IN 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCA VEE VEE VCCO VCCO Q2 nQ2 Q1 nQ1 Vcco Vcco Q0 nQ0 VEE ICS8633-01 SEL0 28-Lead, 209-MIL SSOP 5.3mm x 10.2mm x 1.75mm body package F Package Top View SEL1 MR 8633AF-01 1 2 3 4 www.idt.com 1 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 PLL_SEL Input 2, 11 VCC Power Pullup Description Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. Core supply pins. 3 SEL0 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 4 SEL1 Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 5 CLK0 Input Pulldown Non-inver ting differential clock input. 6 nCLK0 Input 7 CLK1 Input Pullup Inver ting differential clock input. 8 nCLK1 Input Pullup 9 CLK_SEL Input Pulldown 10 MR Input 12 nFB_IN Input 13 14, 15, 26, 27 16, 17 18, 19, 24, 25 20, 21 FB_IN Input VEE Power Negative supply pins. nQ0, Q0 Output Differential output pair. LVPECL interface levels. VCCO Power Output supply pins. nQ1, Q1 Output Differential output pair. LVPECL interface levels. 22, 23 nQ2, Q2 Output Differential output pair. LVPECL interface levels. 28 VCCA Power Analog supply pin. Pulldown Non-inver ting differential clock input. Inver ting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1, nCLK1. LVCMOS / LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx to go Pulldown high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pullup Feedback input to phase detector for regenerating clocks with "zero delay". Pulldown Feedback input to phase detector for regenerating clocks with "zero delay". NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. CONTROL INPUT FUNCTION TABLE Reference Frequency Range (MHz)* Outputs PLL_SEL = 1 PLL Enable Mode Q0:Q2, nQ0:nQ2 250 - 700 ÷1 0 0 ÷4 1 ÷4 Inputs SEL1 SEL0 0 0 TABLE 3B. PLL BYPASS FUNCTION TABLE Inputs SEL1 SEL0 Outputs PLL_SEL = 0 PLL Bypass Mode Q0:Q2, nQ0:nQ2 0 1 125 - 350 ÷1 0 1 0 62.5 - 175 ÷1 1 0 ÷4 ÷1 1 1 ÷8 1 1 31.25 - 87.5 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. 8633AF-01 www.idt.com 2 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 49°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 VCCO Output Supply Voltage 3.465 V IEE Power Supply Current 150 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Maximum Units 2 Typical VCC + 0.3 V -0.3 0.8 V SEL0, SEL1, CLK_SEL, MR VCC = VIN = 3.465V 150 µA PLL_SEL VCC = VIN = 3.465V 5 µA SEL0, SEL1, CLK_SEL, MR VCC = 3.465V, VIN = 0V -5 µA PLL_SEL VCC = 3.465V, VIN = 0V -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current Test Conditions Minimum VCC = VIN = 3.465V CLK0, CLK1, FB_IN nCLK0, nCLK1, nFB_IN VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V -5 nCLK0, nCLK1, nFB_IN VCC = 3.465V, VIN = 0V -150 Input Low Current VPP Peak-to-Peak Input Voltage Maximum Units 150 µA 5 CLK0, CLK1, FB_IN IIL Typical 0.15 µA 1.3 VCMR Common Mode Input Voltage; NOTE 1, 2 VEE + 0.5 VCC - 0.85 NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8633AF-01 www.idt.com 3 µA µA V V REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions Minimum VCCO - 1.4 Typical VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol fIN Parameter Input Frequency CLK0, nCLK0, CLK1, nCLK1 Test Conditions Minimum PLL_SEL = 1 31.25 Typical PLL_SEL = 0 Maximum Units 700 MHz 700 MHz Maximum Units 700 MHz 4.9 ns 150 ps 25 ps 25 ±50 ps ps TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 PLL Reference Zero Delay; NOTE 2, 4 Output Skew; NOTE 3, 4 t(Ø) t sk(o) t jit(cc) t jit(θ) tL Test Conditions Minimum PLL_SEL = 0V, ƒ ≤ 700MHz 2.8 PLL_SEL = 3.3V -50 Cycle-to-Cycle Jitter ; NOTE 4, 6 Phase Jitter ; NOTE 4, 5, 6 50 1 ms 700 ps odc Output Duty Cycle 47 53 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Phase jitter is dependent on the input source used. NOTE 6: Characterized at VCO frequency of 622MHz. % tR / tF 8633AF-01 PLL Lock Time Typical Output Rise/Fall Time 20% to 80% @ 50MHz www.idt.com 4 300 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCA, VCCO Qx V CC SCOPE nCLK0, nCLK1 LVPECL V VEE V Cross Points PP nQx CMR CLK0, CLK1 -1.3V ± 0.165V VEE DIFFERENTIAL INPUT LEVEL nQx nQ0:nQ2 Qx Q0:Q2 ➤ nQy tcycle tcycle n+1 ➤ 3.3V OUTPUT LOAD AC TEST CIRCUIT ➤ n ➤ Qy t jit(cc) = tcycle n –tcycle n+1 t sk(o) 1000 Cycles OUTPUT SKEW CYCLE-TO-CYCLE JITTER nQ0:nQ2 80% 80% Q0:Q2 VSW I N G Clock Outputs t PW 20% 20% tR t tF odc = PERIOD t PW x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD nCLK0, nCLK1 VOH CLK0, CLK1 nCLK0, nCLK1 VOL VOH nFB_IN CLK0, CLK1 nQ0:nQ2 FB_IN VOL ➤ ➤ t (Ø) t jit(Ø) = t (Ø) — t (Ø) mean = Phase Jitter Q0:Q2 tPD t (Ø) mean = Static Phase Offset (where t (Ø) is any random sample, and t (Ø) mean is the average of the sampled cycles measured on controlled edges) PROPAGATION DELAY 8633AF-01 PHASE JITTER & STATIC PHASE OFFSET www.idt.com 5 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8633-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10 μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLKx V_REF nCLKx C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8633AF-01 www.idt.com 6 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 R2 50 R2 50 R3 50 FIGURE 3A. CLK/nCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 3B. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V Zo = 50 Ohm HiPerClockS Input R3 125 3.3V R4 125 Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Zo = 50 Ohm Receiv er R2 84 FIGURE 3C. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 8633AF-01 nCLK FIGURE 3D. CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER www.idt.com 7 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 8633AF-01 125Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.idt.com 8 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER APPLICATION SCHEMATIC EXAMPLE Figure 5 shows an example of ICS8633-01 application schematic. The CLK/nCLK input can be driven by several types of differential input levels. In this example, the input is driven by a 3.3V LVPECL driver. For the LVPECL output drivers, a termination example is shown in this schematic. Additional termination approaches are shown in the LVPECL Termination Application Note. VCC R7 VCCA Zo = 50 Ohm 10 + C16 10u VCC U1 PLL_SEL 3.3V SEL0 SEL1 Zo = 50 Ohm Zo = 50 Ohm CLK_SEL 3.3V PECL Driv er R8 50 R9 50 VCC RU2 SP Zo = 50 Ohm - ICS8633-01 PLL_SEL VCC SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR VCC nFB_IN FB_IN VEE LVPECL_input VCCA VEE VEE VCCO VCCO Q2 nQ2 Q1 nQ1 VCCO VCCO Q0 nQ0 VEE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R5 50 VCCO R4 50 Output Termination Example R6 50 R10 50 RU3 1K RU4 1K RU5 SP CLK_SEL PLL_SEL SEL0 SEL1 RD2 1K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C11 0.01u RD3 SP RD4 SP R2 50 R1 50 Bypass capacitor located near the power pins VCC=3.3V R3 50 (U1-2) VCC C1 0.1uF RD5 1K VCCO=3.3V (U1-11) C6 0.1uF (U1-18) C2 0.1uF VCCO (U1-19) C4 0.1uF (U1-24) C5 0.1uF (U1-25) C7 0.1uF SP = Spare Footprint FIGURE 5. ICS8633-01 LVPECL ZERO DELAY BUFFER SCHEMATIC EXAMPLE 8633AF-01 www.idt.com 9 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8633-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8633-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 150mA = 519.75mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 30mW = 90mW Total Power_MAX (3.465V, with all outputs switching) = 519.75mW + 90mW = 609.75mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.610W * 36°C/W = 91.96°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 28-PIN SSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 8633AF-01 0 200 500 49°C/W 36°C/W 30°C/W www.idt.com 10 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V – 0.9V CCO_MAX ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V ))/R ] * (V OH_MAX CCO_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.2mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8633AF-01 www.idt.com 11 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD SSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 49°C/W 36°C/W 30°C/W TRANSISTOR COUNT The transistor count for ICS8633-01 is: 2969 8633AF-01 www.idt.com 12 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER PACKAGE OUTLINE - F SUFFIX FOR 28 LEAD SSOP TABLE 9. PACKAGE DIMENISIONS SYMBOL Millimeters Minimum N Maximum 28 A A1 2.00 0.05 A2 1.65 1.85 b 0.22 0.38 c 0.09 0.25 D 9.90 10.50 E 7.40 8.20 E1 5.00 e 5.60 0.65 BASIC L 0.55 0.95 α 0° 8° Reference Document: JEDEC Publication 95, MO-150 8633AF-01 www.idt.com 13 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8633AF-01 ICS8633AF-01 28 Lead SSOP Tube 0°C to 70°C 8633AF-01T ICS8633AF-01 28 Lead SSOP 1000 Tape & Reel 0°C to 70°C 8633AF-01LF ICS8633AF-01LF 28 Lead "Lead-Free" SSOP Tube 0°C to 70°C 8633AF-01LFT ICS8633AF-01LF 28 Lead "Lead-Free" SSOP 1000 Tape & Reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 8633AF-01 www.idt.com 14 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER REVISION HISTORY SHEET Rev Table Page B T10 14 16 8633AF-01 Description of Change Updated datasheet's header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. www.idt.com 15 Date 8/2/10 REV. B AUGUST 2, 2010 ICS8633-01 1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY BUFFER We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 Sales Tech Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 netcom@idt.com © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA 8633AF-01 www.idt.com 16 REV. B AUGUST 2, 2010