864S004AKILFT

PRELIMINARY ICS864S004I LVDS ZERO DELAY BUFFER w/ JITTER ATTENUATION FOR VIDEO APPLICATIONS General Description Features The ICS864S004I is Zero-Delay Buffer with four differential LVDS output pairs, and uses external HiPerClockS™ feedback for “zero delay” clock regeneration. Another feature of the device is the ability to select different bandwidth modes during normal operation to allow for additional clock jitter attenuation. • Four LVDS differential output pairs, and one feedback output pair • One differential clock input pair PCLK, nPCLK can accept the following differential input levels: LVDS, LVPECL, CML, SSTL • • • • • Maximum output frequency: 333.33MHz • • • External feedback for “zero delay” clock regeneration ICS The output frequency range is specified to include the most common video rates used in professional video systems. With a wide frequency range, the ICS864S004I is ideal for use in video applications where zero-delay, low skew and jitter attenuation are critical factors. VCO range: 1.2GHz – 2GHz Cycle-to-cycle jitter: TBD 3.3V operating supply voltage Two bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages VDD GND nc MR F_SEL0 F_SEL1 PLL_BYPASS F_SEL2 Pin Assignment 32 31 30 29 28 27 26 25 BW_SEL 1 24 Q0 VDDA 2 23 nQ0 VDD 3 22 Q1 nc 4 21 nQ1 20 nPCLK 6 19 nQ2 SE_CLK 7 18 Q3 nc 8 17 nQ3 VDD GND FB_OUT nFB_IN nFB_OUT 10 11 12 13 14 15 16 FB_IN 9 CLK_SEL 5 Q2 GND PCLK 32-Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT™ / ICS™ LVDS ZERO DELAY BUFFER 1 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Block Diagram 50kHz or 1MHz BW_SEL Pulldown Q0 CLK_SEL Pullup nQ0 Q1 PCLK nPCLK Pulldown 1 Pullup/Pulldown 1 Phase Detector SE_CLK Pulldown VCO Output Divider nQ1 Q2 (center @1.728GHZ) nQ2 0 0 Q3 nQ3 FB_IN Pulldown nFB_IN Pullup/Pulldown F_SEL[0:2] Pulldown FB_OUT 3 nFB_OUT PLL_BYPASS Pulldown MR Pulldown IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 2 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Table 1. Pin Descriptions Number Name Type Description 1 BW_SEL Input 2 VDDA Power Analog supply pin. 3, 16, 25 VDD Power Core supply pins. 4, 8, 27 nc Unused 5 PCLK Input Pulldown Non-inverting differential clock input. LVPECL interface levels. 6 nPCLK Input Pullup/ Pulldown Inverting differential clock input. VDD/2 default when left floating. LVPECL interface levels. 7 SE_CLK Input Pulldown Single-ended clock input. 9, 15, 26 GND Power 10 CLK_SEL Input Pullup Selects the reference clock. When LOW selects SE_CLK as clock source. When HIGH selects PCLK, nPCLK as clock source. LVCMOS/LVTTL interface levels. 11 FB_IN Input Pulldown Non-inverting feedback input to phase detector for regenerating clocks with “zero delay”. Connect to FB_OUT. 12 nFB_IN Input Pullup/ Pulldown Inverting feedback input to phase detector for regenerating clocks with “zero delay”. Connect to nFB_OUT. 13, 14 nFB_OUT, FB_OUT Output Differential output pair. LVDS interface levels. 17, 18 nQ3, Q3 Output Differential output pair. LVDS interface levels. 19, 20 nQ2, Q2 Output Differential output pair. LVDS interface levels. 21, 22 nQ1, Q1 Output Differential output pair. LVDS interface levels. 23, 24 nQ0, Q0 Output Differential output pair. LVDS interface levels. Pulldown Selects between 50kHz and 1MHz PLL bandwidth modes. When HIGH selects 1MHz PLL bandwidth. When LOW selects 50kHz PLL bandwidth. LVCMOS/LVTTL interface levels. No-Connect. Power suply ground. 28 MR Input Pulldown Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 29, 30, 31 F_SEL0, F_SEL1, F_SEL2 Input Pulldown Feedback divider control pins. LVCMOS/LVTTL interface levels. 32 PLL_BYPASS Input Pulldown Selects between the PLL and reference clock as the input to the dividers. When HIGH, selects reference clock. When LOW, selects PLL. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to intenal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT™ / ICS™ LVPECL ZERO DELAY BUFFER Test Conditions 3 Minimum Typical Maximum Units ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY Function Tables Table 3A. Feedback Divider Configuration Table F_SEL2 F_SEL1 F_SEL0 Feedback Divider 0 0 0 0 0 0 Input/Output Frequency (MHz) Minimum Maximum 64 18.75 31.25 1 32 37.5 62.5 1 0 24 50 83.33 0 1 1 12 100 166.67 1 0 0 6 200 333.33 1 0 1 1 1 0 1 1 1 Not Used Table 3B. PLL Bandwidth Configuration Table BW_SEL PLL Bandwidth 0 ~50kHz (default) 1 ~1MHz IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 4 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continous Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 37°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.16 3.3 VDD V IDD Power Supply Current 160 mA IDDA Analog Supply Current 16 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH VIL IIH IIL Test Conditions Minimum Input High Voltage 3.3V Input Low Voltage 3.3V Input High Current Input Low Current Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V SE_CLK, BW_SEL, F_SEL[0:2], MR, PLL_BYPASS VDD = VIN = 3.465V 150 µA CLK_SEL VDD = VIN = 3.465V 5 µA SE_CLK, BW_SEL, F_SEL[0:2], MR, PLL_BYPASS VDD = 3.465V, VIN = 0V -5 µA CLK_SEL VDD = 3.465V, VIN = 0V -150 µA IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 5 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY Table 4C. LVPECL Differential DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter IIH Input High Current IIL Test Conditions Minimum Typical Maximum Units 150 µA PCLK/nPCLK, FB_IN/nFB_IN VDD = VIN = 3.465V PCLK, FB_IN VDD = 3.465V, VIN = 0V -5 µA nPCLK, nFB_IN VDD = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage VCMR Common Mode Input Voltage; NOTE 1 0.3 1.0 V GND + 1.5 VDD V NOTE 1: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 380 mV ∆VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.22 V ∆VOS VOS Magnitude Change 50 mV Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Parameter Symbol fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tjit(per) Period Jitter, RMS; NOTE 1 t(Ø) Static Phase Offset, NOTE 1, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 18.75 20% to 80% Maximum Units 333.33 MHz TBD ps 15 ps TBD ps TBD ps 245 ps 50 % NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal when the PLL is locked and the input reference frequency is stable. IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 6 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Parameter Measurement Information nQx SCOPE VDD 3.3V±5% POWER SUPPLY + Float GND – Qx Qx VDDA nQy LVDS Qy nQx tsk(o) Output Skew VDD nQ0:nQ3, nFB_OUT nPCLK Q0:Q3, FB_OUT V Cross Points PP ➤ V CMR PCLK ➤ 3.3V Output Load AC Test Circuit ➤ tcycle n tcycle n+1 ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles GND Differential Input Level Cycle-to-Cycle Jitter Phase Noise Plot Noise Power nQ0:nQ3, nFB_OUT Q0:Q3, FB_OUT t PW t Phase Noise Mask odc = f1 Offset Frequency PERIOD t PW x 100% t PERIOD f2 RMS Jitter = Area Under the Masked Phase Noise Plot Output Duty Cycle/Pulse Width/Period RMS Period Jitter IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 7 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY Parameter Measurement Information, continued VOH 20% 20% tR nPCLK VOH 80% VOD Clock Outputs VOL tF PCLK VOL nFB_IN VOH FB_IN ➤ t(Ø) VOL ➤ 80% SE_CLK t(Ø) mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) LVDS Output Rise/Fall Time Static Phase Offset VDD VDD out 100 ➤ DC Input LVDS VOD/∆ VOD out out ➤ LVDS ➤ DC Input ➤ out ➤ VOS/∆ VOS ➤ Differential Output Voltage Setup IDT™ / ICS™ LVPECL ZERO DELAY BUFFER Offset Voltage Setup 8 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS864S004I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10µF and a 0.01µF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 2. Power Supply Filtering IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 9 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY LVPECL Clock Input Interface most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 Zo = 50Ω R2 50 Zo = 50Ω PCLK R1 100 PCLK Zo = 50Ω nPCLK Zo = 50Ω nPCLK HiPerClockS PCLK/nPCLK CML HiPerClockS PCLK/nPCLK CML Built-In Pullup Figure 3B. HiPerClockS PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 3A. HiPerClockS PCLK/nPCLK Input Driven by an Open Collector CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 R3 84 3.3V LVPECL Zo = 50Ω Zo = 50Ω C1 Zo = 50Ω C2 R4 84 PCLK PCLK Zo = 50Ω nPCLK nPCLK HiPerClockS Input LVPECL R1 84 R2 84 R5 100 - 200 R6 100 - 200 R1 125 R2 125 HiPerClockS PCLK/nPCLK Figure 3D. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 3C. HiPerClockS PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 2.5V R3 120 R4 120 Zo = 60Ω PCLK Zo = 60Ω nPCLK SSTL R1 120 R2 120 HiPerClockS PCLK/nPCLK Figure 3E. HiPerClockS PCLK/nPCLK Input Driven by an SSTL Driver IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 10 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Recommendations for Unused Input and Output Pins Inputs: Outputs: PCLK/nPCLK Inputs LVDS Outputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. SE_CLK Input For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the SE_CLK input to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 3.3V LVDS Driver Termination A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 11 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 12 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Power Considerations This section provides information on power dissipation and junction temperature for the ICS864S004I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS864S004I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (160mA + 16mA) = 609.84mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.610W * 42.7°C/W = 111°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 32 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 0 1 2.5 42.7°C/W 37.3°C/W 33.5°C/W 13 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY Reliability Information Table 7. θJA vs. Air Flow Table for a 32 Lead VFQFN θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 42.7°C/W 37.3°C/W 33.5°C/W Transistor Count The transistor count for ICS864S004I is: 1852 IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 14 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVPECL ZERO DELAY BUFFER PRELIMINARY Package Outline and Package Dimensions Package Outline - K Suffix for 32 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N L N e (Ty p.) 2 If N & N 1 Anvil Singula tion are Even 2 OR E2 (N -1)x e (Re f.) E2 2 To p View b A (Ref.) D Chamfer 4x 0.6 x 0.6 max OPTIONAL e N &N Odd 0. 08 C D2 2 Th er mal Ba se D2 C The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. Table 8. Package Dimensions JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 15 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I FEMTOCLOCKS™ LVPECL ZERO DELAY BUFFER PRELIMINARY Ordering Information Table 9. Ordering Information Part/Order Number 864S004AKI 864S004AKIT 864S004AKILF 864S004AKILFT Marking TBD TBD ICS4S004AIL ICS4S004AIL Package 32 Lead VFQFN 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN “Lead-Free” 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Tray 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVPECL ZERO DELAY BUFFER 16 ICS864S004AKI REV. A OCTOBER 10, 2007 ICS864S004I LVDS ZERO DELAY BUFFER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA