1:4, Differential-to-LVCMOS/LVTTL
Zero Delay Clock Generator
ICS87004
DATA SHEET
General Description
Features
The ICS87004 is a highly versatile 1:4 Differentialto-LVCMOS/LVTTL Clock Generator and a member of
HiPerClockS™
the HiPerClockS® family of High Performance Clock
Solutions from IDT. The ICS87004 has two selectable
clock inputs. The CLK0, nCLK0 and CLK1, nCLK1
pairs can accept most standard differential input levels. Internal bias
on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs
to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL
and can be configured as zero delay buffer, multiplier or divider and
has an input and output frequency range of 15.625MHz to 250MHz.
The reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the input
clock and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
•
•
•
Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
•
Internal bias on nCLK0 and nCLK1 to support LVCMOS/LVTTL
levels on CLK0 and CLK1 inputs
•
•
•
•
Output frequency range: 15.625MHz to 250MHz
•
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
•
•
•
•
•
•
•
•
Fully integrated PLL
ICS
Block Diagram
CLK1 Pulldown
nCLK1 Pullup/Pulldown
÷2, ÷4, ÷8, ÷16
÷32, ÷64, ÷128
0
Q0
1
Q1
0
1
PLL
Q2
CLK_SEL Pulldown
FB_IN Pulldown
CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration with
configurable frequencies
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 50ps (maximum)
Static phase offset: 50ps ± 125ps (3.3V ± 5%), CLK0/nCLK0
Full 3.3V or 2.5V output operating supply
5V tolerant inputs
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
PLL_SEL Pullup
CLK0 Pulldown
nCLK0 Pullup/Pulldown
Selectable CLK0/nCLK0 or CLK1/nCLK1 clock inputs
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q3
GND
Q0
VDDO
SEL0
SEL1
SEL2
SEL3
CLK_SEL
VDD
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q1
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
CLK1
nCLK1
VDDA
ICS87004
24-Lead TSSOP
7.8mm x 4.4mm x 0.925mm package body
G Package
Top View
SEL0 Pulldown
SEL1 Pulldown
SEL2 Pulldown
SEL3 Pulldown
MR Pulldown
ICS87004AG REVISION C DECEMBER 1, 2009
1
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
1, 12, 21
GND
Power
Type
Description
Power supply ground.
2, 20,
22, 24
Q0, Q3,
Q2, Q1
Output
Single-ended clock outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
3, 19, 23
VDDO
Power
Output supply pins.
4, 5,
6, 7
SEL0, SEL1,
SEL2, SEL3
Input
Pulldown
Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
8
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects differential CLK1, nCLK1. When LOW,
selects differential CLK0, nCLK0. LVCMOS/LVTTL interface levels.
9
VDD
Power
10
CLK0
Input
Pulldown
Non-inverting differential clock input.
11
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock input. VDD/2 default when left floating.
13
VDDA
Power
Core supply pin.
Analog supply pin.
14
nCLK1
Input
Pullup/
Pulldown
15
CLK1
Input
Pulldown
16
PLL_SEL
Input
Pullup
17
FB_IN
Input
Pulldown
Feedback input to phase detector for regenerating clocks with “Zero Delay.”
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
18
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS / LVTTL interface levels.
Inverting differential clock input. VDD/2 default when left floating.
Non-inverting differential clock input.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation
Capacitance (per output)
ROUT
Output Impedance
ICS87004AG REVISION C DECEMBER 1, 2009
Test Conditions
Minimum
Typical
Maximum
Units
VDD, VDDO = 3.465V
23
pF
VDD, VDDO = 2.625V
17
pF
12
Ω
5
2
7
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Function Tables
Table 3A. PLL Enable Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)
Q[0:3]
0
0
0
0
125 - 250
÷1
0
0
0
1
62.5 - 125
÷1
0
0
1
0
31.25 - 62.5
÷1
0
0
1
1
15.625 - 31.25
÷1
0
1
0
0
125 - 250
÷2
0
1
0
1
62.5 - 125
÷2
0
1
1
0
31.25 - 62.5
÷2
0
1
1
1
125 - 250
÷4
1
0
0
0
62.5 - 125
÷4
1
0
0
1
125 - 250
÷8
1
0
1
0
62.5 - 125
x2
1
0
1
1
31.25 - 62.5
x2
1
1
0
0
15.625 - 31.25
x2
1
1
0
1
31.25 - 62.5
x4
1
1
1
0
15.625 - 31.25
x4
1
1
1
1
15.625 - 31.25
x8
ICS87004AG REVISION C DECEMBER 1, 2009
3
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q[0:3]
0
0
0
0
÷8
0
0
0
1
÷8
0
0
1
0
÷8
0
0
1
1
÷16
0
1
0
0
÷16
0
1
0
1
÷16
0
1
1
0
÷32
0
1
1
1
÷32
1
0
0
0
÷64
1
0
0
1
÷128
1
0
1
0
÷4
1
0
1
1
÷4
1
1
0
0
÷8
1
1
0
1
÷2
1
1
1
0
÷4
1
1
1
1
÷2
ICS87004AG REVISION C DECEMBER 1, 2009
4
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
70°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
100
mA
IDDA
Analog Supply Current
16
mA
IDDO
Output Supply Current
6
mA
Table 4B. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Minimum
Typical
Maximum
Units
Core Supply Voltage
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
2.375
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
96
mA
IDDA
Analog Supply Current
15
mA
IDDO
Output Supply Current
6
mA
ICS87004AG REVISION C DECEMBER 1, 2009
Test Conditions
5
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Table 4C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
IIL
Test Conditions
Minimum
VDD = 3.3V
Typical
Maximum
Units
2
VDD + 0.3
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
SEL[0:3], MR,
FB_IN, CLK_SEL
VDD = VIN = 3.465V or 2.625V
150
µA
PLL_SEL
VDD = VIN = 3.465V or 2.625V
5
µA
SEL[0:3], MR,
FB_IN, CLK_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA
PLL_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
-150
µA
VDDO = 3.465V
2.6
V
VDDO = 2.625V
1.8
V
Input Low Current
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VDD = 3.465V or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.
Table 4D. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5% or 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
IIH
Input
High Current
CLK0/nCLK0,
CLK1/nCLK1
VDD = VIN = 3.465V or 2.625V
150
µA
Input
Low Current
CLK0, CLK1
VDD = 3.465V or 2.625V, VIN = 0V
-5
µA
IIL
nCLK0, nCLK1
VDD = 3.465V or 2.625V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage;
NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS87004AG REVISION C DECEMBER 1, 2009
6
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay;
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V, f ≤ 250MHz,
Qx ÷ 2
t(Ø)
Static Phase Offset;
NOTE 2, 4
CLK0, nCLK0
PLL_SEL = 3.3V,
fREF ≤ 167MHz, Qx ÷ 1
tsk(o)
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
CLK1, nCLK1
Minimum
Typical
Maximum
Units
15.625
250
MHz
5
6.2
ns
-75
50
175
ps
-190
-65
175
ps
PLL_SEL = 0V
40
50
ps
fOUT > 40MHz
30
45
ps
1
ms
800
ps
60
%
20% to 80%
400
40
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay;
NOTE 1
CLK0, nCLK0
CLK1, nCLK1
PLL_SEL = 0V, f ≤ 250MHz,
Qx ÷ 2
t(Ø)
Static Phase Offset;
NOTE 2, 4
CLK0, nCLK0
PLL_SEL = 2.5V,
fREF ≤ 167MHz, Qx ÷ 1
tsk(o)
Output Skew;
NOTE 3, 4
CLK0, nCLK0
CLK1, nCLK1
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
CLK1, nCLK1
Minimum
Typical
Maximum
Units
15.625
250
MHz
5.3
6.9
ns
-175
-25
125
ps
-290
-115
125
ps
PLL_SEL = 0V
40
45
ps
fOUT > 40MHz
35
45
ps
1
ms
700
ps
56
%
20% to 80%
400
44
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and
the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS87004AG REVISION C DECEMBER 1, 2009
7
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information
1.65V±5%
VDD,
VDDA,
VDDO
1.25V±5%
SCOPE
Qx
LVCMOS
SCOPE
VDD,
VDDA,
VDDO
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
2.5V Output Load AC Test Circuit
3.3V Output Load AC Test Circuit
VDD
V
DDO
Qx
2
nCLK[0:1]
V
V
Cross Points
PP
CMR
V
DDO
CLK[0:1]
2
tsk(o)
Qy
GND
Output Skew
Differential Input Level
V
V
DDO
DDO
2
DDO
2
➤
tcycle n
➤
VOH
CLK[0:1]
VOL
2
tcycle n+1
VOH
VDDO
➤
2
VOL
FB_IN
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
➤ t(Ø)
➤
V
Q[0:3]
nCLK[0:1]
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges.
Cycle-to-Cycle Jitter
ICS87004AG REVISION C DECEMBER 1, 2009
Static Phase Offset
8
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Parameter Measurement Information, continued
nCLK[0:1]
80%
80%
CLK[0:1]
Q[0:3]
20%
20%
tR
tF
Q[0:3]
VDDO
2
t
PD
Propagation Delay
Output Rise/Fall Time
V
DDO
2
Q[0:3]
t PW
t
odc =
PERIOD
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
ICS87004AG REVISION C DECEMBER 1, 2009
9
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS87004 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. VDD, VDDA and VDDO should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin. The 10Ω resistor can also be replaced by
a ferrite bead.
3.3V or 2.5V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS87004AG REVISION C DECEMBER 1, 2009
10
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
Differential
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
Differential
Input
LVPECL
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
Differential
Input
SSTL
R1
120
R2
120
Differential
Input
*Optional – R3 and R4 can be 0Ω
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
ICS87004AG REVISION C DECEMBER 1, 2009
11
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Reliability Information
Table 6. θJA vs. Air Flow Table for a 24 Lead TSSOP
θJA vs. Air Flow
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
70°C/W
63°C/W
60°C/W
Transistor Count
The transistor count for ICS87004 is: 2578
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 7. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS87004AG REVISION C DECEMBER 1, 2009
12
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Ordering Information
Table 8. Ordering Information
Part/Order Number
87004AG
87004AGT
87004AGLF
87004AGLFT
Marking
ICS87004AG
ICS87004AG
ICS87004AGLF
ICS87004AGLF
Package
24 Lead TSSOP
24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS87004AG REVISION C DECEMBER 1, 2009
13
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
Revision History Sheet
Rev
Table
Page
A
T8
13
Ordering Information Table - added Lead-Free marking.
6/16/04
A
T8
13
Ordering Information Table - corrected Lead-Free part number. Added Lead-Free note.
5/17/05
B
T5A
T5B
6
6
10
3.3V AC Characteristics Table - adjusted tPD parameter from 6ns max. to 6.2ns max.
2.5V AC Characteristics Table - adjusted tPD parameter from 6.7ns max. to 6.9ns max.
Added Recommendations for Unused Input and Output Pins section.
10/7/05
T4D
6
Differential DC Characteristics Table - updated NOTES 1, 2.
T5A, T5B
7
AC Characteristics Tables - Static Phase Offset, split CLKx into 2 rows. Specs changed for
CLK1/nCLK1. Added Thermal note.
11
Updated Differential Clock Input Interface section.
13
Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.
C
T8
Description of Change
Date
10/6/09
Converted datasheet format.
C
1
Features section - corrected output skew from 465ps ot 50ps (maximum)
ICS87004AG REVISION C DECEMBER 1, 2009
14
12/1/09
©2009 Integrated Device Technology, Inc.
ICS87004 Data Sheet
6024 Silver Creek Valley Road
San Jose, California 95138
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
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