8701CYILF

8701I Low Skew, ÷1, ÷2 Clock Generator Data Sheet GENERAL DESCRIPTION FEATURES The 8701I is a low skew, ÷1, ÷2 Clock Generator. The low impedance LVCMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines. • Twenty LVCMOS outputs, 7Ω typical output impedance • LVCMOS / LVTTL clock input • Maximum input frequency: 250MHz • Bank enable logic allows unused banks to be disabled in reduced fanout applications The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. • Bank skew: 200ps • Output skew: 250ps • Multiple frequency skew: 300ps • Part-to-part skew: 600ps The 8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the 8701I ideal for those clock distribution applications demanding well defined performance and repeatability. • 3.3V or mixed 3.3V input, 2.5V output operating supply BLOCK DIAGRAM PIN ASSIGNMENT • -40°C to 85°C ambient operating temperature • Other divide values available on request • Available in lead-free RoHS compliant package 48-Pin LQFP 7mm x 7mm x 1.4mm package body Y Package Top View ©2016 Integrated Device Technology, Inc 1 Revision C January 22, 2016 8701I Data Sheet TABLE 1. PIN DESCRIPTIONS Number 2, 5, 11, 26, 32, 35, 41, 44 7, 9, 18, 21, 28, 30, 37, 39, 46, 48 16, 20 25, 27, 29, 31, 33 34, 36, 38, 40, 42 43, 45, 47, 1, 3 4, 6, 8, 10, 12 22 Name Type Description VDDO Power Output supply pins. GND Power Power supply ground. VDD QA0, QA1, QA2, QA3, QA4 QB0, QB1, QB2, QB3, QB4 QC0, QC1, QC2, QC3, QC4 QD0, QD1, QD2, QD3, QD4 CLK Power Positive supply pins. Bank A outputs.LVCMOS / LVTTLinterface levels. Output 7Ω typical output impedance. Bank B outputs.LVCMOS / LVTTLinterface levels. Output 7Ω typical output impedance. Bank C outputs.LVCMOS / LVTTLinterface levels. Output 7Ω typical output impedance. Bank D outputs. LVCMOS / LVTTLinterface levels. Output 7Ω typical output impedance. Input Pulldown LVCMOS / LVTTL clock input. Controls frequency division for Bank D outputs. 13 DIV_SELD Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank C outputs. 14 DIV_SELC Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank B outputs. 23 DIV_SELB Input Pullup LVCMOS / LVTTLinterface levels. Controls frequency division for Bank A outputs. 24 DIV_SELA Input Pullup LVCMOS / LVTTLinterface levels. BANK_EN1, Enables and disables outputs by banks. Input Pullup 17, 19 LVCMOS / LVTTLinterface levels. BANK_EN0 Master Reset and output enable. When HIGH, output drivers are 15 nMR/OE Input Pullup enabled. Whe LOW, output drivers are in HiZ and dividers are reset. LVCMOS / LVTTLinterface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ©2016 Integrated Device Technology, Inc 2 Revision C January 22, 2016 8701I Data Sheet TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ CPD Power Dissipation Capacitance (per output) ROUT Output Impedance VDD, VDDO = 3.465V Units 15 pF Ω 7 TABLE 3. FUNCTION TABLE nMR/OE 0 Inputs BANK_EN1 BANK_EN0 X X DIV_SELx X QA0:QA4 Hi Z QB0:QB4 Hi Z Outputs QC0:QC4 Hi Z QD0:QD4 Hi Z Qx frequency zero 1 0 0 0 Active Hi Z Hi Z Hi Z fIN/2 1 1 0 0 Active Active Hi Z Hi Z fIN/2 1 0 1 0 Active Active Active Hi Z fIN/2 1 1 1 0 Active Active Active Active fIN/2 1 0 0 1 Active Hi Z Hi Z Hi Z fIN 1 1 0 1 Active Active Hi Z Hi Z fIN 1 0 1 1 Active Active Active Hi Z fIN 1 1 1 1 Active Active Active Active fIN ©2016 Integrated Device Technology, Inc 3 Revision C January 22, 2016 8701I Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol VDD Parameter Positive Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current ©2016 Integrated Device Technology, Inc Test Conditions 4 Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 Units V V 2.375 2.5 2.625 V 100 mA Revision C January 22, 2016 8701I Data Sheet TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Test Conditions Minimum Typical Maximum Units DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE 2 VDD + 0.3 V CLK 2 VDD + 0.3 V DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE -0.3 0.8 V CLK -0.3 1.3 V Input High Current DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE VDD = VIN = 3.465V 5 µA CLK VDD = VIN = 3.465V 150 µA Input Low Current DIV_SELA, DIV_SELB, DIV_SELC, DIV_SELD, BANK_EN0, BANK_EN1, nMR/OE VDD = 3.465V, VIN = 0V -150 µA CLK VDD = 3.465V, VIN = 0V -5 µA VDD = VDDO = 3.135V IOH = -36mA 2.6 V VDD = 3.135V, VDDO = 2.375 IOH = -27mA 1.8 V Output High Voltage Output Low Voltage ©2016 Integrated Device Technology, Inc VDD = VDDO = 3.135V IOL = 36mA 0.5 V VDD = 3.135V, VDDO = 2.375 IOL = 27mA 0.5 V 5 Revision C January 22, 2016 8701I Data Sheet TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Input Frequency Test Conditions Minimum Typical Maximum Units 250 MHz tpHL Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 tsk(b) Bank Skew; NOTE 2, 7 tsk(o) Output Skew; NOTE 3, 7 tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 tsk(pp) Part to Part Skew; NOTE 5, 7 Measured on rising edge at VDDO/2 tR Output Rise Time; NOTE 6 30% to 70% 200 900 ps tF Output Fall Time; NOTE 6 30% to 70% 200 900 ps tPW Output Pulse Width 0MHz ≤ f ≤ 200MHz tCYCLE/2 - 0.6 tCYCLE/2 tCYCLE/2 + 0.6 ns f = 200MHz 1.9 2.5 3.1 ns tpLH 0MHz ≤ f ≤ 200MHz 2.2 3.6 ns 0MHz ≤ f ≤ 200MHz 2.2 3.6 ns 200 ps 250 ps 300 ps 600 ps Measured on rising edge at VDDO/2 Output Enable Time; f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. NOTE 4 Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. tEN ©2016 Integrated Device Technology, Inc 6 ns ns Revision C January 22, 2016 8701I Data Sheet TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Input Frequency Test Conditions Minimum Typical Maximum Units 250 MHz tpHL Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low; NOTE 1 tsk(b) Bank Skew; NOTE 2, 7 tsk(o) Output Skew; NOTE 3, 7 tsk(w) Multiple Frequency Skew; NOTE 4, 7 Measured on rising edge at VDDO/2 Measured on rising edge at VDDO/2 tsk(pp) Part to Part Skew; NOTE 5, 7 Measured on rising edge at VDDO/2 tR Output Rise Time; NOTE 6 30% to 70% 200 900 ps tF Output Fall Time; NOTE 6 30% to 70% 200 900 ps tPW Output Pulse Width 0MHz ≤ f ≤ 200MHz tCYCLE/2 - 0.6 tCYCLE/2 tCYCLE/2 + 0.6 ns f = 200MHz 1.9 2.5 3.1 ns tpLH 0MHz ≤ f ≤ 200MHz 2.4 3.7 ns 0MHz ≤ f ≤ 200MHz 2.4 3.7 ns 225 ps 250 ps 300 ps 650 ps Measured on rising edge at VDDO/2 Output Enable Time; f = 10MHz 6 NOTE 6 Output Disable Time; tDIS f = 10MHz 6 NOTE 6 All parameters measured at 200MHz unless noted otherwise. NOTE 1: Measured from the VDD input crossing point to the output at VDDO/2. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions. NOTE 4 Defined as skew across banks of outputs operating at different frequency with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. tEN ©2016 Integrated Device Technology, Inc 7 ns ns Revision C January 22, 2016 8701I Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW PART-TO-PART SKEW BANK SKEW (where X denotes outputs in the same bank) PROPAGATION DELAY OUTPUT DUTY CYCLE/PULSE WIDTH/PERIIOD OUTPUT RISE/FALL TIME ©2016 Integrated Device Technology, Inc 8 Revision C January 22, 2016 8701I Data Sheet APPLICATION INFORMATION Driver Termination For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. POWER CONSIDERATIONS For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer. ©2016 Integrated Device Technology, Inc 9 Revision C January 22, 2016 8701I Data Sheet RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 500 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8701I is: 1743 ©2016 Integrated Device Technology, Inc 10 Revision C January 22, 2016 8701I Data Sheet PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BBC MINIMUM NOMINAL N MAXIMUM 48 A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.50 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.50 Ref. e 0.50 BASIC L 0.45 0.60 θ 0° -- 7° ccc -- -- 0.08 0.75 Reference Document: JEDEC Publication 95, MS-026 ©2016 Integrated Device Technology, Inc 11 Revision C January 22, 2016 8701I Data Sheet TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8701CYILF ICS8701CYILF 48 lead “Lead Free” LQFP Tray 0°C to +70°C 8701CYILFT ICS8701CYILF 48 lead “Lead Free” LQFP Tape and Reel 0°C to +70°C ©2016 Integrated Device Technology, Inc 12 Revision C January 22, 2016 8701I Data Sheet REVISION HISTORY SHEET Rev A Table 1 5A 5B T2 B Page 2 5 7 8 - 10 10 11 12 1 3 8 9 T7 12 C T7 12 14 C T7 1 12 Description of Change Date Updated format throughout the datasheet. Renamed LVCMOS_CLK to CLK. Renamed VDDI to VDD. Pin Description Table, revised nMR/OE description. 3.3V AC Characteristics Table, updated notes. 3.3V/2.5V Characteristics Table, updated notes. Updated drawings. Added Power Consideration and Driver Termination notes. Added Reliability Information and Transistor Count. Revised Package Outline. 8/19/02 Features Section - added lead-free bullet. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. Parameter Measurement Information - added Bank Skew diagram. Application Information - added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free part number, marking and note. Updated format throughout the data sheet. Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. Removed ICS from the part number where needed. Features Section - removed reference to leaded package. Ordering Information - removed quantity for tape and reel. Deleted LF note below the table. Updated header and footer. ©2016 Integrated Device Technology, Inc 13 2/28/06 7/27/10 1/22/16 Revision C January 22, 2016 8701I Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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