87021I
÷1/÷2 Differential-to-LVCMOS/LVTTL
Clock Generator
Data Sheet
GENERAL DESCRIPTION
FEATURES
The 87021I is a high performance ÷1/÷2 Differential-to-LVCMOS/
LVTTL Clock Generator and a member of the family of High
Performance Clock Solutions from IDT. The CLK, nCLK pair can
accept most standard differential input levels. Guaranteed partto-part skew characteristics make the 87021I ideal for those clock
distribution applications demanding well defined performance
and repeatability.
• Two single-ended LVCMOS/LVTTL outputs
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 250MHz
• Additive phase jitter, RMS: 0.18ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 450ps (maximum)
• Propagation delay: 3.4ns (maximum)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Availalbe in lead-free (RoHS 6) package
BLOCK DIAGRAM
PIN ASSIGNMENT
÷1
0
R ÷2
1
CLK
nCLK
CLK
nCLK
MR
F_SEL
Q0
Q1
8
7
6
5
VDD
Q0
Q1
GND
87021I
MR
8-Lead SOIC
3.90mm x 4.90mm x 1.375mm package body
M Package
Top View
F_SEL
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87021I Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
CLK
Input
Type
2
nCLK
Input
Description
Pulldown Non-inverting differential clock input.
Pullup
Inverting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal dividPulldown
ers and the outputs are enabled. LVCMOS / LVTTL interface levels. See
Table 3.
Selects divider value for Qx outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
3
MR
Input
4
F_SEL
Input
5
GND
Power
Power supply ground.
6
Q1
Output
Singled-ended output. LVCMOS/LVTTL interface levels.
7
Q0
Output
Singled-ended output. LVCMOS/LVTTL interface levels.
8
VDD
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance
(per output)
RPULLUP
Input Pullup Resistor
RPULLDOWN
Input Pulldown Resistor
ROUT
Output Impedance
©201Igrated Device Technology, Inc
Test Conditions
VDD = 3.465V
VDD = 2.625V
VDD = 3.465V
2
Minimum
Typical
Maximum
Units
4
pF
24
pF
16
pF
51
kΩ
51
kΩ
9
Ω
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87021I Data Sheet
TABLE 3. FUNCTION TABLE
MR
F_SEL
Divide Value
1
X
Reset: Q0, Q1 outputs low
0
0
÷1
0
1
÷2
CLOCK
MR
÷1
CLOCK
MR
÷2
FIGURE 1. TIMING DIAGRAM
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87021I Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
103°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Positive Supply Voltage
IDD
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
60
mA
Units
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
Positive Supply Voltage
IDD
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
2.375
2.5
2.625
V
35
mA
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
VOH
Output High Voltage; NOTE 1
VDD = 3.465V
2.6
VOL
Output Low Voltage; NOTE 1
VDD = 3.465V or 2.625V
Typical
1.3
-0.3
Maximum
Units
VDD + 0.3
V
0.7
V
150
µA
µA
V
0.5
V
Maximum
Units
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information section,
“3.3V Output Load Test Circuit” diagram.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
1.1
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.5
V
IIH
Input High Current
VDD = VIN = 2.625V
150
µA
IIL
Input Low Current
VDD = 2.625V, VIN = 0V
-5
VOH
Output High Voltage; NOTE 1
VDD = 2.625V
1.8
VOL
Output Low Voltage; NOTE 1
VDD = 2.625V
µA
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information section,
“2.5V Output Load Test Circuit” diagram.
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87021I Data Sheet
TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%
Symbol
Parameter
OR
VDD = 2.5V±5%, TA = -40°C TO 85°C
Maximum
Units
CLK
VDD = VIN = 3.465V or 2.625V
Test Conditions
150
µA
nCLK
VDD = VIN = 3.465V or 2.625V
5
µA
CLK
VDD = 3.465V or 2.625V, VIN = 0V
-5
µA
nCLK
VDD= 3.465V or 2.625V, VIN = 0V
-150
µA
IIH
Input High Current
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage;
NOTE 1
Minimum
Typical
0.15
1.3
V
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tPD
tjit
Test Conditions
Propagation Delay;
CLK to Qx
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Minimum
Typical
2.1
250MHz, Integration Range:
12kHz – 20MHz
Maximum
Units
250
MHz
3.4
ns
0.18
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
450
ps
tsk(o)
Output Skew; NOTE 3, 4
50
ps
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle;
NOTE 5
20% to 80%
250
700
ps
Fout ≤ 133MHz
45
55
%
Fout > 133MHz
40
60
%
Maximum
Units
250
MHz
3.4
ns
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 5: Output Duty Cycle assuming 50% input duty cycle.
TABLE 5B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tPD
tjit
Test Conditions
Propagation Delay;
CLK to Qx
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Minimum
Typical
2.7
250MHz, Integration Range:
12kHz – 20MHz
0.3
ps
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
450
ps
tsk(o)
Output Skew; NOTE 3, 4
25
ps
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle;
NOTE 5
20% to 80%
250
700
ps
Fout ≤ 133MHz
45
55
%
Fout > 133MHz
40
60
%
For NOTES, please see above Table 5A.
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87021I Data Sheet
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase
noise is defined as the ratio of the noise power present in a 1Hz
band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency domain,
we get a better understanding of its effects on the desired application
over the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 250MHz
SSB PHASE NOISE dBc/HZ
(12kHz to 20MHz) = 0.18ps typical
OFFSET FROM CARRIER FREQUENCY (HZ)
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87021I Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEW
OUTPUT SKEW
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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87021I Data Sheet
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/
R1 = 0.609.
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LVCMOS OUTPUTS
All unused LVCMOS output can be left floating. There should be
no trace attached.
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87021I Data Sheet
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 2A to 2E show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm
the driver termination requirements. For example in Figure 2A, the
input termination applies for IDT HiPerClockS LVHSTL drivers. If
you are using an LVHSTL driver from another vendor, use their
termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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87021I Data Sheet
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
123°C/W
103°C/W
200
500
110°C/W
94°C/W
99°C/W
89°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 87021I is: 414
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87021I Data Sheet
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUN
N
A
MAXIMUM
8
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BASIC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
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87021I Data Sheet
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
87021AMILF
87021AIL
8 lead “Lead Free” SOIC
Tube
-40°C to +85°C
87021AMILFT
87021AIL
8 lead “Lead Free” SOIC
Tape and Reel
-40°C to +85°C
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87021I Data Sheet
REVISION HISTORY SHEET
Rev
Table
Page
B
T2
2
B
B
T8
1
1
12
8
12
Description of Change
Date
Pin Characteristics Table - added ROUT row.
8/26/08
Removed ICS from the part numbers where needed.
General Description - Removed the ICS chip and HiPerClockS.
Features Section - Removed reference to lead free packages.
Ordering Information - removed quantity from tape and reel. Deleted LF note
below the table.
Updated header and footer.
1-26-16
Changed Shipping Packaging from "Tray" to "Tube".
©2016 Integrated Device Technology, Inc
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