870931ARI-01LFT

870931I-01 LVCMOS Clock Generator General Description Features The 870931I-01 is an LVCMOS clock generator that uses an internal phase lock loop (PLL) for frequency multiplication and to lock the low-skew outputs to the reference clock. The device offers six outputs. The PLL loop filter is completely internal and does not require external components. Several combinations of the PLL feedback and a divide-by-2 (controlled by FREQ_SEL) allow applications to optimize frequency generation over a wide range of input reference frequencies. The PLL can also be disabled by the PLL_EN control signal to allow for low frequency or DC testing. The 870931I-01 device is a member of the family of high performance clock solutions from IDT. • • • • • • • • • • • • • • Pin Assignment GND OE/nRST FEEDBACK AVDD VDD AGND SYNC FREQ_SEL GND Q0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Data Sheet Single-ended input reference clock Six single-ended clock outputs Internal PLL does not require external loop filter components 5V tolerant inputs Maximum output frequency: 80MHz, (Q0:Q4 outputs) Maximum output frequency: 40MHz, (Q/2 output) LVCMOS interface levels for all inputs and outputs PLL disable feature for low-frequency testing Output drive capability: ±24mA Output skew: 300ps (maximum), Q0:Q4 and Q/2 Full 3.3V supply voltage Available in lead-free packages -40°C to 85°C ambient operating temperature Fully pin and function compatible with the IDTQS5LV931 (including 50, 66 and 80MHz options) Q4 Q/2 GND Q3 VDD Q2 GND PLL_EN GND Q1 870931I-01 20-Lead QSOP, 150Mil 3.9mm x 8.65mm x 1.5mm package body R Package Top View Block Diagram 1 0 SYNC 1 fREF PLL fVCO 20MHz - 160MHz ÷2 ÷2 Q0 Q1 0 Q2 Q3 Q4 FEEDBACK ÷4 Q/2 PLL_EN FREQ_SEL ©2016 Integrated Device Technology, Inc 1 Revision B April 25, 2016 870931I-01 Data Sheet Table 1. Pin Descriptions Number Name Type Description 1, 9, 12, 14, 18 GND Power Power supply ground. 2 OE/nRST Input Output enable and asynchronous reset. Resets all outputs. Logic LOW, the outputs are in high-impedance state. Logic HIGH enables all outputs. LVCMOS/LVTTL interface levels. 3 FEEDBACK Input PLL feedback input which is connected to one of the clock outputs to close the PLL feedback loop. LVCMOS/LVTTL interface levels. 4 AVDD Power Positive power supply for the PLL. 5, 16 VDD Power Positive power supply pins. 6 AGND Power Power supply ground for the PLL. 7 SYNC Input Single-ended reference clock input. LVCMOS/LVTTL interface levels. 8 FREQ_SEL Input Frequency select. Logic LOW level inserts a divide-by-2 into the PLL output and feedback path. Logic HIGH inserts a divide-by-1 into the PLL output and feedback path. LVCMOS/LVTTL interface levels. 10, 11, 15, 17, 20 Q0, Q1, Q2, Q3, Q4 Output 13 PLL_EN Input 19 Q/2 Output Single-ended clock outputs. LVCMOS/LVTTL interface levels. PLL enable. Enable and disables the PLL. Logic HIGH enables the PLL. Logic LOW disables the PLL and the input reference signal is routed to the output dividers (PLL bypass). LVCMOS/LVTTL interface levels. Single-ended clock output. LVCMOS/LVTTL interface levels. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance ROUT Output Impedance ©2016 Integrated Device Technology, Inc Test Conditions VDD = AVDD = 3.6V 2 Minimum Typical Maximum Units 4 pF 330 pF 11  Revision B April 25, 2016 870931I-01 Data Sheet Device Configuration The 870931I-01 requires a connection to one of the clock outputs to the FEEDBACK input to close the PLL feedback path. The selection of the output (output divider) for PLL feedback will impact the device configuration and input to output frequency ratio and frequency ranges. See Table 3D for details. Function Tables Table 3A. OE/nRST Mode Configuration Table Input OE/nRST Operation 0 Device is reset and the outputs Q0:Q4 and Q/2 are in high-impedance state. This control is asynchronous. 1 Outputs are enabled. Table 3B. FREQ_SEL Mode Configuration Table Input FREQ_SEL Operation 0 The VCO output is frequency-divided by 2. This setting allows for a lower input frequency range. See also table 3D for available frequency ranges. 1 The VCO output is frequency-divided by 1. This setting allows for a higher input frequency range. See also table 3D for available frequency ranges. Table 3C. PLL_EN Mode Configuration Table Input PLL_EN Operation 0 The PLL is bypassed. The input reference clock is routed to the output dividers for low-frequency board test purpose. The PLL-related AC specifications do not apply in PLL bypass mode. 1 The PLL is enabled and locks to the input reference signal. Table 3D. Frequency Configuration Table Outputs Used for PLL Feedback Q0, Q1, Q2, Q3 or Q4 Input Frequency Range (MHz) Output Frequency Range (MHz) and Output-to-Input Frequency Multiplication Factor FREQ_SEL SYNC Q[0:4] Q/2 0 5 - 40 5 - 40 (1x) 2.5 - 20 (0.5x) 1 10 - 80 10 - 80 (1x) 5 - 40 (0.5x) 0 2.5 - 20 5 - 40 (2x) 2.5 - 20 (1x) 1 5 - 40 10 - 80 (2x) 5 - 40 (1x) Q/2 ©2016 Integrated Device Technology, Inc 3 Revision B April 25, 2016 870931I-01 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 72.3°C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD, AVDD Positive Supply Voltage IDDQ Quiescent Power Supply Current Minimum Typical Maximum Units 3.0 3.3 3.6 V 5 mA Maximum Units VDD = AVDD = Max., OE/nRST = 0, SYNC =0, All Outputs Open Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter Test Conditions VIH Input High Voltage 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V IIH Input High Current SYNC, OE/nRST, FEEDBACK, PLL_EN, FREQ_SEL VDD = VIN = 3.3V 5 µA IIL Input Low Current SYNC, OE/nRST, FEEDBACK, PLL_EN, FREQ_SEL VDD = 3.3V, VIN = 0V -5 µA VOH Output High Voltage: Q0:Q4, Q/2 IOH = -24 mA 2.6 V VOL Output Low Voltage Q0:Q4, Q/2 IOL = 24 mA 0.5 V IOZ Output Leakage Current Q0:Q4, Q/2 OE/nRST = 0, VOUT = 0V or VDD, VDD = 3.6V ±5 µA ©2016 Integrated Device Technology, Inc 4 Minimum Typical Revision B April 25, 2016 870931I-01 Data Sheet Table 5. AC Electrical Characteristics, VDD = AVDD = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol fREF Parameter Test Conditions SYNC Input Reference Frequency Typical Maximum Units Feedback of Q0:Q4, FREQ_SEL = 0 5 40 MHz Feedback of Q0:Q4, FREQ_SEL = 1 10 80 MHz Feedback of Q/2, FREQ_SEL = 0 2.5 20 MHz Feedback of Q/2, FREQ_SEL = 1 5 40 MHz 80 MHz Q0-Q4 fOUT Output Frequency idc Input Duty Cycle SYNC tR / tF Input Rise/ Fall Time tsk(o) Minimum Q/2 40 MHz 75 % SYNC 3 ns Output Skew; NOTE 1, 2, 3 Rising edges of Q0:Q4 and Q/2 300 ps Output Skew; NOTE 1, 2, 3 Falling edges of Q0:Q4 25 300 ps Q0:Q4 80MHz tPERIOD/2 - 0.5 tPERIOD/2 + 0.5 ns Q/2 40MHz tPERIOD/2 - 0.4 tPERIOD/2 + 0.4 ns Feedback = Q 320 ps Feedback = Q/2 530 ps 500 ps tPW Output Pulse Width tjit(cc) Cycle-to-Cycle Jitter t Static Phase Offset, (SYNC to Q0:Q4 FEEDBACK delay); NOTE 2, 4 tPZL Output Enable Time; NOTE 5 OE/nRST Low-to-High 14 ns tPHZ, tPLZ Output Disable Time; NOTE 5 OE/nRST High-to-Low 14 ns tR / tF Output Rise/ Fall Time Q0:Q4, Q/2 0.8V – 2.0V 2 ns tLOCK PLL Lock Time 10 ms 80MHz -500 0.2 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Measured between coincident rising output edges of Q0:Q4 and Q/2. NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. ©2016 Integrated Device Technology, Inc 5 Revision B April 25, 2016 870931I-01 Data Sheet Parameter Measurement Information 1.65V±0.15V Qx SCOPE VDD, AVDD tsk(o) Qx Qy GND Q/2 tsk(o) -1.65V±0.15V 3.3V Output Load AC Test Circuit Output Skew VDD SYNC 2 VDD Q[0:4] FEEDBACK ➤ ➤ tcycle n+1 ➤ ➤ tcycle n 2 ➤ t(Ø) t(Ø) mean = Static Phase Offset ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges Cycle-to-Cycle Jitter Static Phase Offset VDD OE (High-level enabling) VDD/2 VDD/2 0V Q[0:4], Q/2 Pulse Width tEN Output Qx (See Note) t PERIOD tDIS VDD/2 VOH VDD/2 VOL Output Enable/Disable ©2016 Integrated Device Technology, Inc Output Pulse Width 6 Revision B April 25, 2016 870931I-01 Data Sheet Parameter Measurement Information, continued 2V Q[0:4], Q/2 2V 0.8V 0.8V tR tF Output Rise/Fall Time Application Information Recommendations for Unused Output Pins Outputs: LVCMOS Outputs All unused LVCMOS output can be left floating. There should be no trace attached. ©2016 Integrated Device Technology, Inc 7 Revision B April 25, 2016 870931I-01 Data Sheet Schematic Example power pin. The input is driven by a 3.3V LVCMOS driver. An example of LVCMOS termination is shown in this schematic. Figure 1 shows an example of an 870931I-01 application schematic. In this example, the device is operated at VDD = 3.3V. The decoupling capacitors should be located as close as possible to the Logic Control Input Examples Set Logic Input to '1' VDD Set Logic Input to '0' VDD RU1 1K RU2 Not Install To Logic Input pins To Logic Input pins RD1 Not Install RD2 1K Unused output can be left floating. There should no trace attached to unused output. Device characterized with all outputs terminated. VDD R1 VDD VDDA FEEDBACK 10 C1 10u C2 0.1u VDD=3.3V U1 QE/nRST VDD VDD C3 .1uf FREQ_SEL VDD 1 2 3 4 5 6 7 8 9 10 GND OE/nRST FEEDBACK AVDD VDD AGND SYNC FREQ_SEL GND Q0 Q4 Q/2 GND Q3 VDD Q2 GND PLL_EN GND Q1 R2 20 39 19 18 17 VDD = 3.3V 16 15 VDD 14 13 PLL_EN C4 .1uf 12 11 R3 Zo = 50 39 Receiv er Q1 Ro ~ 7 OhmR4 Zo = 50 Ohm GND FREF R5 Zo = 50 39 43 Driv er_LVCMOS Receiv er Figure 1. 870931I-01 Schematic Layout Example ©2016 Integrated Device Technology, Inc 8 Revision B April 25, 2016 870931I-01 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the 870931I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 870931I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 0.3V = 3.6V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX= 3.6V *5mA = 18mW • Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2 Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.6V / [2 * (50 + 11)] = 29.5mA • Power Dissipation on the ROUT per LVCMOS output Power (ROUT) = ROUT * (IOUT)2 = 11 * (29.5mA)2 = 9.57mW per output • Total Power (ROUT) = ROUT (per output) * number of outputs = 9.57mW * 6 outputs = 57.42mW Dynamic Power Dissipation at 80MHz Power (80MHz) = CPD * Frequency * (VDD)2 = 330pF * 80MHz * (3.6V)2 = 342mW Total Power = Power (core)MAX + Total Power (ROUT) + Power (80MHz) = 18mW + 57.42mW + 342mW = 417.42mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 72.3°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.417W * 72.3°C/W = 115.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for a 20 Lead QSOP, Forced Convection JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards ©2016 Integrated Device Technology, Inc 0 200 500 72.3°C/W 64.4°C/W 61.0°C/W 9 Revision B April 25, 2016 870931I-01 Data Sheet Reliability Information Table 7. JA vs. Air Flow Table for a 20 Lead QSOP JA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 72.3°C/W 64.4°C/W 61.0°C/W Transistor Count The transistor count for 870931I-01: 1489 Package Outline and Package Dimensions Package Outline - R Suffix for 20 Lead QSOP, 150MIL Table 8. Package Dimensions for 20 Lead QSOP All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.35 1.75 A1 0.10 0.25 A2 1.50 b 0.20 0.30 c 0.18 0.25 D 8.55 8.750 E 5.80 6.20 E1 3.80 4.00 e 0.635 Basic L 0.40 1.27  0° 8° ZD 1.47 Ref Reference Document: JEDEC Publication 95, MO-137 ©2016 Integrated Device Technology, Inc 10 Revision B April 25, 2016 870931I-01 Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number 870931ARI-01LF 870931ARI-01LFT Marking 870931AI01L 870931AI01L ©2016 Integrated Device Technology, Inc Package “Lead-Free” 20 Lead QSOP “Lead-Free” 20 Lead QSOP 11 Shipping Packaging Tube Tape & Reel Temperature -40C to 85C -40C to 85C Revision B April 25, 2016 870931I-01 Data Sheet Revision History Sheet Rev Table A A A B Page Description of Change Date 8 Added Layout Schematic. 6/10/09 T9 11 Removed leaded orderable parts from the Ordering Information table 11/15/12 T9 1 11 Removed ICS from part number were needed. General Description - Deleted ICS Chip and HiperClocks. Ordering Information - Deleted LF note below table. Removed quantity for tape and reel. Updated header and footer. 1/27/16 1 Corrected header title. 4/25/16 ©2016 Integrated Device Technology, Inc 12 Revision B April 25, 2016 870931I-01 Data Sheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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