8714004DKILF

FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet ICS8714004I DATA SHEET General Description Features The ICS8714004I is Zero-Delay Buffer/Frequency Multiplier with four differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for “zero delay” clock regeneration. In PCI Express and Ethernet applications, 100MHz and 125MHz are the most commonly used reference clock frequencies and each of the four output pairs can be independently set for either 100MHz or 125MHz. With an output frequency range of 98MHz to 165MHz, the device is also suitable for use in a variety of other applications such as Fibre Channel (106.25MHz) and XAUI (156.25MHz). The M-LVDS Input/Output pair is useful in backplane applications when the reference clock can either be local (on the same board as the ICS8714004I) or remote via a backplane connector. In output mode, an input from a local reference clock applied to the CLK, nCLK input pins is translated to M-LVDS and driven out to the MLVDS, nMLVDS pins. In input mode, the internal M-LVDS driver is placed in a High-Impedance state using the OE_MLVDS pin and MLVDS, nMLVDS pin then becomes an input (e.g. from a backplane). • Four 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • • • • • One M-LVDS I/O pair (MLVDS, nMLVDS) • • External feedback for “zero delay” clock regeneration • • • Full 3.3V supply mode -40°C to 85°C ambient operating temperature The ICS8714004I uses low phase noise FemtoClock technology, thus making it ideal for such applications as PCI Express Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel, and 10 Gigabit Ethernet. It is packaged in a 40-VFQFN package (6mm x 6mm). Output frequency range: 98MHz - 165MHz Input frequency range: 19.6MHz - 165MHz VCO range: 490MHz - 660MHz PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter compliant RMS phase jitter @ 125MHz (1.875MHz – 20MHz): 0.558ps (typical) Lead-free (RoHs 6) packaging nQ1 nQ0 Q1 VDDA VDD Q0 CLK nCLK PDIV0 PDIV1 Pin Assignment VDD 1 40 39 38 37 36 35 34 33 32 31 30 OE_MLVDS 2 29 Q2 VDD MLVDS 3 28 nQ2 nMLVDS 4 27 GND PLL_SEL 5 26 Q3 FBO_DIV MR 6 25 nQ3 7 24 FBOUT OE0 8 nFBOUT OE1 9 23 22 GND 10 21 IREF VDD QDIV3 QDIV2 QDIV1 QDIV0 GND FBIN nFBIN FBI_DIV1 VDD FBI_DIV0 11 12 13 14 15 16 17 18 19 20 ICS8714004I 40-Lead VFQFN 6mm x 6mm x 0.925mm package body 4.65mm x 4.65mm Epad Size K Package Top View ICS8714004DKI REVISION A MARCH 24, 2014 1 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Block Diagram 2 OE[1:0] (PU, PU) PDIV1 Pulldown PDIV0 Pulldown CLK nCLK OE_MLVDS Pulldown Pullup/Pulldown QDIV0 (PD) QDIV0 0 ÷4 (default) 1 ÷5 PDIV1:0 00 ÷4 (default) 01 ÷5 10 ÷8 11 ÷1 Pullup 0 QDIV1 0 ÷4 (default) 1 ÷5 PD FBIN nFBIN Pullup PLL VCO Range 490-660MHz 1 QDIV2 0 ÷4 (default) 1 ÷5 Pullup MR nQ1 Pulldown Pullup/Pulldown Q2 nQ2 QDIV3 (PD) QDIV3 0 ÷4 (default) 1 ÷5 FBI_DIV1:0 00 ÷1 01 ÷2 10 ÷4 11 ÷5 (default) IREF PLL_SEL Q1 QDIV2 (PD) nMLVDS FBI_DIV0 nQ0 QDIV1 (PD) MLVDS FBI_DIV1 Q0 Q3 nQ3 FBO_DIV (PD) FBO_DIV 0 ÷4 (default) 1 ÷5 Pullup FBOUT nFBOUT Pulldown Pull-up resistor (PU) on pin (power-up default is HIGH if not externally driven) Pull-down resistor (PD) on pin (power-up default is LOW if not externally driven) ICS8714004DKI REVISION A MARCH 24, 2014 2 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name 1, 11, 22, 30, 35 VDD 2 3 4 OE_MLVDS MLVDS nMLVDS Type Description Power Core supply pins. Input Active High Output Enable. When HIGH, the M-LVDS output driver is active and provides a buffered copy of reference clock applied the CLK, nCLK input to the MLVDS, nMLVDS output pins. The MLVDS, nMLVDS frequency equals the CLK, nCLK frequency divided by the PDIV Divider value (selectable ÷1, ÷4, ÷5, ÷8). When LOW, the M-LVDS output driver is placed into a High Impedance state and the MLVDS, nMLVDS pins can accept a differential input. LVCMOS/LVTTL interface levels. Pullup I/O Non-Inverting M-LVDS input/output. The input/output state is determined by the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives the non-inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input and can accept the following differential input levels: M-LVDS, LVDS, LVPECL, HSTL, HCSL. I/O Inverting M-LVDS input/output. The input/output state is determined by the OE_MLVDS pin. When OE_MLVDS = HIGH, this pin is an output and drives the inverting M-LVDS output. When OE_MLVDS = LOW, this pin is an input and can accept the following differential input levels: M-LVDS, LVDS, LVPECL, HSTL, HCSL. 5 PLL_SEL Input Pullup PLL select. Determines if the PLL is in bypass or enabled mode (default). In enabled mode, the output frequency = VCO frequency/QDIV divider. In bypass mode, the output frequency = reference clock frequency/ (PDIV*QDIV). LVCMOS/LVTTL interface levels. 6 FBO_DIV Input Pulldown Output Divider Control for the feedback output pair, FBOUT, nFBOUT. Refer to Table 3D. LVCMOS/LVTTL interface levels. Active High master reset. When logic HIGH, the internal dividers are reset causing the Qx, nQx outputs to drive High Impedance. Note that assertion of MR overrides the OE[1:0] control pins and all outputs are disabled. When logic LOW, the internal dividers are enabled and the state of the outputs is determined by OE[1:0]. MR must be asserted on power-up to ensure outputs phase aligned. LVCMOS/LVTTL interface levels. 7 MR Input Pulldown 8 OE0 Input Pullup Output Enable. Together with OE1, determines the output state of the outputs with the default state: all output pairs switching. Refer to Table 3B Truth table. LVCMOS/LVTTL Interface levels. 9 OE1 Input Pullup Output Enable. Together with OE0, determines the output state of the outputs with the default state: all output pairs switching. Refer to Table 3B Truth table. LVCMOS/LVTTL Interface levels 10, 16, 27 GND Power 12 FBI_DIV0 Input Pullup Feedback Input Divide Select 0. Together with FBI_DIV1, determines the feedback input divider value. Refer to Table 3C. LVCMOS/LVTTL interface levels. 13 FBI_DIV1 Input Pullup Feedback Input Divide Select 1. Together with FBI_DIV0, determines the feedback input divider value. Refer to Table 3C. LVCMOS/LVTTL interface levels. 14 nFBIN Input Pullup/ Pulldown Inverted differential feedback input to the PLL for regenerating clocks with “Zero Delay.” 15 FBIN Input Pulldown Non-inverted differential feedback input to the PLL for regenerating clocks with “Zero Delay.” ICS8714004DKI REVISION A MARCH 24, 2014 Power supply ground. 3 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Number Name Type Description 17 QDIV0 Input Pulldown Output Divider Control for Q0, nQ0. Refer to Table 3F. LVCMOS/LVTTL interface levels. 18 QDIV1 Input Pulldown Output Divider Control for Q1, nQ1. Refer to Table 3F. LVCMOS/LVTTL interface levels. 19 QDIV2 Input Pulldown Output Divider Control for Q2, nQ2. Refer to Table 3F. LVCMOS/LVTTL interface levels. 20 QDIV3 Input Pulldown Output Divider Control for Q3, nQ3. Refer to Table 3F. LVCMOS/LVTTL interface levels. 21 IREF Input 23, 24 nFBOUT, FBOUT Output Differential feedback output pair. The feedback output pair always switches independent of the output enable settings on the OE[1:0] pins. HCSL interface levels. 25, 26 nQ3, Q3 Output Differential output pair. HCSL interface levels. 28, 29 nQ2, Q2 Output Differential output pair. HCSL interface levels. 31, 32 nQ1, Q1 Output Differential output pair. HCSL interface levels. 33, 34 nQ0, Q0 Output Differential output pair. HCSL interface levels. 36 VDDA Power Analog supply pin. 37 CLK Input Pulldown Non-inverting differential clock input. Accepts HCSL, LVDS, M-LVDS, HSTL, LVPECL input levels. 38 nCLK Input Pullup/ Pulldown Inverting differential clock input. Accepts HCSL, LVDS, M-LVDS, HSTL, LVPECL input levels. 39 PDIV0 Input Pulldown Input Divide Select 0. Together with PDIV1 determines the input divider value. Refer to Table 3E. LVCMOS/LVTTL Interface levels. 40 PDIV1 Input Pulldown Input Divide Select 1. Together with PDIV0 determines the input divider value. Refer to Table 3E. LVCMOS/LVTTL Interface levels. An external fixed precision resistor from this pin to ground is needed to provide a reference current for the differential HCSL outputs. A resistor value of 475 provides an HCSL voltage swing of approximately 700mV. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ICS8714004DKI REVISION A MARCH 24, 2014 Test Conditions 4 Minimum Typical Maximum Units ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Function Tables Table 3A. Common Configuration Table NOTE 1 Input Frequency Output Frequency Application Frequency Mult. Factor PDIV FBI_DIV FBO_DIV QDIVx 100MHz 100MHz PCIe Buffer 1 ÷1 ÷1 ÷5 ÷5 125MHz 125MHz PCIe, Ethernet Buffer 1 ÷1 ÷1 ÷4 ÷4 100MHz 125MHz PCIe Multiplier 5/4 ÷1 ÷1 ÷5 ÷4 125MHz 100MHz PCIe Divider 4/5 ÷1 ÷1 ÷4 ÷5 25MHz 100MHz PCIe Multiplier 4 ÷1 ÷4 ÷5 ÷5 25MHz 125MHz PCIe, Ethernet Multiplier 5 ÷1 ÷4 ÷5 ÷4 25MHz 156.25MHz 25/4 ÷1 ÷5 ÷5 ÷4 62.5MHz 125MHz Ethernet Multiplier 2 ÷1 ÷2 ÷4 ÷4 53.125MHz 106.25MHz Fibre Channel Multiplier 2 ÷1 ÷2 ÷5 ÷5 XAUI Multiplier NOTE 1: This table shows common configurations and is not exhaustive. When using alternate configurations, the user must ensure the VCO frequency is always within its range of 490MHz – 660MHz. Table 3B. Output Enable Truth Table Inputs Output State OE1 OE0 Q0, nQ0 Q1, nQ1 Q2, nQ2 Q3, nQ3 0 0 Q0, nQ0 switching Disabled (High Impedance) Disabled (High Impedance) Disabled (High Impedance) 0 1 Q0, nQ0 switching Q1, nQ1 switching Disabled (High Impedance) Disabled (High Impedance) 1 0 Q0, nQ0 switching Q1, nQ1 switching Q2, nQ2 switching Disabled (High Impedance) 1(default) 1(default) Q0, nQ0 switching Q1, nQ1 switching Q2, nQ2 switching Q3, nQ3 switching Table 3C. Feedback Input Divider Control Table Table 3E. Input Divide Select Control Table Inputs Inputs FBI_DIV1 FBI_DIV0 Feedback Input Divider Values PDIV1 PDIV0 Input Divider Values 0 0 ÷1 0 0 ÷4 (default) 0 1 ÷2 0 1 ÷5 1 0 ÷4 1 0 ÷8 1 1 ÷5 (default) 1 1 ÷1 Table 3D. Feedback Output Divider Control Table Table 3F. Output Divider Control Control Table Inputs Inputs FBO_DIV Feedback Output Divider Value QDIV[3:0] Output Divider Value 0 ÷4 (default) 0 ÷4 (default) 1 ÷5 1 ÷5 ICS8714004DKI REVISION A MARCH 24, 2014 5 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, JA 32.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions VDD Core Supply Voltage VDDA Analog Supply Voltage IDD Power Supply Current IDDA Analog Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V VDD – 0.15 3.3 VDD V Outputs Unloaded 170 210 mA Outputs Unloaded 11 15 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2.2 VDD + 0.3 V -0.3 0.8 V MR, PDIV[1:0], QDIV[3:0], FBO_DIV VDD = VIN = 3.465V 150 µA PLL_SEL, OE_MLVDS, FBI_DIV[1:0], OE[1:0] VDD = VIN = 3.465V 5 µA MR, PDIV[1:0], QDIV[3:0], FBO_DIV VDD = 3.465V, VIN = 0V -5 µA PLL_SEL, OE_MLVDS, FBI_DIV[1:0], OE[1:0] VDD = 3.465V, VIN = 0V -150 µA ICS8714004DKI REVISION A MARCH 24, 2014 6 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 CLK, nCLK, FBIN, nFBIN Minimum Typical VDD = VIN = 3.465V Maximum Units 150 µA CLK, FBIN VDD = 3.465V, VIN = 0V -5 µA nCLK, nFBIN VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. M-LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change ICS8714004DKI REVISION A MARCH 24, 2014 Test Conditions Minimum Typical Maximum Units 370 410 470 mV 50 mV 2.3 V 50 mV 0.3 7 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet AC Electrical Characteristics Table 5A. PCI Express Jitter Specifications, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol tj (PCIe Gen 1) tREFCLK_HF_RMS (PCIe Gen 2) tREFCLK_LF_RMS (PCIe Gen 2) tREFCLK_RMS (PCIe Gen 3) Parameter Phase Jitter Peak-to-Peak; NOTE 1, 4 Phase Jitter RMS; NOTE 2, 4 Phase Jitter RMS; NOTE 2, 4 Phase Jitter RMS; NOTE 3, 4 Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 20 30 86 ps ƒ = 125MHz, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12 25 86 ps ƒ = 100MHz High Band: 1.5MHz - Nyquist (clock frequency/2) 2 3 3.1 ps ƒ = 125MHz High Band: 1.5MHz - Nyquist (clock frequency/2) 0.8 1.4 3.1 ps ƒ = 100MHz Low Band: 10kHz - 1.5MHz 0.1 0.4 3.0 ps ƒ = 125MHz Low Band: 10kHz - 1.5MHz 0.1 0.4 3.0 ps ƒ = 100MHz Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.5 0.7 0.8 ps ƒ = 125MHz Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.2 0.4 0.8 ps Test Conditions Minimum NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86ps peak-to-peak for a sample size of 106 clock periods. NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification. NOTE 4: This parameter is guaranteed by characterization. Not tested in production. ICS8714004DKI REVISION A MARCH 24, 2014 8 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Table 5B. AC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tsk(o) Output Skew; NOTE 1, 2 tjit(Ø) RMS Phase Jitter (Random); NOTE 3, 4 Test Conditions Minimum Typical Maximum Units 165 MHz 35 80 ps Outputs measured Q[0:3] 100 210 ps 125MHz, Integration Range: 1.875MHz – 20MHz 0.558 ps 100MHz, Integration Range: 1.875MHz – 20MHz 0.567 ps 98 tL PLL Lock Time 100 ms VMAX Absolute Max Output Voltage; NOTE 5, 6 1150 mV VMIN Absolute Min Output Voltage; NOTE 5, 7 -300 VRB Ringback Voltage; NOTE 8, 9 -100 tSTABLE Time before VRB is allowed; NOTE 8, 9 500 VCROSS Absolute Crossing Voltage; NOTE 10, 11 150 VCROSS Total Variation of VCROSS over all edges; NOTE 10, 12 Rise/Fall Edge Rate Rising/Falling Edge Rate; NOTE 8, 13 odc Output Duty Cycle; NOTE 14 Measured between -150mV to +150mV mV 100 mV ps 550 mV 140 mV 0.6 4 V/ns 45 55 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Characterized with configurations in Table 3A. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: Refer to the Phase Noise plots. NOTE 4: Measurements depend on input source used. NOTE 5: Measurement taken from single-ended waveform. NOTE 6: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section. NOTE 7: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section. NOTE 8: Measurement taken from a differential waveform. NOTE 9: tSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed to drop back into the VRB ±100mV differential range. See Parameter Measurement Information Section. NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx. See Parameter Measurement Information Section NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. See Parameter Measurement Information Section. NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the VCROSS for any particular system. See Parameter Measurement Information Section. NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing. See Parameter Measurement Information Section. NOTE 14: Input duty cycle must be 50%. ICS8714004DKI REVISION A MARCH 24, 2014 9 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Noise Power dBc Hz Typical Phase Noise at 125MHz Offset Frequency (Hz) ICS8714004DKI REVISION A MARCH 24, 2014 10 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Noise Power dBc Hz Typical Phase Noise at 100MHz Offset Frequency (Hz) ICS8714004DKI REVISION A MARCH 24, 2014 11 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Parameter Measurement Information 3.3V±5% 3.3V±5% 3.3V±5% 3.3V±5% VDD Measurement Point VDD VDDA VDDA 2pF Measurement Point IREF GND 2pF 0V 0V This load condition is used for VMAX, VMIN, VRB, tSTABLE, VCROSS, VCROSS and Rise/Fall Edge Rate measurements. This load condition is used for IDD, tjit(cc), tjit(Ø) and tsk(o) measurements. 3.3V HCSL Output Load Test Circuit 3.3V HCSL Output Load Test Circuit VDD SCOPE VDD 3.3V±5% POWER SUPPLY + Float GND – Qx nCLK VDDA V V Cross Points PP CMR CLK nQx GND 3.3V M-LVDS Output Load Test Circuit Differential Input Level nQ0:Q3, nFBOUT nQx Qx Q0:Q3, FBOUT tcycle n nQy Qy Output Skew ICS8714004DKI REVISION A MARCH 24, 2014 tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Cycle-to-Cycle Jitter 12 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Parameter Measurement Information, continued VDD out M-LVDS ➤ DC Input out ➤ VOS/Δ VOS ➤ M-LVDS Offset Voltage Setup RMS Phase Jitter VDD M-LVDS 100 100 ➤ VOD/Δ VOD out ➤ DC Input ➤ out M-LVDS Differential Output Voltage Setup Differential Measurement Points for Ringback Single-ended Measurement Points for Delta Cross Point Single-ended Measurement Points for Absolute Cross Point/Swing ICS8714004DKI REVISION A MARCH 24, 2014 13 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Parameter Measurement Information, continued Differential Measurement Points for Rise/Fall Time Differential Measurement Points for Duty Cycle/Period ICS8714004DKI REVISION A MARCH 24, 2014 14 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Application Information Overview clock to CLK, nCLK input. The ICS8714004I must provide a 25MHz M-LVDS clock to the backplane and also provide two local clocks: one 100MHz HCSL output to an ASIC and one 125MHz output to the PCI Express serdes. The is a high performance FemtoClock Zero Delay Buffer/ Multiplier/Divider which uses external feedback for accurate clock regeneration and low static and dynamic phase offset. It can be used in a number different ways: Solution: Since only two outputs are needed, the two unused outputs can be disabled. Set OE[1:0] = 01b so that only Q0, nQ0 and Q1, nQ1 are switching. Since a 25MHz backplane clock is needed from a 125MHz reference clock, set PDIV = ÷5 and OE_MLVDS = HIGH to enable the M-LVDS driver. 25MHz is applied to the MLVDS, nMLVDS pins and to the phase detector input. Set FBO_DIV = 4 and FBI_DIV = 5 which makes the VCO run at 500MHz (25MHz * 4 * 5 = 500MHz). Set QDIV0 = 0 (÷4) for 125MHz output and QDIV1 = 1 (÷5) for 100MHz output. To figure out what pins must pulled up or down externally with resistors, check the internal pullup or pulldown resistors on each pin in the pin description table or on the block diagram. PDIV[1:0] defaults to 00/÷4 and we need 01/÷5. So PDIV1 can be left floating (it has an internal pulldown resistor) and PDIV0 must be driven or pulled up via external pullup resistor to HIGH state. OE_MLVDS defaults to Logic 1 (active) and this is what we need, so that pin can be left floating. The FBO_DIV and FBIN dividers default to the desired values, so their respective control pins can be left floating (FBO_DIV and FBI_DIV[1:0]). QDIV0 needs to be ÷4, which is a default value so this pin can be left floating. QDIV1 must be HIGH for ÷5, so this pin must be pulled high or driven high externally. OE[1:0] = 01, so OE0 can Float and OE1 must be pulled Low. • Backplane clock multiplier. Many backplane clocks are relatively low frequency because of heavy electrical loading. The ICS8714004I can multiply a low frequency backplane clock (e.g. 25MHz) to an appropriate reference clock frequency for PCIe, Ethernet, 10G Ethernet: 100MHz, 125MHz, 156.25MHz. The device can also accept a high frequency local reference (100MHz or 125MHz, for example) and divide the frequency down to 25MHz M-LVDS to drive a backplane. • PCIe frequency translator for PCIe add-in cards. In personal computers, the PCIe reference clock is 100MHz, but some 2.5G serdes used in PCI Express require a 125MHz reference. The ICS8714004I can perform the 100MHz  125MHz and 125MHz  100MHz frequency translation for a PCI Express add-in card while delivering low dynamic and static phase offset. • General purpose, low phase noise Zero Delay Buffer Configuration Notes and Examples When configuring the output frequency, the main consideration is keeping the VCO within its range of 490MHz - 660MHz. The designer must ensure that the VCO will always be within its allowed range for the expected input frequency range by using the appropriate choice of feedback output and input dividers. There are two input modes for the device. In the first mode, a reference clock is provided to the CLK/nCLK input and this reference clock is divided by the value of the PDIV divider (selectable ÷1, ÷4, ÷5, ÷8). In the second mode, a reference clock is provided to the MLVDS, nMLVDS input pair. OE_MLVDS determines the input mode. When OE_MLVDS = HIGH (default), the M-LVDS driver is active and provides an M-LVDS output to the MLVDS, nMLVDS pins and also the reference to the phase detector via the PDIV divider. When OE_MLVDS is LOW, the internal M-LVDS driver is in High Impedance state and the MLVDS, nMLVDS pin pair becomes an input and the reference clock applied to this input is applied to the phase detector. MLVDS, nMLVDS Input Mode OE_MLVDS = LOW VCO frequency = MLVDS, nMLVDS freq. * FBI_DIV * FBO_DIV Output frequency = VCO frequency/QDIVx value = MLVDS, nMLVDS freq. * FBI_DIV * FBO_DIV/(QDIVx) Example - backplane: The 8714004I sits on a backplane card and must multiply a 25MHz reference that comes from the backplane into one 125MHz reference clock for a gigabit Ethernet serdes and one 100MHz reference clock for a PCI Express serdes. Solution. Since only two outputs are needed, the two unused outputs can be disabled. Set OE1:0 = 01b so that only Q0, nQ0 and Q1, nQ1 are switching. Set OE_MLVDS = 0 so the internal M-LVDS driver is in a High Impedance state, allowing the MLVDS, nMLVDS pins to function as an input for the 25MHz clock reference. Set FBO_DIV = 4 and FBI_DIV = 5 which makes the VCO run at 500MHz (25MHz * 4 * 5 = 500MHz). Set QDIV0 = 0 (÷4) for 125MHz output and QDIV1 = 1 (÷5) for 100MHz output. To figure out what pins must pulled up or down externally with resistors, check the internal pullup or pulldown resistors on each pin in the pin description table or on the block diagram. PDIV[1:0] defaults to 00/÷4 and we need 01/÷5. So PDIV1 can be left floating (it has an internal pulldown resistor) and PDIV0 must be driven or pulled up via external pullup resistor to HIGH state. OE_MLVDS defaults to Logic 1 (active) and this is what we need, so that pin can be left floating. The FBO_DIV and FBIN dividers default to the desired values, so their respective control pins can be left MLVDS, nMLVDS Output Mode OE_MLVDS = HIGH (default) VCO frequency = CLK/nCLK frequency * FBI_DIV * FBO_DIV/ (PDIV value) Allowed VCO frequency = 490MHz – 660MHz Output frequency = VCO frequency/QDIVx value = CLK/nCLK freq. * FBI_DIV * FBO_DIV/(PDIV*QDIVx) Example: a frequency synthesizer provides a 125MHz reference ICS8714004DKI REVISION A MARCH 24, 2014 15 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet floating (FBO_DIV and FBI_DIV1:0). QDIV0 needs to be ÷4, which is a default value so this pin can be left floating. QDIV1 must be HIGH for ÷5, so this pin must be pulled high or driven high externally. OE[1:0] = 01, so OE0 can Float and OE1 must be pulled Low. Master Clock Card 25 MHz ICS8714004I CLK MLVDS 100 MHz HCSL ÷4 MLVDS SSC Synthesizer ICS841402I CLK 100 MHz HCSL FPGA FemtoClock VCO 125 MHz HCSL PCIe Serdes Slave synthesizer Off or output disabled Backplane Slave Clock Card 25 MHz MLVDS ICS8714004I CLK SSC Synthesizer ICS841402I ÷4 CLK 100 MHz HCSL FPGA FemtoClock VCO 125 MHz HCSL PCIe Serdes Figure 1, Example Backplane Application Bold lines indicate active clock path This example shows a case where each card may be dynamically configured as a master or slave card, hence the need for an ICS8714004I and ICS841402I on each card. On the master timing card, the ICS841402I provides a 100MHz reference to the ICS8714004I CLK, nCLK input. The M-LVDS pair on the ICS8714004I is configured as an output (OE_MLVDS = Logic 1) and the internal divider is set to ÷4 to generate 25MHz M-LVDS to the backplane. The 25MHz clock is also used as a reference to the FemtoClock PLL which multiplies to a VCO frequency of 500MHz. Each of the four output pairs may be individually set for ÷4 or ÷5 for 125MHz or 100MHz operation respectively and in this example, one output pair is set to 100MHz for the FPGA and another output pair is set to 125MHz for the PCI Express serdes. For the slave card, the ICS8714004DKI REVISION A MARCH 24, 2014 M-LVDS pair is configured as an input (OE_MLVDS = LOW) and the FemtoClock PLL multiplies this reference frequency to 500MHz VCO frequency and the output dividers are set to provide 100MHz to the FPGA and 125MHz to the PCI Express Serdes as shown. 16 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage V1 = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1 in the center of the input voltage swing. For example, if the input clock swing is 3.3V and VDD = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8714004DKI REVISION A MARCH 24, 2014 17 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Overdriving the XTAL Interface The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This VCC can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 3B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. XTAL_OUT R1 100 Ro Rs C1 Zo = 50 ohms XTAL_IN R2 100 Zo = Ro + Rs .1uf LVCMOS Driver Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface XTAL_OUT C2 Zo = 50 ohms XTAL_IN .1uf Zo = 50 ohms LVPECL Driver R1 50 R2 50 R3 50 Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface ICS8714004DKI REVISION A MARCH 24, 2014 18 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 4A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω Zo = 50Ω nCLK nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Differential Input LVPECL R1 50Ω R2 50Ω R2 50Ω Figure 4B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 4A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver 3.3V 3.3V 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK R1 100Ω nCLK Differential Input LVPECL nCLK Zo = 50Ω Receiver LVDS Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 4C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V 3.3V Zo = 50Ω *R3 CLK CLK R2 100Ω R1 100Ω nCLK HCSL *R4 Zo = 50Ω Differential Input Figure 4E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8714004DKI REVISION A MARCH 24, 2014 nCLK Receiver MLVDS Figure 4F. CLK/nCLK Input Driven by a 3.3V MLVDS Driver 19 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8714004DKI REVISION A MARCH 24, 2014 20 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins: Differential Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs M-LVDS Outputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. All unused M-LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached. MLVDS, nMLVDS Inputs For applications not requiring the use of the differential input, both MLVDS and nMLVDS can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from MLVDS to ground. ICS8714004DKI REVISION A MARCH 24, 2014 21 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Recommended Termination Figure 6A is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination is the standard for PCI Express™and HCSL output types. 0.5" Max Rs All traces should be 50Ω impedance single-ended or 100Ω differential. 0-0.2" 22 to 33 +/-5% 0.5 - 3.5" 1-14" L1 L2 L4 L1 L2 L4 L5 L5 PCI Expres s PCI Expres s Connector Driver 0-0.2" L3 L3 PCI Expres s Add-in Card 49.9 +/- 5% Rt Figure 6A. Recommended Source Termination (where the driver and receiver will be on separate PCBs) Figure 6B is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will 0.5" Max Rs 0 to 33 L1 be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential. 0-18" 0-0.2" L2 L3 L2 L3 0 to 33 L1 PCI Expres s Driver 49.9 +/- 5% Rt Figure 6B. Recommended Termination (where a point-to-point connection can be used) ICS8714004DKI REVISION A MARCH 24, 2014 22 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht  s  = H3  s    H1  s  – H2  s   The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y  s  = X  s   H3  s    H1  s  – H2  s   In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCIe Gen 2A Magnitude of Transfer Function PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ICS8714004DKI REVISION A MARCH 24, 2014 PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 23 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Schematic Example Figure 7 (next page) shows an example ICS8714004I application schematic. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. Input and output terminations shown are also intended as examples only and may not represent the exact user configuration. In order to achieve the best possible filtering, it is highly recommended that the 0.1uF capacitors be placed on the device side of the PCB as close to the power pins as possible. This is represented by the placement of these capacitors in the schematic. If space is limited, the ferrite bead, 10uf and 0.1uF capacitors connected to 3.3V can be placed on the opposite side of the PCB. If space permits, place all filter components on the device side of the board. In this particular schematic the MLVDS port is in output mode, configured by setting OE_MLVDS = 1. Since the zero delay function is local to the chip, the FBOUT to FBIN connection is a special case of a point to point PCIe link. The close proximity of these two ports means that the 33 series resistors are not necessary and the 49.9 termination resistors are to be placed at the FBIN port. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS8714004I provides separate VDD and VDDA power supplies to isolate any high switching noise from coupling into the internal PLL. ICS8714004DKI REVISION A MARCH 24, 2014 24 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Logic Control Input E xamples VDD Set Logi c Input to '1' 3.3V Set Logi c Input to '0' VDD FB1 VDD RU1 1K 2 RU2 Not Install To L ogic In put pins C2 10uF To L ogic In put pins RD1 Not Ins tall 1 BLM18BB221SN1 C1 0.1uF FB2 2 VDDA RD2 1K 1 BLM18BB221SN1 C3 10uF 1 11 22 30 35 VDD C4 0. 1uF VDD VDD VDD VDD VDD U1 36 OE_MLVDS OE0 OE1 2 8 9 MR PLL_SEL 7 5 F BI_DIV0 F BI_DIV1 F BO_DIV 12 13 6 PDI V0 PDI V1 39 40 QDIV0 QDIV1 QDIV2 QDIV3 17 18 19 20 VDDA OE_MLVDS OE0 OE1 MR PLL_SEL Q0 nQ0 F BI_DIV0 F BI_DIV1 F BO_DIV MLVDS 34 33 C7 0. 1uF C8 0. 1uF R6 1" t o 14 " Zo = 50 0. 5" t o 3. 5" Zo = 50 Q1 nQ1 Q2 nQ2 MLVDS 32 31 C11 0.1uF + 33 Zo = 50 QDIV0 QDIV1 QDIV2 QDIV3 C10 0.1uF Place each 0.1uF bypass cap directly adjacent to its corresponding VDD or VDDA pin. 33 R9 PDIV0 PDIV1 C9 0.1uF VDDA C5 0. 1uF 3 To MLVDS bus C6 0. 1uF R7 50 Zo = 50 - R4 50 HCSL_Receiv er PCI E xpress Add-In Card HCS L Terminati on 29 28 4 nMLVDS nMLVDS OE_MLVDS = 1 to select MLVDS output R3 Q3 nQ3 33 26 25 R2 0" t o 18 " Zo = 50 + 33 Zo = 50 CLK Zo = 50 Ohm - Optional Zo = 50 Ohm R1 100 37 nCLK 38 IREF 21 CLK R11 475 nCLK HCSL_Receiver R8 50 R5 50 PCI E xpress Point-to-Point Connecti on LVDS Driv er 15 14 nFBIN FBOUT nFBOUT 24 23 41 10 16 27 ePAD R12 49.9 GND GND GND R13 49.9 F BIN Figure 7. ICS8714004I Schematic Example ICS8714004DKI REVISION A MARCH 24, 2014 25 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS8714004I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8714004I is the sum of the core power plus the analog power plus the output power dissipated due to the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating output power dissipated due to the load. • Power (core)MAX = VDD_MAX * (IDD_MAX +IDDA_MAX} = 3.465V *(210mA + 15mA) = 779.6mW • Power (outputs)MAX = 44.5mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 44.5mW = 222.5mW Total Power_MAX = 779.6mW + 222.5mW = 1002.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 32.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 1.002W * 32.4°C/W = 117.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 40 Lead VFQFN, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8714004DKI REVISION A MARCH 24, 2014 0 1 2.5 32.4°C/W 28.3°C/W 25.4°C/W 26 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure 8. VDD IOUT = 17mA VOUT RREF = 475 ± 1% RL 50 IC Figure 8. HCSL Driver Circuit and Termination HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation, use the following equations which assume a 50 load to ground. The highest power dissipation occurs when VDD_MAX. Power = (VDD_MAX – VOUT) * IOUT, since VOUT = IOUT * RL = (VDD_MAX – IOUT * RL) * IOUT = (3.465V – 17mA * 50) * 17mA Total Power Dissipation per output pair = 44.5mW ICS8714004DKI REVISION A MARCH 24, 2014 27 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Reliability Information Table 7. JA vs. Air Flow Table for a 40 Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 32.4°C/W 28.3°C/W 25.4°C/W Transistor Count The transistor count for ICS8714004I is: 3799 ICS8714004DKI REVISION A MARCH 24, 2014 28 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Package Outline and Package Dimensions Package Outline - K Suffix for 40 Lead VFQFN (Ref.) S eating Plan e N &N Even (N -1)x e (R ef.) A1 Ind ex Area A3 N To p View Anvil Anvil Singulation Singula tion or OR Sawn Singulation L N e (Ty p.) 2 If N & N 1 are Even 2 E2 (N -1)x e (Re f.) E2 2 b A (Ref.) D e N &N Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C Bottom View w/Type A ID D2 C Bottom View w/Type C ID 2 1 2 1 CHAMFER 4 Th er mal Ba se D2 2 N N-1 RADIUS 4 N N-1 There are 2 methods of indicating pin 1 corner at the back of the VFQFN package: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type C: Mouse bite on the paddle (near pin 1) Table 8. Package Dimensions NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pin-out are shown on the front page. The package dimensions are in Table 8. JEDEC Variation: VJJD-2/-5 All Dimensions in Millimeters Symbol Minimum Maximum N 40 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 10 ND & NE D&E 6.00 Basic D2 & E2 4.65 4.65 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8714004DKI REVISION A MARCH 24, 2014 29 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet Ordering Information Table 9. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8714004DKILF ICS714004DIL “Lead-Free” 40 Lead VFQFN Tray -40C to 85C 8714004DKILFT ICS714004DIL “Lead-Free” 40 Lead VFQFN Tape & Reel -40C to 85C ICS8714004DKI REVISION A MARCH 24, 2014 30 ©2014 Integrated Device Technology, Inc. FemtoCLock® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet ICS8714004I Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2014. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.