8725BY-01LFT

Differential-to-HSTL Zero Delay Clock Generator ICS8725B-01 DATA SHEET General Description Features The ICS8725B-01 is a highly versatile 1:5 Differentialto-HSTL clock generator and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from IDT. The ICS8725B-01 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25MHz to 700MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. • • • Five differential HSTL output pairs • • • • Output frequency range: 31.25MHz to 700MHz • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • • • • • • Static phase offset: 15ps ± 135ps ICS Block Diagram VCO range: 250MHz to 700MHz External feedback for “zero delay” clock regeneration with configurable frequencies Cycle-to-cycle jitter: 25ps (maximum) Output skew: 45ps (maximum) 3.3V core, 1.8V output operating supply 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages VDDO nQ4 Q4 GND SEL3 PLL_SEL Q3 CLK0 3 22 nQ3 nCLK0 4 21 Q2 CLK1 5 20 nQ2 nCLK1 6 19 Q1 CLK_SEL 7 18 nQ1 MR 8 17 VDDO 9 10 11 12 13 14 15 16 VDDO SEL0 23 Q0 8:1, 4:1, 2:1, 1:1 1:2, 1:4, 1:8 VDDO 2 nQ0 Q4 nQ4 24 SEL1 GND PLL 1 SEL2 Q3 nQ3 1 SEL0 FB_IN 0 32 31 30 29 28 27 26 25 Q2 nQ2 nFB_IN 0 VDDA VDD Q1 nQ1 VDD ÷1, ÷2, ÷4, ÷8 ÷16, ÷32, ÷64 CLK_SEL FB_IN nFB_IN Input frequency range: 31.25MHz to 700MHz Q0 nQ0 1 CLK1 nCLK1 CLKx/nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL Pin Assignment PLL_SEL CLK0 nCLK0 Selectable differential CLKx/nCLKx input pairs SEL1 ICS8725B-01 SEL2 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View SEL3 MR ICS8725BY-01 REVISION A JULY 16, 2009 1 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 1. Pin Descriptions Number Name 1, 2, 12, 29 SEL0, SEL1, SEL2, SEL3 Type Description Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels. 3 CLK0 Input Pulldown Non-inverting differential clock input. 4 nCLK0 Input Pullup Inverting differential clock input. 5 CLK1 Input Pulldown 6 nCLK1 Input Pullup Non-inverting differential clock input. 7 CLK_SEL Input Pulldown Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0, nCLK0. LVCMOS/LVTTL interface levels. Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Inverting differential clock input. 8 MR Input 9, 32 VDD Power 10 nFB_IN Input Pullup Inverting differential feedback input to phase detector for regenerating clocks with “Zero Delay.” 11 FB_IN Input Pulldown Non-inverted differential feedback input to phase detector for regenerating clocks with “Zero Delay.” 13, 28 GND Power Power supply ground. 14, 15 nQ0, Q0 Output Differential output pair. HSTL interface levels. 16, 17, 24, 25 VDDO Power Output supply pins. 18, 19 nQ1, Q1 Output Differential output pair. HSTL interface levels. 20, 21 nQ2, Q2 Output Differential output pair. HSTL interface levels. 22, 23 nQ3, Q3 Output Differential output pair. HSTL interface levels. 26, 27 nQ4, Q4 Output Differential output pair. HSTL interface levels. 30 VDDA Power Analog supply pin. 31 PLL_SEL Input Core supply pins. Pullup PLL select. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 2 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ICS8725BY-01 REVISION A JULY 16, 2009 Test Conditions 2 Minimum Typical Maximum Units ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Function Tables Table 3A. Control Input Function Table Inputs Outputs PLL_SEL = 1 PLL Enable Mode SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q[0:4], nQ[0:4] 0 0 0 0 250 - 700 ÷1 0 0 0 1 125 - 350 ÷1 0 0 1 0 62.5 - 175 ÷1 0 0 1 1 31.25 - 87.5 ÷1 0 1 0 0 250 - 700 ÷2 0 1 0 1 125 - 350 ÷2 0 1 1 0 62.5 - 175 ÷2 0 1 1 1 250 - 700 ÷4 1 0 0 0 125 - 350 ÷4 1 0 0 1 250 - 700 ÷8 1 0 1 0 125 - 350 x2 1 0 1 1 62.5 - 175 x2 1 1 0 0 31.25 - 87.5 x2 1 1 0 1 62.5 - 175 x4 1 1 1 0 31.25 - 87.5 x4 1 1 1 1 31.25 - 87.5 x8 *NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz. ICS8725BY-01 REVISION A JULY 16, 2009 3 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 3B. PLL Bypass Function Table Inputs Outputs PLL_SEL = 0 PLL Bypass Mode SEL3 SEL2 SEL1 SEL0 Q[0:4], nQ[0:4] 0 0 0 0 ÷4 0 0 0 1 ÷4 0 0 1 0 ÷4 0 0 1 1 ÷8 0 1 0 0 ÷8 0 1 0 1 ÷8 0 1 1 0 ÷16 0 1 1 1 ÷16 1 0 0 0 ÷32 1 0 0 1 ÷64 1 0 1 0 ÷2 1 0 1 1 ÷2 1 1 0 0 ÷4 1 1 0 1 ÷1 1 1 1 0 ÷2 1 1 1 1 ÷1 ICS8725BY-01 REVISION A JULY 16, 2009 4 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 135 mA IDDA Analog Supply Current 16 mA IDDO Output Supply Current 0 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V CLK_SEL, SEL[0:3], MR VDD = VIN = 3.465V 150 µA PLL_SEL VDD = VIN = 3.465V 5 µA CLK_SEL, SEL[0:3], MR VDD = 3.465V, VIN = 0V -5 µA PLL_SEL VDD = 3.465V, VIN = 0V -150 µA ICS8725BY-01 REVISION A JULY 16, 2009 5 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol IIH IIL Parameter Test Conditions Minimum Typical Maximum Units FB_IN, CLK0, CLK1 VDD = VIN = 3.465V 150 µA nFB_IN, nCLK0, nCLK1 VDD = VIN = 3.465V 5 µA Input High Current FB_IN, CLK0, CLK1 VDD = 3.465V, VIN = 0V -5 µA nFB_IN, nCLK0, nCLK1 VDD = 3.465V, VIN = 0V -150 µA Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD – 0.85 V Maximum Units NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. HSTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 1.0 1.4 V VOL Output Low Voltage; NOTE 1 0 0.4 V VOX Output Crossover Voltage; NOTE 2 40 60 % VSWING Peak-to-Peak Output Voltage Swing 0.6 1.1 V NOTE 1: Outputs terminated with 50Ω to ground. NOTE 2: Defined with respect to output voltage swing at a given condition. Table 5. Input Frequency Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter FIN Input Frequency CLK0, nCLK0, CLK1, nCLK1 ICS8725BY-01 REVISION A JULY 16, 2009 Test Conditions Minimum PLL_SEL = 1 31.25 PLL_SEL = 0 6 Typical Maximum Units 700 MHz 700 MHz ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR AC Electrical Characteristics Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = 0°C to 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(Ø) Static Phase Offset; NOTE 2, 5 tsk(o) Output Skew; NOTE 3, 5 tjit(cc) Test Conditions Minimum PLL_SEL = 0V, f ≤ 700MHz 3.2 PLL_SEL = 3.3V -120 Typical Maximum Units 700 MHz 4.4 ns 150 ps 45 ps Cycle-to-Cycle Jitter; NOTE 5, 6 25 ps tjit(θ) Phase Jitter; NOTE 4, 5, 6 ±50 ps tL PLL Lock Time 1 ms tR / tF Output Rise/Fall Time 700 ps tPW Output Pulse Width tPERIOD/2 + 85 ps 15 PLL_SEL = 0V 20% to 80% @ 50MHz 300 tPERIOD/2 - 85 tPERIOD/2 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: Phase jitter is dependent on the input source used. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Characterized at VCO frequency of 622MHz. ICS8725BY-01 REVISION A JULY 16, 2009 7 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information 3.3V±5% 1.8V±0.2V VDD VDD, VDDA Qx SCOPE nCLK0, nCLK1 VDDO V Cross Points PP HSTL V CMR CLK0, CLK1 nQx GND GND 0V Differential Input Level 3.3V Core/1.8V Output Load AC Test Circuit nCLK0, nCLK1 VOH CLK0, CLK1 VOL nFB_IN nQx Qx VOH VOL FB_IN nQy ➤ ➤ t(Ø) tjit(Ø) =  t(Ø) – t(Ø) mean= Phase Jitter t(Ø) mean = Static Phase Offset Qy tsk(o) Where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on the controlled edges) Output Skew Phase Jitter and Static Phase Offset nQ[0:4] nQ[0:4] Q[0:4] Q[0:4] t PW ➤ tcycle n ➤ tcycle n+1 t ➤ ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles odc = PERIOD t PW x 100% t PERIOD Cycle-to-Cycle Jitter ICS8725BY-01 REVISION A JULY 16, 2009 Output Duty Cycle/Pulse Width/Period 8 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Parameter Measurement Information, continued nCLK0, nCLK1 nQ[0:4] 80% 80% VOX Q[0:4] CLK0, CLK1 VSW I N G nQ[0:4] 20% 20% tR tF Q[0:4] tPD Propagation Delay Output Rise/Fall Time Application Information Power Supply Filtering Technique To achieve optimum jitter performance, power supply isolation is required. To achieve optimum jitter performance, power supply isolation is required. The ICS8725B-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead. ICS8725BY-01 REVISION A JULY 16, 2009 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering 9 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Recommendations for Unused Input Pins Inputs: Outputs: LVCMOS Control Pins HSTL OUTPUTS All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused HSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. Wiring the Differential Input to Accept Single Ended Levels Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF - C1 0.1uF R2 1K Figure 2. Single-Ended Signal Driving Differential Input ICS8725BY-01 REVISION A JULY 16, 2009 10 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 3A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 3B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50Ω Zo = 50Ω CLK CLK R1 100 Zo = 50Ω nCLK HiPerClockS Input LVPECL R1 84 R2 84 Figure 3C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Zo = 50Ω Receiver LVDS Figure 3D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω Figure 3F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 3E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8725BY-01 REVISION A JULY 16, 2009 11 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Schematic Example The schematic of the ICS8725B-01 layout example is shown in Figure 4A. The ICS8725B-01 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board. VDD SP = Spare (i.e. not installed) RU2 SP RU3 1K RU4 1K RU5 SP RU6 1K RD6 SP RD7 1K VDD Zo = 50 Ohm + SEL3 RD5 1K (77.76 MHz) PLL_SEL RD4 SP C16 10u VDD VDDO VDDO - LVHSTL_input Zo = 50 Ohm (155.52 MHz) Zo = 50 Ohm CLK_SEL 3.3V PECL Driv er R8 50 R9 50 1 2 3 4 5 6 7 8 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR U1 ICS8725B-01 R10 50 VDD nFB_IN FB_IN SEL2 GND nQ0 Q0 VDDO SEL0 SEL1 Zo = 50 Ohm R4A 50 R4B 50 24 23 22 21 20 19 18 17 VDDO Q3 nQ3 Q2 nQ2 Q1 nQ1 VDDO VDD=3.3V VDDO=1.8V 9 10 11 12 13 14 15 16 3.3V VDD PLL_SEL VDDA SEL3 GND Q4 nQ4 VDDO 32 31 30 29 28 27 26 25 RD3 SP VDD 10 C11 0.01u CLK_SEL PLL_SEL SEL0 SEL1 SEL2 SEL3 RD2 1K R7 VDDA RU7 SP SEL[3:0] = 0101, Divide by 2 SEL2 R2B 50 R2A 50 Bypass capacitors located near the power pins VDD (U1-9) VDD C1 0.1uF (U1-32) C6 0.1uF VDDO VDDO (U1-16) C2 0.1uF (U1-17) C4 0.1uF (U1-24) C5 0.1uF (U1-25) C7 0.1uF Figure 4. ICS8725B-01 HSTL Zero Delay Buffer Schematic Example ICS8725BY-01 REVISION A JULY 16, 2009 12 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR The following component footprints are used in this layout example: All the resistors and capacitors are size 0603. location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. Power and Grounding • The differential 50Ω output traces should have same length. Place the decoupling capacitors C1, C6, C2, C4, C5, and C7 as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. Clock Traces and Termination Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component • Make sure no other signal traces are routed between the clock trace pair. The matching termination resistors should be located as close to the receiver input pins as possible. GND R7 C16 C11 C7 VDDO C6 C5 VDD U1 Pin 1 VDDA VIA 50 Ohm Traces C4 C1 C2 Figure 4B. PCB Board Layout for ICS8725B-01 ICS8725BY-01 REVISION A JULY 16, 2009 13 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS8725B-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8725B-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (135mA + 16mA) = 523.215mW • Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 5 * 32.8mW = 164mW Total Power_MAX (3.465V, with all outputs switching) = 523.215mW + 164mW = 687.215mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 47.9°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.687W * 47.9°C/W = 102.9°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance θJA for 32 Lead LQFP, Forced Convection θJA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS8725BY-01 REVISION A JULY 16, 2009 14 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 5. VDD Q1 VOUT RL 50Ω Figure 5. HSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX) Pd_L = (VOL_MAX /RL) * (VDDO_MAX - VOL_MAX) Pd_H = (1.0V/50Ω) * (2V - 1.0V) = 20mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW ICS8725BY-01 REVISION A JULY 16, 2009 15 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Reliability Information Table 8. θJA vs. Air Flow Table for a 32 Lead LQFP θJA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS8725B-01 is: 2969 ICS8725BY-01 REVISION A JULY 16, 2009 16 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Package Outline and Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 9. Package Dimensions for 32 Lead LQFP JEDEC Variation: BBA All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 θ 0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 ICS8725BY-01 REVISION A JULY 16, 2009 17 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Ordering Information Table 10. Ordering Information Part/Order Number 8725BY-01 8725BY-01T 8725BY-01LF 8725BY-01LFT Marking ICS8725BY-01 ICS8725BY-01 ICS8725BY01L ICS8725BY01L Package 32 Lead LQFP 32 Lead LQFP “Lead-Free” 32 Lead LQFP “Lead-Free” 32 Lead LQFP Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS8725BY-01 REVISION A JULY 16, 2009 18 ©2009 Integrated Device Technology, Inc. ICS8725B-01 Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 DIFFERENTIAL-TO-HSTL ZERO DELAY CLOCK GENERATOR Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. 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