8732AY-01LFT

8732-01 Low Voltage, Low Skew 3.3V LVPECL Clock Generator Data Sheet GENERAL DESCRIPTION Features The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock Generator. The 8732-01 has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single ended clock input accepts LVCMOS or LVTTL input levels. The 8732-01 has a fully integrated PLL along with frequency configurable outputs. An external feedbackinput and outputs regenerate clocks with “zero delay”. • Ten differential 3.3V LVPECL outputs The 8732-01 has multiple divide select pins for each bank of outputs along with 3 independent feedback divide select pins allowing the 8732-01 to function both as a frequency multiplier and divider. The PLL_SEL input can be usedto bypass the PLL for test and system debug purposes.In bypass mode, the input clock is routed around the PLLand into the internal output dividers. • Maximum output frequency: 350MHz • Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL CLK1 inputs • CLK0, nCLK0 supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK1 accepts the following input levels: LVCMOS or LVTTL • VCO range: 250MHz to 700MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum) CLK1, 80ps (maximum) • Output skew: 150ps (maximum) • Static phase offset: -150ps to 150ps • Lead-Free package fully RoHS compliant VCCO QFB1 nQFB1 QFB0 nQFB0 VEE VCC FB_IN nFB_IN FBDIV_SEL0 FBDIV_SEL1 FBDIV_SEL2 PIN ASSIGNMENT VEE BLOCK DIAGRAM VCCO 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 VCCO QA0 2 38 nQB3 nQA1 5 35 QB2 VEE 6 34 VEE PLL_SEL 7 33 MR ICS8732-01 VCCO VCCO 31 nQA2 10 30 QA3 11 29 nQB0 nQA3 12 28 QB0 VEE DIV_SELB0 VCC nc DIV_SELB1 VCCA CLK_SEL CLK0 nCLK0 CLK1 VEE VCC DIV_SELA0 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 DIV_SELA1 VEE QB1 52-Lead LQFP 10mm x 10mm x 1.4mm package body Y package Top View ©2016 Integrated Device Technology, Inc 1 Revision E January 22, 2016 8732-01 Data Sheet TABLE 1. PIN DESCRIPTIONS Number 1, 8, 32, 39, 40 2, 3, 4, 5 6, 13, 17, 27, 34, 45, 52 Name Type Description VCCO Power Output supply pins. QA0, nQA0, QA1, nQA1 Output Differential output pair. LVPECL interface levels. VEE Power Negative supply pins. 7 PLL_SEL Input 9, 10, 11, 12 QA2, nQA2, QA3, nQA3 Output 14 DIV_SELA1 Input 15 DIV_SELA0 Input 16, 26, 46 VCC Power 18 CLK1 Input 19 nCLK0 Input 20 CLK0 Input Pulldown Non-inverting differential clock input. 21 CLK_SEL Input Pulldown 22 VCCA Power 23 nc Unused 24 DIV_SELB1 Input 25 DIV_SELB0 Input 28, 29, 30, 31 QB0, nQB0, QB1, nQB1 Output 33 MR Input 35, 36, 37, 38 41, 42, 43, 44 QB2, nQB2, QB3, nQB3 QFB1, nQFB1, QFB0, nQFB0 47 FB_IN Input 48 nFB_IN Input 49 FBDIV_SEL0 Input 50 FBDIV_SEL1 Input 51 FBDIV_SEL2 Input Pullup Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock. When HIGH, selects PLL. LVCMOS / LVTTL interface levels. Differential output pairs. LVPECL interface levels. Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Core supply pins. Pulldown LVCMOS / LVTTL reference clock input. Pullup Inverting differential clock input. Clock select input. When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1. LVCMOS / LVTTL interface levels. Analog supply pin. No connect. Determines output divider valued in Table 3. LVCMOS / LVTTL interface levels. Determines output divider valued in Table 3. Pulldown LVCMOS / LVTTL interface levels. Pulldown Differential output pairs. LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs Pulldown nQx to go high. When LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Output Differential output pairs. LVPECL interface levels. Output Differential feedback output pairs. LVPECL interface levels. Feedback input to phase detector for regenerating clocks with “zero delay”. Feedback input to phase detector for regenerating clocks Pullup with “zero delay”. Selects divide value for differential feedback output pairs. Pulldown LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. Pulldown LVCMOS / LVTTL interface levels. Selects divide value for differential feedback output pairs. Pulldown LVCMOS / LVTTL interface levels. Pulldown NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. ©2016 Integrated Device Technology, Inc 2 Revision E January 22, 2016 8732-01 Data Sheet TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance RPULLUP RPULLDOWN Minimum Typical Maximum Units 4 pF Input Pullup Resistor 51 kΩ Input Pulldown Resistor 51 kΩ TABLE 3A. CONTROL INPUT FUNCTION TABLE FOR QA0:QA3 OUTPUTS Inputs Outputs MR PLL_SEL DIV_SELA1 DIV_SELA0 QA0:QA3, nQA0:nQA3 1 X X X Low 0 1 0 0 fVCO/2 0 1 0 1 fVCO/4 0 1 1 0 fVCO/6 0 1 1 1 fVCO/8 0 0 0 0 fREF_CLK/2 0 0 0 1 fREF_CLK/4 0 0 1 0 fREF_CLK/6 0 0 1 1 fREF_CLK/8 TABLE 3B. CONTROL INPUT FUNCTION TABLE FOR QB0:QB3 OUTPUTS Inputs Outputs MR PLL_SEL DIV_SELB1 DIV_SELB0 1 X X X Low 0 1 0 0 fVCO/2 0 1 0 1 fVCO/4 0 1 1 0 fVCO/8 0 1 1 1 fVCO/12 0 0 0 0 fREF_CLK/2 0 0 0 1 fREF_CLK/4 0 0 1 0 fREF_CLK/8 0 0 1 1 fREF_CLK/12 ©2016 Integrated Device Technology, Inc QB0:QB3, nQB0:nQB3 3 Revision E January 22, 2016 8732-01 Data Sheet TABLE 3C. CONTROL INPUT FUNCTION TABLE FOR QFB0, QFB1 Inputs Outputs MR PLL_SEL FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 QFB0, QFB1 nQFB0, nQFB1 1 X X X X Low 0 1 0 0 0 fVCO/4 0 1 0 0 1 fVCO/6 0 1 0 1 0 fVCO/8 0 1 0 1 1 fVCO/10 0 1 1 0 0 fVCO/8 0 1 1 0 1 fVCO/12 0 1 1 1 0 fVCO/16 0 1 1 1 1 fVCO/20 0 0 0 0 0 fREF_CLK/4 0 0 0 0 1 fREF_CLK/6 0 0 0 1 0 fREF_CLK/8 0 0 0 1 1 fREF_CLK/10 0 0 1 0 0 fREF_CLK/8 0 0 1 0 1 fREF_CLK/12 0 0 1 1 0 fREF_CLK/16 0 0 1 1 1 fREF_CLK/20 TABLE 4A. QX OUTPUT FREQUENCY W/FB_IN = QFB0 OR QFB1 Inputs fVCO FB_IN FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 Output Divider Mode QFB 0 0 0 QFB 0 0 1 QFB 0 1 QFB 0 1 QFB 1 0 QFB 1 0 QFB 1 QFB 1 CLK1 (MHz) (NOTE 1) Minimum Maximum ÷4 62.5 175 (NOTE 2) fREF_CLK x 4 ÷6 41.67 116.67 fREF_CLK x 6 0 ÷8 31.25 87.5 fREF_CLK x 8 1 ÷10 25 70 fREF_CLK x 10 0 ÷8 31.25 87.5 fREF_CLK x 8 1 ÷12 20.83 58.33 fREF_CLK x 12 1 0 ÷16 15.62 43.75 fREF_CLK x 16 1 1 ÷20 12.5 35 fREF_CLK x 20 NOTE 1: VCO frequency range is 250MHz to 700MHz. NOTE 2: The maximum input frequency that the phase detector can accept is 175MHz. ©2016 Integrated Device Technology, Inc 4 Revision E January 22, 2016 8732-01 Data Sheet ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 42.3°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V ICC Power Supply Current 165 mA ICCA Analog Supply Current 15 mA TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH Parameter Input High Voltage Maximum Units CLK1 Test Conditions 2 VCC+ 0.3 V CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, MR 2 VCC+ 0.3 V -0.3 1.3 V -0.3 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA CLK1 VIL Input Low Voltage IIH Input High Current CLK_SEL, PLL_SEL, DIV_SELAx, DIV_SELBx, FBDIV_SELx, MR CLK_SEL, MR, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx PLL_SEL IIL Input Low Current Minimum Typical CLK_SEL, MR, CLK1 DIV_SELAx, DIV_SELBx, FBDIV_SELx VCC = 3.465V, VIN = 0V -5 µA PLL_SEL VCC = 3.465V, VIN = 0V -150 µA ©2016 Integrated Device Technology, Inc 5 Revision E January 22, 2016 8732-01 Data Sheet TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH Parameter Input High Current Test Conditions CLK0, FB_IN nCLK0, nFB_IN Minimum Typical VCC = VIN = 3.465V VCC = VIN = 3.465V Maximum Units 150 µA 5 µA CLK0, FB_IN VCC = 3.465V, VIN = 0V -5 µA nCLK0, nFB_IN VCC = 3.465V, VIN = 0V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 0.15 1.3 V VEE + 0.5 VCC - 0.85 V Maximum Units V NOTE 1: For single ended applications, the maximum input voltage for FB_IN, nFB_IN is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 5D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units 200 MHz Maximum 350 Units MHz 150 ps NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fREF Input Reference Frequency Test Conditions Minimum Typical TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol fMAX Parameter Output Frequency t(Ø) Static Phase Offset; NOTE 1 tsk(o) Output Skew; NOTE 2, 3, 4 tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 Test Conditions Minimum PLL_SEL = 3.3V, fREF = 100MHz, fVCO = 400MHz -150 Typical 150 ps CLK0, nCLK 50 ps CLK1 80 PLL Lock Time 10 tL tR / tF Output Rise/Fall Time 20% to 80% 200 700 odc Output Duty Cycle 48 52 fOUT ≤ 175MHz All parameters measured at fMAX unless noted otherwise. NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal when the PLL is locked and the input reference frequency is stable. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: All outputs in divide by 4 configuration. ©2016 Integrated Device Technology, Inc 6 ps ms ps % Revision E January 22, 2016 8732-01 Data Sheet PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW CYCLE-TO-CYCLE JITTER STATIC PHASE OFFSET OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ©2016 Integrated Device Technology, Inc 7 Revision E January 22, 2016 8732-01 Data Sheet APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to FIGURE 2A. LVPECL OUTPUT TERMINATION ©2016 Integrated Device Technology, Inc FIGURE 2B. LVPECL OUTPUT TERMINATION 8 Revision E January 22, 2016 8732-01 Data Sheet POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 8732-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 3 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 3. POWER SUPPLY FILTERING DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 4A. CLK/NCLK INPUT DRIVEN BY LVHSTL DRIVER FIGURE 4B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Receiv er R2 84 FIGURE 4C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER ©2016 Integrated Device Technology, Inc nCLK Zo = 50 Ohm FIGURE 4D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 9 Revision E January 22, 2016 8732-01 Data Sheet LAYOUT GUIDELINE Figure 5 shows a schematic example of the 8732-01. In this example, the CLK0/nCLK0 input is selected. The decoupling capacitors should be physically located near the power pin. For 8732-01, the unused outputs can be left floating. Zo = 50 + VCC R14 1K Zo = 50 - VCC VCC R4 50 10 C16 10uF C11 0.1uF DIV_SELA1 DIV_SELA0 VCC Zo = 50 Zo = 50 R1 50 R2 50 DIV_SELA1 DIV_SELA0 VCC VEE CLK1 nCLK0 CLK0 CLK_SEL VCCA nc DIV_SELB1 DIV_SELB0 VCC 52 51 50 49 48 47 46 45 44 43 42 41 40 VEE FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 nFB_IN FB_IN VCC VEE nQFB0 QFB0 nQFB1 QFB1 VCCO FBDIV_SEL2 FBDIV_SEL1 FBDIV_SEL0 R10 50 R13 1K R11 50 R12 50 27 28 29 30 31 32 33 34 35 36 37 38 39 R3 50 DIV_SELB1 DIV_SELB0 R6 50 VEE QB0 nQB0 QB1 nQB1 VCCO MR VEE QB2 nQB2 QB3 nQB3 VCCO LVPECL 14 15 16 17 18 19 20 21 22 23 24 25 26 R5 50 U1 ICS8732-01 VEE nQA3 QA3 nQA2 QA2 VCCO PLL_SEL VEE nQA1 QA1 nQA0 QA0 VCCO R7 13 12 11 10 9 8 7 6 5 4 3 2 1 VCCA Zo = 50 Logic Input Pin Examples VCC Set Logic Input to '1' RU1 1K VCC + Set Logic Input to '0' RU2 SP Zo = 50 SP = Spare (i.e. not intstalled) (U1-1) To Logic Input pins RD1 SP To Logic Input pins RD2 1K - VCC=3.3V VCC C1 0.1uF (U1-8) C2 0.1uF (U1-16) R8 50 (U1-26) C3 0.1uF C4 0.1uF (U1-32) (U1-39) C5 0.1uF (U1-40) C6 0.1uF C7 0.1uF R7 50 (U1-46) C8 0.1uF R9 50 Bypass capacitors located near the power pins FIGURE 5. 8732-01 LVPECL BUFFER SCHEMATIC EXAMPLE ©2016 Integrated Device Technology, Inc 10 Revision E January 22, 2016 8732-01 Data Sheet POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 8732-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 8732-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 165mA = 572mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 10 * 30mW = 300mW Total Power_MAX (3.465V, with all outputs switching) = 572mW + 300mW = 872mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4°C/W per Table 8 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.872W * 36.4°C/W = 101.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 8. THERMAL RESISTANCE θJA FOR 52-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W 200 500 47.1°C/W 36.4°C/W 42.0°C/W 34.0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ©2016 Integrated Device Technology, Inc 11 Revision E January 22, 2016 8732-01 Data Sheet 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ©2016 Integrated Device Technology, Inc 12 Revision E January 22, 2016 8732-01 Data Sheet RELIABILITY INFORMATION TABLE 9. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 58.0°C/W 42.3°C/W 200 500 47.1°C/W 36.4°C/W 42.0°C/W 34.0°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 8732-01 is: 4916 ©2016 Integrated Device Technology, Inc 13 Revision E January 22, 2016 8732-01 Data Sheet PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP TABLE 10. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL BCC MINIMUM NOMINAL N MAXIMUM 52 A -- A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.22 0.32 0.38 c 0.09 -- 0.20 -- D 12.00 BASIC D1 10.00 BASIC E 12.00 BASIC E1 10.00 BASIC e 1.60 0.65 BASIC L 0.45 -- θ 0° -- 7° ccc -- -- 0.08 0.75 Reference Document: JEDEC Publication 95, MS-026 ©2016 Integrated Device Technology, Inc 14 Revision E January 22, 2016 8732-01 Data Sheet TABLE 11. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 8732AY-01LF ICS8732AY-01LF 52 lead “Lead Free” LQFP Tube 0°C to +70°C 8732AY-01LFT ICS8732AY-01LF 52 lead “Lead Free” LQFP Tape and Reel 0°C to +70°C ©2016 Integrated Device Technology, Inc 15 Revision E January 22, 2016 8732-01 Data Sheet REVISION HISTORY SHEET Rev Table Page Description of Change T2 T4A 1 3 4 Features Section - changed VCO min. from 200MHz to 250MHz. Pin Characteristics Table - changed CIN from max. 4pF to typical 4pF. Qx Output Frequency Table - changed the CLK1 min. column to correlate with the VCO change. Absolute Maximum Ratings - changed VO to IO and included Continuous Current and Surge Current Added Differential Clock Input Interface in the Application Information section. B 5 8 C T5A 5 8 10 1 C C Date Power Supply DC Characteristics Table - changed IEE from 240mA max. to 165mA max., and ICCA from 14mA max. to 15mA max. Power Considerations - recalculated Power Dissipation and Junction Temperatures to correspond with Table 5A. Updated LVPECL Output Termination diagrams. Added Schematic Layout. 5/20/03 6/23/03 9/24/03 Block Diagram - changed REF_SEL to CLK_SEL. 3/3/04 C T11 15 Ordering Information Table - corrected Tape & Reel Count to read 500 from 1000. 4/29/04 C T4A 4 Qx Output Frequency Table - changed NOTE 2 from “200MHz” to “175MHz”. 10/19/04 T11 T5A 1 15 5 Features Section - added Lead Free bullet. Ordering Information Table - added Lead Free part number and note. 5/23/05 Power Supply DC Characteristics Table - corrected IEE to read ICC. 5/31/05 T5D 6 LVPECL DC Characteristics Table -corrected VOH max. from VCCO - 1.0V to VCCO 0.9V. Power Considerations - corrected power dissipation to reflect VOH max in Table 5D. 4/13/07 C C D 11 - 12 E T11 E T5D E T11 15 17 9 15 Updated datasheet’s header/footer with IDT from ICS. Removed ICS prefix from Part/Order Number column. Added Contact Page. VOH Maximum = VCCO - 0.9 7/31/10 5/2/13 Removed ICS in the part number where needed. Ordering Information - removed quantity from tape and reel. Deleted LF note below the table. Update header and footer. ©2016 Integrated Device Technology, Inc 16 1/22/16 Revision E January 22, 2016 8732-01 Data Sheet Corporate Headquarters 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. 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