87332I-01
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The 87332I-01 is a high performance ÷2 Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator. The CLK, nCLK pair can accept
most standard differential input levels The 87332I-01 is characterized
to operate from either a 2.5V or a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make the 87332I-01
ideal for those clock distribution applications demanding well defined
performance and repeatability.
• One ÷2 differential 2.5V/3.3V LVPECL / ECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 500MHz
• Maximum input frequency: 1GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.6ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
CLK
nCLK
÷2
PIN ASSIGNMENT
MR
CLK
nCLK
nc
Q
nQ
1
2
3
4
8
7
6
5
Vcc
Q
nQ
VEE
87332I-01
MR
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
87332AMI-01 REVISION C 2/12/15
1
©2015 Integrated Device Technology, Inc.
87332AMI-01 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
MR
Input
Master reset. When LOW, outputs are enabled. When HIGH,
Pulldown divider is reset forcing Q output LOW and nQ output HIGH.
LVCMOS / LVTTL interface level.
2
CLK
Input
Pulldown Non-inverting differential clock input.
3
nCLK
Input
4
nc
Unused
Pullup
Inverting differential clock input.
No connect.
5
VEE
Power
Negative supply pin.
6, 7
Q, nQ
Output
Differential output pair. LVPECL interface levels.
8
VCC
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
Units
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CLK
MR
Q
FIGURE 1. TIMING DIAGRAM
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
2
REVISION C 2/12/15
87332AMI-01 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5 V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
112.7°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
Parameter
VCC
Positive Supply Voltage
Test Conditions
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
2.375
3.3
3.8
V
30
mA
TABLE 3B. LVCMOS DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VIH
Input High Voltage
MR
VIL
Input Low Voltage
MR
IIH
Input High Current
MR
VCC = VIN = 3.8V
IIL
Input Low Current
MR
VCC = 3.8V, VIN = 0V
Minimum
Typical
2
-0.3
Maximum
Units
VCC + 0.3
V
0.8
V
150
µA
-5
µA
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
Parameter
IIH
Input High Current
Test Conditions
CLK
Minimum
Typical
VCC = VIN = 3.8V
Units
150
µA
5
µA
nCLK
VCC = VIN = 3.8V
CLK
VCC = 3.8V, VIN = 0V
-5
µA
nCLK
VCC = 3.8V, VIN = 0V
-150
µA
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
VEE + 0.5
VCMR
NOTE 1, 2
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
REVISION C 2/12/15
Maximum
3
1.3
V
VCC - 0.85
V
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.65
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4. AC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Input Frequency
tPD
Propagation Delay; NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
Test Conditions
Minimum
Typical
Maximum
Units
1
GHz
ƒ ≤ 1GHz
1.1
1.4
1.6
ns
400
ps
tR
Output Rise Time
20% to 80%
200
700
ps
tF
Output Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
49
51
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
4
REVISION C 2/12/15
87332AMI-01 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART-TO-PART SKEW
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
REVISION C 2/12/15
5
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single
ended levels. The reference voltage V_REF = VCC/2 is generated by
the bias resistors R1, R2 and C1. This bias circuit should be located
as close as possible to the input pin. The ratio of R1 and R2 might
need to be adjusted to position the V_REF in the center of the input
voltage swing. For example, if the input clock swing is only 2.5V and
VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
FIGURE 3A. LVPECL OUTPUT TERMINATION
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
R2
84
FIGURE 3B. LVPECL OUTPUT TERMINATION
6
REVISION C 2/12/15
87332AMI-01 DATA SHEET
TERMINATION FOR 2.5V LVPECL OUTPUTS
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 4B can be eliminated and the termination is
shown in Figure 4C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
REVISION C 2/12/15
7
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 5A to 5F show interface
examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm
the driver termination requirements. For example in Figure 5A, the
input termination applies for IDT open emitter LVHSTL drivers. If
you are using an LVHSTL driver from another vendor, use their
termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 5A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN
EMITTER LVHSTL DRIVER
FIGURE 5B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL
DRIVER
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 5C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL
DRIVER
FIGURE 5D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
FIGURE 5E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER
FIGURE 5F. CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
8
REVISION C 2/12/15
87332AMI-01 DATA SHEET
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 87332I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 87332I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 30mA = 114mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.8V, with all outputs switching) = 114mW + 30mW = 144mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature for HiPerClockSTM devices is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C
ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.144W * 103.3°C/W = 99.9°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (multi-layer).
TABLE 5. THERMAL RESISTANCE θJA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REVISION C 2/12/15
9
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX - VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
10
REVISION C 2/12/15
87332AMI-01 DATA SHEET
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 87332I-01 is: 383
Compatible to part number MC100EP32
PACKAGE OUTLINE AND DIMENSIONS
TABLE 7. PACKAGE DIMENSIONS
PACKAGE OUTLINE - M SUFFIX
SYMBOL
Millimeters
MINIMUN
N
MAXIMUM
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
e
4.00
1.27 BASIC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
REVISION C 2/12/15
11
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332AMI-01 DATA SHEET
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Package
Temperature
87332AMI-01LF
332AI01L
8 lead “Lead-Free” SOIC
tube
-40°C to 85°C
87332AMI-01LFT
332AI01L
8 lead “Lead-Free” SOIC
tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
12
REVISION C 2/12/15
87332AMI-01 DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
1
2
6
6
7
8
13
T2
B
T8
T3D
4
C
T4
C
C
T8
REVISION C 2/12/15
9 - 10
4
6
8
12
12
Description of Change
Date
Features Section - added Lead-Free bullet.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added “Wiring the Differential Input to Accept Single Ended Levels.
Added Termination for 3.3V LVPECL Output.
Added Termination for 2.5V LVPECL Output.
Added Differential Clock Input Interface.
Ordering Information Table - corrected marking. Added Lead-Free part number
and note.
Updated format of datasheet.
LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to
VCC - 0.9V; and VSWING max. from 0.9V to 1.0V.
Power Considerations - corrected power dissipation to reflect VOH max in Table 3D.
Added thermal note to AC Characteristics table.
Updated figures 3A & 3B, LVPECL Output Termination diagrams.
Updated Differential Clock Input Interface.
Ordering Information Table - add LF marking. Deleted “ICS” prefix from part/order number.
Updated header/footer of datasheet.
Ordering Information - removed leaded devices - PDN CQ-13-02
13
7/5/05
4/13/07
11/16/09
2/12/15
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
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6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.
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