700MHz, Differential-to-3.3V LVPECL
Zero Delay Clock Generator
8735BI-21
DATA SHEET
General Description
Features
The 8735BI-21 is a highly versatile 1:1 Differential-to-3.3V LVPECL
clock generator. The CLK, nCLK pair can accept most standard
differential input levels. The 8735BI-21 has a fully integrated PLL and
can be configured as zero delay buffer, multiplier or divider, and has
an output frequency range of 31.25MHz to 700MHz. The reference
divider, feedback divider and output divider are each programmable,
thereby allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the
device to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for system
test and debug purposes. In bypass mode, the reference clock is
routed around the PLL and into the internal output dividers.
• One differential 3.3V LVPECL output pair, one differential feedback
output pair
• Differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input levels:
LVDS, LVPECL, LVHSTL, HCSL
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• External feedback for “zero delay” clock regeneration with
configurable frequencies
Pin Assignment
• Cycle-to-cycle jitter: 50ps (maximum)
CLK
1
20
nc
nCLK
MR
2
19
3
18
SEL1
SEL0
VCC
nFB_IN
FB_IN
SEL2
VEE
4
17
5
16
6
15
7
14
8
13
VCC
PLL_SEL
VCCA
SEL3
VCCO
nQFB
9
12
Q
QFB
10
11
nQ
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in RoHS compliant package
Block Diagram
PLL_SEL
÷1, ÷2, ÷4, ÷8,
8735BI-21
÷16, ÷32, ÷64
29
nc
VCCA
30
nc
PLL_SEL
31
VEE
VCC
32
SEL3
nc
20-pin, 7.5mm x 12.8mm X 2.3MM SOIC Package
28
27
26
25
CLK
nCLK
FB_IN
nFB_IN
SEL0
24
VCCO
SEL1
2
23
nc
nc
3
22
Q
nc
4
21
nQ
SEL0
20
QFB
SEL1
7
18
nc
SEL3
MR
8
17
Vcco
10
11
12
13
14
15
16
nc
nc
nc
SEL2
VEE
nQFB
SEL2
19
FB_IN
6
nFB_IN
nCLK
nc
5
VCC
CLK
9
Q
nQ
1
QFB
nQFB
PLL
1
8735BI-21
0
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
MR
32-pin, 5mm x 5mm X 0.925MM VFQFN Package
8735BI-21 REVISION 1 1/27/15
1
©2015 Integrated Device Technology, Inc.
8735BI-21 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions1
Name
Type
Description
CLK
Input
Pulldown
Non-inverting differential clock input.
nCLK
Input
Pullup
Inverting differential clock input.
nFB_IN
Input
Pullup
Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to nQFB.
FB_IN
Input
Pulldown
Feedback input to phase detector for regenerating clocks with “zero delay”. Connect to QFB.
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the
true outputs Q and QFB to go low and the inverted outputs nQ and nQFB to go high. When
LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
SEL0, SEL1,
SEL2, SEL3
Input
Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
PLL_SEL
Input
Pullup
nQ, Q
Output
Differential feedback outputs. LVPECL interface levels.
nQFB, QFB
Output
Differential feedback outputs. LVPECL interface levels.
VEE
Power
Negative supply.
VCC
Power
Core supply.
VCCA
Power
Analog supply.
VCCO
Power
Output supply.
Selects between the PLL and reference clock as the input to the dividers. When LOW,
selects reference clock. When HIGH, selects PLL.
LVCMOS / LVTTL interface levels.
NOTE 1: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
RPULLDOWN
Test Conditions
Typical
Maximum
Units
4
pF
Input Pullup Resistor
51
k
Input Pulldown Resistor
51
k
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
IN, nIN
Minimum
2
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Table 3A. Control Input Function Table1
Outputs
PLL_SEL = 1
PLL Enable Mode
Inputs
SEL3
SEL2
SEL1
SEL0
Reference Frequency Range (MHz)
Q, nQ; QFB, nQFB
0
0
0
0
250-700
÷ 1 (default)
0
0
0
1
125 - 350
÷1
0
0
1
0
62.5 - 175
÷1
0
0
1
1
31.25 - 87.5
÷1
0
1
0
0
250 - 700
÷2
0
1
0
1
125 - 350
÷2
0
1
1
0
62.5 - 175
÷2
0
1
1
1
250 - 700
÷4
1
0
0
0
125 - 350
÷4
1
0
0
1
250 - 700
÷8
1
0
1
0
125 - 350
x2
1
0
1
1
62.5 - 175
x2
1
1
0
0
31.25 - 87.5
x2
1
1
0
1
62.5 - 175
x4
1
1
1
0
31.25 - 87.5
x4
1
1
1
1
31.25 - 87.5
x8
NOTE 1: VCO frequency range for all configurations above is 250MHz to 700MHz.
Table 3B. PLL Bypass Function Table1
Outputs
PLL_SEL = 0
PLL Bypass Mode
Inputs
SEL3
SEL2
SEL1
SEL0
Q, nQ; QFB, nQFB
0
0
0
0
÷ 4 (default)
0
0
0
1
÷4
0
0
1
0
÷4
0
0
1
1
÷8
0
1
0
0
÷8
0
1
0
1
÷8
0
1
1
0
÷ 16
0
1
1
1
÷ 16
1
0
0
0
÷ 32
1
0
0
1
÷ 64
1
0
1
0
÷2
1
0
1
1
÷2
1
1
0
0
÷4
1
1
0
1
÷1
1
1
1
0
÷2
1
1
1
1
÷1
NOTE 1: VCO frequency range for all configurations above is 250MHz to 700MHz.
REVISION 1 1/27/15
3
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical
Characteristics” or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
Item
Rating
Supply Voltage, VCC_X
4.6V
Inputs, VCC
-0.5V to VCC + 0.5V
Outputs, VCCO
-0.5V to VCCO + 0.5V
Junction Temperature, TJ
125°C
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 3.3V ±5%, TA = -40°C to 85°C
Symbol
Parameter
VCC
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
VCCA
Analog Supply Voltage
3.135
3.3
3.465
V
VCCO
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
155
mA
ICCA
Analog Supply Current
17
mA
Maximum
Units
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VCC = VCCO = 3.3V ±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High
Current
IIL
Input Low
Current
Test Conditions
Minimum
Typical
SEL0, SEL1,
SEL2, SEL3, MR
VCC = VIN = 3.465V
150
µA
PLL_SEL
VCC = VIN = 3.465V
5
µA
SEL0, SEL1,
SEL2, SEL3, MR
VCC = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VCC = 3.465V, VIN = 0V
-150
µA
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
4
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Table 4C. Differential Input DC Characteristics, VCC = VCCO = 3.3V ±5%, TA = -40°C to 85°C
Symbol
Parameter
IIH
Input High
Current
IIL
Input Low
Current
VPP
VCMR
Test Conditions
Minimum
Typical
Maximum
Units
CLK, FB_IN
VCC = VIN = 3.465V
150
µA
nCLK, nFB_IN
VCC = VIN = 3.465V
5
µA
CLK, FB_IN
VCC = 3.465V, VIN = 0V
-5
µA
nCLK, nFB_IN
VCC = 3.465V, VIN = 0V
-150
µA
Peak-to-Peak Voltage
1
Common Mode Input Voltage
2, 3
0.15
1.3
V
VEE + 0.5V
VCC – 0.85
V
Maximum
Units
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
NOTE 3: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ±5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Output High
Voltage1
VCCO – 1.4
VCCO – 0.9
V
VOL
Output Low
Voltage1
VCCO – 2.1
VCCO – 1.7
V
VSWING
Peak-to-Peak Voltage Swing
0.6
1.0
V
Maximum
Units
700
MHz
700
MHz
VOH
NOTE 1: Outputs terminated with 50 to VCCO – 2V.
Table 5. Input Frequency Characteristics, VCC = VCCO = 3.3V ±5%, TA = 0°C to 85°C
Symbol
Parameter
fIN
Input Frequency
REVISION 1 1/27/15
CLK, nCLK
Test Conditions
Minimum
PLL_SEL = 1
31.25
PLL_SEL = 0
5
Typical
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
AC Electrical Characteristics
Table 6. Input Frequency Characteristics, VCC = VCCO = 3.3V ±5%, TA = 0°C to 85°C1
Symbol
Parameter
fOUT
Output Frequency
tPD
tsk(o)
t(Ø)
tjit(cc)
Propagation
Test Conditions
PLL_SEL = 0V, f 700MHz
Delay2
3, 4
Offset4, 5
Cycle-to-Cycle Jitter
2.8
PLL_SEL = 0V
Output Skew
Static Phase
Minimum
PLL_SEL = 3.3V
-100
4, 6
Jitter4, 6, 7
tjit()
Phase
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Typical
Maximum
Units
700
MHz
4.9
ns
35
ps
200
ps
50
ps
±80
ps
1
ms
20% to 80% @ 50MHz
200
700
ps
fOUT 250MHz
47
53
%
NOTE 1: All parameters measured at fOUT unless noted otherwise.
NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
NOTE 6: Characterized at VCO frequency of 622MHz,.
NOTE 7: Phase jitter is dependent on the input source used.
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
6
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Parameter Measurement Information
2V
VCC
VCC,
VCCA,
VCCO
Qx
SCOPE
nCLK
V
V
Cross Points
PP
CMR
CLK
nQx
VEE
VEE
1.3V± 0.165V
3.3V Output Load Test Circuit
Differential Input Level
nCLK
VOH
CLK
VOL
nFB_IN
FB_IN
VOH
Qx
VOL
nQy
➤
➤ t(Ø)
nQx
tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter
t(Ø) mean = Static Phase Offset
Qy
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges)
Phase Jitter and Static Phase Offset
Output Skew
nQ, nQFB
80%
80%
Q, QFB
VSW I N G
tcycle n
tcycle n+1
Clock
Outputs
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Cycle-to-Cycle Jitter
20%
20%
tR
tF
Output Rise/Fall Time
nQ, nQFB
nCLK
Q, QFB
CLK
nQ, nQFB
Q, QFB
tPD
Output Duty Cycle/Pulse Width/Period
REVISION 1 1/27/15
Propagation Delay
7
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Suggested edge
rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the
layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a
differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8
REVISION 1 1/27/15
8735BI-21 DATA SHEET
3.3V Differential Clock Input Interface
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figure 2A to Figure 2E show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. Figure 2E.CLK/nCLK Input Driven by a 3.3V
LVDS Driver
REVISION 1 1/27/15
9
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figure 3A and Figure 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential output is a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 3A. 3.3V LVPECL Output Termination
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
R2
84
Figure 3B. 3.3V LVPECL Output Termination
10
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Schematic Example
Figure 4 shows a schematic example of the 8735BI-21. In this
example, the input is driven by an HCSL driver. The zero delay buffer
is configured to operate at 155.52MHz input and 77.75MHz output.
The logic control pins are configured as follows:
SEL [3:0] = 0101; PLL_SEL = 1. The decoupling capacitors should
be physically located near the power pin. For 8735BI-21.
3.3V
R7
VCC
VCCA
U1
Zo = 50 Ohm
10
(155.5 MHz)
1
2
3
4
5
6
7
8
9
10
VCC
Zo = 50 Ohm
SEL2
HCSL
R8
50
R9
50
nc
SEL1
SEL0
VCCI
PLL_SEL
VCCA
SEL3
VCCO
Q
nQ
CLK
nCLK
MR
VCCI
nFB_IN
FB_IN
SEL2
VEE
nQFB
QFB
20
19
18
17
16
15
14
13
12
11
C11
0.01u
SEL1
SEL0
VCC
PLL_SEL
VCCA
SEL3
VCC
C16
10u
Zo = 50 Ohm
+
Zo = 50 Ohm
VCC
RU3
1K
R1
50
RU4
1K
RU5
SP
RU6
1K
R2
50
ICS8735-21
-
PLL_SEL
SEL0
SEL1
SEL2
SEL3
R4
50
R3
50
Bypass capacitors located
near the power pins
(U1-4) VCC
RD3
SP
RD4
SP
RD5
1K
RD6
SP
LVPECL_input
(77.75 MHz)
RU7
SP
RD7
1K
SP = Space (i.e. not intstalled)
(U1-17)
R5
50
R6
50
(U1-13)
VCC=3.3V
C1
0.1uF
C2
0.1uF
C3
0.1uF
SEL[3:0] = 0101,
Divide by 2
Figure 4. 8735BI-21 LVPECL Buffer Schematic Example
REVISION 1 1/27/15
11
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Lead frame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
12
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8735BI-21.
Equations and example calculations are also provided.
Max ICC_MA at worst case:
85°C = 133mA
1.
Power Dissipation.
The total power dissipation for the 8735BI-21 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
•
Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 155mA = 537mW
•
Power (outputs)MAX = 30mW/Loaded output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX = (3.465V, with all outputs switching) = 537mW + 60mW = 597mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures
that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 46.2°C/W per Table 7A, and 33.1°C/W per Table 7B below:
Therefore, Tj for an ambient temperature of 85°C with all outputs switching for 20-Lead SOIC is:
85°C + 0.597W * 46.2°C/W = 112.6°C. This is below the limit of 125°C.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching for 32-Lead VFQFN is:
85°C + 0.597W * 33.1°C/W = 104.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7A. Thermal Resistance JA for 20 Lead SOIC, Forced Convection
JA vs. Air Flow
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
46.2°C/W
39.7°C/W
36.8°C/W
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Table 7B. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
REVISION 1 1/27/15
13
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate power dissipation due to loading, use the following equations which assume a 50 load, and a termination voltage of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V
(VCCO_MAX – VOH_MAX) = 0.9V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V
(VCCO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.9V)/50] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.7V)/50] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
14
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Reliability Information
Table 8A. JA vs. Air Flow Table for a 20 Lead SOIC
JA vs. Air Flow
Linear Feet per Minute
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
46.2°C/W
39.7°C/W
36.8°C/W
0
1
3
33.1°C/W
28.1°C/W
25.4°C/W
Table 8B. JA vs. Air Flow Table for a 32 Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Transistor Count
The transistor count for 8735BI-21 is: 2969
Package Outline and Package Dimensions
Package Outline - M Suffix for 20 Lead SOIC
Table 9A. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
20
A
2.65
A1
0.10
A2
2.05
2.55
B
0.33
0.51
C
0.18
0.32
D
12.60
13.00
E
7.40
7.60
e
1.27 Basic
H
10.00
10.65
h
0.25
0.75
L
0.40
1.27
0°
7°
Reference Document: JEDEC Publication 95, MS-013, MS-119
REVISION 1 1/27/15
15
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
8735BI-21 DATA SHEET
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
L
A3
N
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
Bottom View w/Type A ID
4
Th er mal
Ba se
D2
C
Bottom View w/Type C ID
2
1
2
1
CHAMFER
D2
2
N N-1
RADIUS
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9B. Package Dimensions
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pin-out are shown on the front page. The
package dimensions are in Table 9B.
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.25
0.30
8
ND & NE
D&E
5.00 Basic
D2 & E2
3.0
3.3
e
0.50 Basic
L
0.30
0.40
0.50
Reference Document: JEDEC Publication 95, MO-220
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
16
REVISION 1 1/27/15
8735BI-21 DATA SHEET
Ordering Information
Table 10. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8735BMI-21LF
8735BMI-21LF
20 Lead SOIC, Lead-Free
Tube
-40°C to 85°C
8735BMI-21LFT
8735BMI-21LF
20 Lead SOIC, Lead-Free
Tape & Reel
-40°C to 85°C
8735BKI-21LF
735BI21L
32 Lead VFQFN, Lead-Free
Tray
-40°C to 85°C
8735BKI-21LFT
735BI21L
32 Lead VFQFN, Lead-Free
Tape & Reel
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION 1 1/27/15
17
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY
CLOCK GENERATOR
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