873995AYLFT

873995 Differential-to-3.3V LVPECL Zero Delay/Multiplier/Divider DATA SHEET GENERAL DESCRIPTION FEATURES The 873995 is a Zero Delay/Multiplier/Divider with hitless input clock switching capability and a member of the family of low jitter/phase noise devices from IDT. The 873995 is ideal for use in redundant, fault tolerant clock trees where low phase noise and low jitter are critical. The device receives two differential LVPECL clock signals from which it generates 6 LVPECL clock outputs with “zero” delay. The out-put divider and feedback divider selections also allow for frequency multiplication or division. • Six differential 3.3V LVPECL outputs The 873995 Dynamic Clock Switch (DCS) circuit continuously monitors both input clock signals. Upon detection of a failure (input clock stuck LOW or HIGH for at least 1 period), INP_BAD for that clock will be set HIGH. If that clock is the primary clock, the DCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase disturbance. • External feedback for “zero delay” clock regeneration with configurable frequencies The low jitter characteristics combined with input clock monitoring and automatic switching from bad to good input clocks make the 873995 an ideal choice for mission criti-cal applications that utilize 1G or 10G Ethernet or 1G/4G/10G Fibre Channel. • 3.3V supply voltage • Selectable differential clock inputs • CLKx, nCLKx pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Input clock frequency range: 49MHz to 213.33MHz • Output clock frequency range: 49MHz to 640MHz • VCO range: 490MHz to 640MHz • Output skew: 100ps (maximum) • RMS phase jitter (1.875MHz - 20MHz): 0.77ps (typical) assuming a low phase noise reference clock input • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package • Use replacement part 873996AYLF BLOCK DIAGRAM 873995 REVISION A 8/25/15 PIN ASSIGNMENT 1 ©2015 Integrated Device Technology, Inc. 873995 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 PLL_SEL Input Pullup 2 nMR Input Pullup 3 nINIT Input Pullup 4, 12, 17 VEE Power 5 CLK0 Input Pulldown Non-inverting differential clock input. 6 nCLK0 Input Pullup/ Inverting differential clock input. VCC/2 default when left floating. Pulldown 7 CLK1 Input Pulldown Non-inverting differential clock input. 8 nCLK1 Input Pullup/ Inverting differential clock input. VCC/2 default when left floating. Pulldown 9 EXT_FB Input Pulldown Differential external feedback. 10 nEXT_FB Input 11 SEL_CLK Input 13, 47 VCC Power 14, 15, 16 NB0, NB1, NB2 Input Pullup 18, 19, 20 NA0, NA1, NA2 Input Pullup 21, 28 VCCO_B Power Output supply voltage for B Bank outputs. 22, 23 nQB2, QB2 Output Differential output pair. LVPECL interface levels. 24, 25 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 26, 27 nQB0, QB0 Output Differential output pair. LVPECL interface levels. Selects between the PLL and reference clock as the input to the dividers. When LOW, selects reference clock.When HIGH, selects PLL. LVCMOS / LVTTL interface levels. Active LOW Master Reset. When logic LOW, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic HIGH, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. When HIGH-to-LOW, resets the input bad flags and aligns CLK_INDICATOR to SEL_CLK. LVCMOS / LVTTL interface levels. Negative supply pins. Pullup/ Differential external feedback. VCC/2 default when left floating. Pulldown Selects the primary reference clock. When LOW, selects CLK0 as the Pulldown primary clock source. When HIGH, selects CLK1 as the primary clock source. LVCMOS / LVTTL interface levels. Core supply pins. Bank B output divider control pins. LVCMOS / LVTTL interface levels. Bank A output divider control pins. LVCMOS / LVTTL interface levels. 29, 36 VCCO_A Power Output supply voltage for A Bank outputs. 30, 31 nQA2, QA2 Output Differential output pair. LVPECL interface levels. 32, 33 nQA1, QA1 Output Differential output pair. LVPECL interface levels. 34, 35 nQA0, QA0 Output Differential output pair. LVPECL interface levels. 37 VCCO_FB Power Output supply voltage for FB outputs. 38, 39 QFB, nQFB Output Feedback outputs. LVPECL interface levels. 40 VCCA Power Analog supply pin. 41, 42, 43 NFB0, NFB1, NFB2 Input 44 CLK_INDICATOR Output 45 INP0BAD Output Pullup Feedback divider control pins. LVCMOS / LVTTL interface levels. Clock indicator pin. When LOW, CLK0, nCLK0 is selected, when HIGH, CLK1, nCLK1 is selected. LVCMOS / LVTTL interface levels. Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is active HIGH. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. REVISION A 8/25/15 2 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET TABLE 1. PIN DESCRIPTIONS, CONTINUED Number Name Type 46 INP1BAD Output 48 MAN_OVERRIDE Input Description Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is active HIGH. LVCMOS / LVTTL interface levels. Manual override. When HIGH, disables internal clock switch circuitry Pulldown and CLK_INDICATOR will track SEL_CLK. When LOW, Dynamic Clock Switch is enabled. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical Maximum 4 Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. FEEDBACK DIVIDER FUNCTION TABLE NFB[2:0] Feedback Divider Value Output Frequency Range 000 1 N/ANOTE1 001 2 N/ANOTE1 010 3 163.33MHz - 200MHz 011 4 122.5MHz - 160MHz 100 5 98MHz - 128MHz 101 6 81.66MHz - 106.66MHz 110 8 61.25MHz - 80MHz 111 10 49MHz - 64MHz NOTE 1: The Phase Detector has a maximum frequency limit of 200MHz, so these values cannot be used for feedback. The reason these options are available is for applications that use an output on Bank A or Bank B for feedback and the QFB/ nQFB pair for a high frequency output. For example, a user may need two 62.5MHz outputs, three 125MHz outputs and one 625MHz output from a 62.5MHz reference clock. For this case, the user would use one of the Bank A Outputs for feedback and set the bank for /10, and use the other two Bank A Outputs to drive the 2 loads. The Bank B Output Divider would be set for /5, and the Feedback Divider would be set for /1. TABLE 3B. NA/NB BANK DIVIDER FUNCTION TABLE NA[2:0], NB[2:0] Bank A/B Divider Value Output Frequency Range 000 1 490MHz - 640MHz 001 2 245MHz - 320MHz 010 3 163.33MHz - 213.33MHz 011 4 122.5MHz - 160MHz 100 5 98MHz - 128MHz 101 6 81.66MHz - 106.66MHz 110 8 61.25MHz - 80MHz 111 10 49MHz - 64MHz REVISION A 8/25/15 3 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 31.8°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = VCCO_FB = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum VCC Core Supply Voltage VCCA Analog Supply Voltage VCCO_A, _B, _FB Output Supply Voltage 3.135 IEE ICCA Units 3.135 3.3 3.465 V VCC – 0.15 3.3 VCC V 3.3 3.465 V Power Supply Current 300 mA Analog Supply Current 15 mA Maximum Units TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical LVCMOS Inputs 2 VCC + 0.3 V LVCMOS Inputs -0.3 0.8 V VIN = VCC = 3.465V 5 µA VIN = VCC = 3.465V 150 µA NA[2:0], NB[2:0], NFB[2:0], PLL_SEL, nINIT, nMR SEL_CLK, MAN_OVERRIDE NA[2:0], NB[2:0], NFB[2:0], PLL_SEL, nINIT, nMR SEL_CLK, MAN_OVERRIDE VIN = 0V, VCC = 3.465V -150 µA VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = VCCO_FB = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions CLK0, CLK1, EXT_ FB nCLK0, nCLK1, nEXT_FB CLK0, CLK1, EXT_ FB nCLK0, nCLK1, nEXT_FB VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units VIN = VCC = 3.465V 150 µA VIN = VCC = 3.465V 150 µA VIN = 0V, VCC = 3.465V -5 µA VIN = 0V, VCC = 3.465V -150 µA 0.15 1.3 V VEE + 0.5 VCC - 0.85 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLKx, nCLKx is VCC + 0.3V. REVISION A 8/25/15 4 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = VCCO_FB = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions VCCO_X - 1.4 Minimum Typical VCCO_X - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO_X - 2.0 VCCO_X - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO_A, _B, _FB = - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = VCCO_FB = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fVCO PLL VCO Lock Range t(Ø) Static Phase Offset; NOTE 2 tjit(ø) RMS Phase Jitter (Random); NOTE 7 tsk(o) Output Skew; NOTE 3 100 ps tsk(b) Bank Skew; NOTE 4 80 ps ΔPER/CYCLE odc tR / tF Rate of change of Periods Test Conditions 62.5MHz Output; NOTE 1, 5 125MHz Output; NOTE 1, 5 62.5MHz Output; NOTE 1, 6 125MHz Output; NOTE 1, 6 Output Duty Cycle Output Rise/Fall Time Minimum Typical 490 PLL_SEL = HIGH Tested at typical conditions Maximum Units 640 MHz 60 ps 0.77 ps 30 ps/cycle 60 ps/cycle 45 ps/cycle 90 ps/cycle M>2 47 53 % M=2 45 55 % M=1 40 60 % 20% to 80% 250 600 ps All parameters measured at fMAX unless noted otherwise. NOTE 1: These parameters are guaranteed by characterization. Not tested in production. NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal, when the PLL is locked and the input reference frequency is stable. NOTE 3: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5: Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. NOTE 6: Specification holds for a clock switch between two signals greater than 400ps out of phase. Delta period change per cycle is averaged over the clock switch excursion. NOTE 7: Please refer to the Phase Noise Plot. REVISION A 8/25/15 5 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET ➤ TYPICAL PHASE NOISE AT 62.5MHZ 62.5MHz NOISE POWER dBc Hz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.77ps Gb Ethernet Filter Raw Phase Noise Data ➤ ➤ Phase Noise Result by adding a Gb Ethernet Filter to raw data OFFSET FREQUENCY (HZ) REVISION A 8/25/15 6 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW BANK SKEW RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD STATIC PHASE OFFSET OUTPUT RISE/FALL TIME REVISION A 8/25/15 7 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET APPLICATIONS INFORMATION CLOCK REDUNDANCY AND REFERENCE SELECTION status of the secondary clock. If the secondary clock is detected as a good input clock, the 873995 will automatically deselect the initial clock as the reference and multiplex in the secondary clock. When a successful switch from the initial to secondary clock has been accomplished, CLK_INDICATOR will be updated to indicate the new reference. If and when the fault on the initial clock is corrected, the corresponding input bad flag will be updated to represent this clock as good again. However, the DCS will not undergo an unneccessary clock switch as long as the secondary clock remains good. If, at a later time, a fail-ure occurs on the secondary clock, the 873995 will then switch to the initial clock if it is detected as good. See the Dynamic Clock Switch State Diagram (page 9) and for additional details on the functionality of the Dynamic Clock Switching circuit. The 873995 accepts two differential input clocks, CLK0/nCLK0 and CLK1/nCLK1, for the purpose of redundancy. Only one of these clocks can be selected at any given time for use as the reference. One clock will be defined during the initialization process as the initial, or primary clock, while the remaining clock is the redundant or secondary clock. During the initialization process, input signal SEL_CLK determines which input clock will be used as the initial clock. When SEL_CLK is driven HIGH, the initial clock to be used as the reference is CLK1/nCLK1, otherwise an internal pulldown pulls this input LOW so that the initial clock input is CLK0/nCLK0. The output signal CLK_INDICATOR indicates which clock input is being used as the reference (LOW = CLK0/nCLK0, HIGH = CLK1/nCLK1), and will initially be at the same level as SEL_CLK. OUTPUT TRANSITIONING INITIALIZATION EVENT After a successful manual or DCS initiated clock switch, the internal PLL of the 873995 will begin slewing to phase/ frequency alignment. The PLL will achieve lock to the new input with minimal phase disturbance at the outputs. An initialization event is required to specify the initial input clock. In order to run an initialization event, nINIT must transition from HIGH-to-LOW. Following a HIGH-to-LOW transition of nINIT, the input clock specified on the SEL_CLK input will be set as the initial input clock. In addition, both input-bad flags (INP0BAD and INP1BAD outputs) will be cleared. MASTER RESET OPERATION When the input signal is driven LOW, the internal dividers of the 873995 are reset causing the true outputs, Qx, to go LOW and the inverted outputs, nQx, to go HIGH. With no signal driving nMR, an internal pullup pulls nMR HIGH and the output clocks and internal dividers are enabled. FAILURE DETECTION AND ALARM SIGNALING Within the 873995 device, CLK0/nCLK0 and CLK1/nCLK1 are continuously monitored for failures. A failure on either of these clocks is detected when one of the clock signals is stuck HIGH or LOW for at least 1 period of the Feedback. Upon detection of a failure, the corresponding input-bad signal, INP0BAD or INP1BAD, will be set HIGH. The input clocks are continuously monitored and the input-bad signals will continue to reflect the real-time status of each input clock. RECOMMENDED POWER-UP SEQUENCE 1. 2. MANUAL CLOCK SWITCHING When input signal MAN_OVERRIDE is driven HIGH, the clock specified by SEL_CLK will always be used as the reference, even when a clock failure is detected at the reference. In order to switch between CLK0/nCLK0 and CLK1/nCLK1 as the reference clock, the level on SEL_CLK must be driven to the appropriate level. When the level on SEL_CLK is changed, the selection of the new clock will take place, and CLK_INDICATOR will be updated to indicate which clock is now supplying the reference to the PLL. 3. 4. ALTERNATE POWER-UP SEQUENCE If both input clocks are valid before power up, the part may be powered-up in DCS mode. However, it cannot be guaranteed that the PLL will achieve lock with one specific input clock. DYNAMIC CLOCK SWITCHING 1. The Dynamic Clock Switching (DCS) process serves as an automatic safety mechanism to protect the stability of the PLL when a failure occurs on the reference. 2. When input signal MAN_OVERRIDE is not driven HIGH, an internal pulldown pulls it LOW so that DCS is enabled. If DCS is enabled and a failure occurs on the initial clock, the 873995 device will check the REVISION A 8/25/15 Before startup, set MAN_OVERRIDE HIGH and set SEL_CLK to the desired input clock. This will ensure that, during startup, the PLL will acquire lock using the input clock specified by SEL_CLK. Once powered-up, and assuming a stable clock free of failures is present at the clock designated by SEL_CLK, the PLL will begin to phase/frequency slew as it attempts to achieve lock with the input reference clock. Drive MAN_OVERRIDE LOW to enable DCS mode. Transition nINIT from HIGH-to-LOW in order to clear both input-bad flags and to set the initial input clock. 3. 8 Before startup, leave MAN_OVERRIDE floating and the internal pulldown will enable DCS mode. Once powered up, the PLL will begin to phase/frequency slew as it attempts to achieve lock with one of the input reference clocks. Transition nINIT from HIGH-to-LOW in order to clear both input-bad flags and to set the initial input clock. DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 STATE DIAGRAM 873995 DATA SHEET REVISION A 8/25/15 9 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 873995 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT REVISION A 8/25/15 10 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET DIFFERENTIAL CLOCK INPUT INTERFACE The CLKx /nCLKx accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V 3.3V 3.3V 3.3V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 LVPECL HiPerClockS Input R1 50 R2 50 3.3V Zo = 50 Ohm R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY IDT HIPERCLOCKS LVHSTL DRIVER 3.3V HiPerClockS Input R3 125 FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R4 125 Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Zo = 50 Ohm nCLK Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. REVISION A 8/25/15 11 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission FIGURE 4A. LVPECL OUTPUT TERMINATION REVISION A 8/25/15 FIGURE 4B. LVPECL OUTPUT TERMINATION 12 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/ shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application SOLDER PIN PIN PAD EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER PIN LAND PATTERN (GROUND PAD) FIGURE 5. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE REVISION A 8/25/15 13 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER SOLDER PIN PAD 873995 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 873995. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 873995 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 300mA = 1039.5mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30mW = 180mW Total Power_MAX (3.465V, with all outputs switching) = 1039.5mW + 180mW = 1219.56mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 25.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 1.220W * 25.8°C/W = 101.5°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 48-PIN TQFP, E-PAD FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards REVISION A 8/25/15 31.8°C/W 14 1 2 25.8°C/W 24.2°C/W DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO- 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX - VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - (VCCO_MAX - VOH_MAX))/RL] * (VCCO_MAX - VOH_MAX) = [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX - 2V))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - (VCCO_MAX - VOL_MAX))/RL] * (VCCO_MAX - VOL_MAX) = [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW REVISION A 8/25/15 15 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 48 LEAD TQFP, E-PAD θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 31.8°C/W 1 2 25.8°C/W 24.2°C/W TRANSISTOR COUNT The transistor count for 873995 is: 5969 REVISION A 8/25/15 16 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD TQFP, E-PAD TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL ABC - HD MINIMUM NOMINAL N MAXIMUM 48 A -- -- 1.20 A1 0.05 -- 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 4.00 BASIC E 9.00 BASIC E1 7.00 BASIC E2 4.00 BASIC e 0.5 BASIC L 0.45 θ 0° ccc -- D3 & E3 2.0 0.60 0.75 7° -- 0.08 7.0 Reference Document: JEDEC Publication 95, MS-026 REVISION A 8/25/15 17 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 873995AYLF ICS873995AYL 873995AYLFT ICS873995AYL 48 Lead “Lead-Free” TQFP, E-Pad tray 0°C to 70°C 48 Lead “Lead-Free” TQFP, E-Pad tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION A 8/25/15 18 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER 873995 DATA SHEET REVISION HISTORY SHEET Rev Table A A REVISION A 8/25/15 Page 1 13 Description of Change Date Pin Assignment - Fixed Pin Numbering Alignment. Updated Thermal Release Path section. 9/11/08 Product Discontinuation Notice - Last time buy expires August 14, 2016 PDN CQ-15-04 Updated data sheet format. 8/25/15 19 DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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