874002AGLFT

874002 PCI Express/Jitter Attenuator DATA SHEET GENERAL DESCRIPTION FEATURES The 874002 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874002 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the 874002 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pin. • Two differential LVDS output pair • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • 3.3V operating supply • Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature • Available in lead-free (RoHS 6) package PLL BANDWIDTH (TYPICAL) BW_SEL 0 = PLL Bandwidth: 200kHz Float = PLL Bandwidth: 400kHz (Default) 1 = PLL Bandwidth: 800kHz T h e 8 7 4 0 0 2 u s e s I D T ’s 3 r d G e n e ra t i o n Fe m t o C l o ck T M PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. BLOCK DIAGRAM OE PIN ASSIGNMENT Pullup F_SEL Pulldown BW_SEL Float 0 = 200kHz Float = 400kHz 1 = 800kHz CLK Pulldown nCLK Pullup Output Divider 0 ÷5 (default) 1 ÷4 Phase Detector QA0 nQA0 VCO 490 - 640 MHz QA1 874002 20-Lead TSSOP nQA1 FB_IN Pulldown nFB_IN Pullup ÷5 (fixed) 6.5mm x 4.4mm x 0.92mm package body G Package Top View FB_OUT nFB_OUT MR Pulldown 874002 REVISION A 7/16/15 1 ©2015 Integrated Device Technology, Inc. 874002 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type 1, 20 nQA0, QA0 Output Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 FB_OUT, nFB_OUT Output Differential feedback output pair. LVDS interface levels. 5 MR Input 6 BW_SEL Input 7 nc Unused 8 VDDA Power 9 F_SEL Input 10 VDD Power 11 OE Input 12 CLK Input 13 nCLK Input 14 GND Power 15 FB_IN Input 16 nFB_IN Input 17, 18 nQA1, QA1 Output Description Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx, FB_OUT) to go low and the inverted Pulldown outputs (nQx, nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ PLL Bandwidth select input. 0 = 200kHz, Float = 400kHz, 1 = 800kHz. Pulldown See Table 3B. No connect. Analog supply pin. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C. Core supply pin. Pullup Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A. Pulldown Non-inverting differential clock input. Pullup Inverting differential clock input. Power supply ground. Pulldown Non-inverting differential feedback input. Pullup Inverting differential feedback input. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Input Minimum Typical Maximum Units TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Outputs Input OE QAx/nQAx FB_OUT/nFB_OUT BW_SEL PLL Bandwidth (Typical) 0 1 HiZ Enabled Enabled Enabled 0 200kHz 1 800kHz Float 400kHz TABLE 3C. FREQUENCY SELECT FUNCTION TABLE Input F_SEL 0 (default) 1 Outputs QA[0:1]/nQA[0:1] FB_OUT/nFB_OUT ÷5 ÷5 ÷4 PCI EXPRESS/JITTER ATTENUATOR ÷5 2 REVISION A 7/16/15 874002 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD - 0.12 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 110 mA Maximum Units VDD + 0.3 V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage VIM Input Mid Voltage BW_SEL IIH Input High Current OE BW_SEL, F_SEL, MR IIL Input Low Current F_SEL, OE, MR Minimum Typical 2 BW_SEL VDD - 0.4 F_SEL, OE, MR V -0.3 BW_SEL VDD/2 - 0.1 0.8 V VDD + 0.4 V VDD/2 +0.1 V VDD = VIN = 3.465V 5 µA VDD = VIN = 3.465V 150 µA OE, BW_SEL VDD = 3.465V, VIN = 0V -150 µA F_SEL, MR VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 CLK, FB_IN VDD = VIN = 3.465V nCLK, nFB_IN VDD = VIN = 3.465V CLK, FB_IN VDD = VIN = 3.465V nCLK, nFB_IN VDD = VIN = 3.465V Minimum Typical Maximum 150 5 3 µA µA 150 -150 µA µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V. REVISION A 7/16/15 Units PCI EXPRESS/JITTER ATTENUATOR 874002 DATA SHEET TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 250 370 485 mV 50 mV 1.0 1.30 1.60 V 50 mV Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical fMAX Output Frequency 160 MHz tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 35 ps tsk(o) Output Skew; NOTE 2, 3 40 ps tsk(Ø) Static Phase Offset; NOTE 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle 98 -150 20% to 80% 110 ps 300 -20 700 ps 48 52 % NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. PCI EXPRESS/JITTER ATTENUATOR 4 REVISION A 7/16/15 874002 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL OUTPUT SKEW CYCLE-TO-CYCLE JITTER t(Ø) mean = Static Phase Offset (where t(Ø) is any random sample, and t(Ø) mean is the average of the sampled cycles measured on controlled edges) OUTPUT RISE/FALL TIME REVISION A 7/16/15 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 5 PCI EXPRESS/JITTER ATTENUATOR 874002 DATA SHEET OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP DIFFERENTIAL OUTPUT VOLTAGE SETUP PCI EXPRESS/JITTER ATTENUATOR 6 REVISION A 7/16/15 874002 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The 874002 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to a c c e p t s i n g l e e n d e d l eve l s . T h e r e fe r e n c e vo l t a g e V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT REVISION A 7/16/15 7 PCI EXPRESS/JITTER ATTENUATOR 874002 DATA SHEET DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V 3.3V 3.3V 3.3V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 LVPECL HiPerClockS Input R1 50 R2 50 3.3V Zo = 50 Ohm R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY IDT HIPERCLOCKS LVHSTL DRIVER 3.3V HiPerClockS Input R3 125 FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R4 125 Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Zo = 50 Ohm nCLK Receiv er R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. PCI EXPRESS/JITTER ATTENUATOR 8 REVISION A 7/16/15 874002 DATA SHEET 3.3V LVDS DRIVER TERMINATION the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION REVISION A 7/16/15 9 PCI EXPRESS/JITTER ATTENUATOR 874002 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 874002. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 874002 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 12mA) = 318.78mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 110mA = 381.15mW Total Power_MAX = 318.78mW + 381.15mW = 699.93mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.700W * 66.6°C/W = 116.6°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. PCI EXPRESS/JITTER ATTENUATOR 10 REVISION A 7/16/15 874002 DATA SHEET RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 874002 is: 1216 REVISION A 7/16/15 11 PCI EXPRESS/JITTER ATTENUATOR 874002 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 PCI EXPRESS/JITTER ATTENUATOR 12 REVISION A 7/16/15 874002 DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 874002AGLF ICS874002AGL 20 Lead “Lead-Free” TSSOP tube 0°C to 70°C 874002AGLFT ICS874002AGL 20 Lead “Lead-Free” TSSOP tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION A 7/16/15 13 PCI EXPRESS/JITTER ATTENUATOR 874002 DATA SHEET REVISION HISTORY SHEET Rev Table A T3C 2 Added T3C F_SEL Function Table. 12/06/06 T9 13 Ordering Information - removed leaded devices. Updated data sheet format. 7/16/15 A Page PCI EXPRESS/JITTER ATTENUATOR Description of Change 14 Date REVISION A 7/16/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. 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