874003AG-02LF

PCI EXPRESS™ Jitter Attenuator ICS874003-02 DATA SHEET General Description Features The ICS874003-02 is a high performance Differential-to- LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003-02 has a bandwidth of 400kHz which is designed to provide good jitter attenuation. • • • Three differential LVDS output pairs • • • • • Input frequency range: 98MHz to 128MHz • • • Full 3.3V supply mode RD ® The ICS874003-02 uses IDT’s 3 Generation Femtoclock PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. One differential clock input CLK, nCLK supports the following input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Output frequency range: 98MHz to 320MHz VCO range: 490MHz - 640MHz Cycle-to-cycle jitter: 35ps (maximum) For PCI Express Spread Spectrum Clocking support use the ICS874003-05 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment F_SEL[2:0] Function Table Inputs Outputs F_SEL2 F_SEL1 F_SEL0 QA[0:1], nQA[0:1] QB0, nQB0 0 0 0 ÷2 ÷2 1 0 0 ÷5 ÷2 0 1 0 ÷4 ÷2 1 1 0 ÷2 ÷4 0 0 1 ÷2 ÷5 1 0 1 ÷5 ÷4 0 1 1 ÷4 ÷5 1 1 1 ÷4 ÷4 ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 1 QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Block Diagram OEA Pullup F_SEL2:0 Pulldown 3 QA0 ÷5 ÷4 ÷2 (default) nQA0 QA1 CLK Pulldown nCLK Pullup Phase Detector VCO 490 - 640MHz nQA1 3 ÷5 ÷4 ÷2 (default) M = ÷5 (fixed) QB0 nQB0 MR Pulldown OEB Pullup ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 2 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 1. Pin Descriptions Number Name 1, 20 QA1, nQA1 Output Type Description Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output Differential output pair. LVDS interface levels. 5 MR Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Input Pulldown Frequency select pin for QAx, nQAx and QB0, nQB0 outputs. LVCMOS/LVTTL interface levels. 7 nc Unused No connect. 8 VDDA Power Analog supply pin. 10 VDD Power Core supply pin. 11 OEA Input Pullup 12 CLK Input Pulldown 13 nCLK Input Pullup 14 GND Power 15 OEB Input 17, 18 nQB0, QB0 Output Output enable pin for QA pins. When HIGH, the QAx, nQAx outputs are active. When LOW, the QAx, nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Non-inverting differential clock input. Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0, nQB0 outputs are active. When LOW, the QB0, nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ Function Table Table 3. Output Enable Function Table Inputs Outputs OEA OEB QA[0:1], nQA[0:1] QB0, nQB0 0 0 Hi-Impedance Hi-Impedance 1 1 Enabled Enabled ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 3 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuos Current Surge Current 10mA 15mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. LVDS Power Supply DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VDD Core Supply Voltage VDDA Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V Analog Supply Voltage VDD – 0.12 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 75 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 75 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V OEA, OEB VDD = VIN = 3.465V 5 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = VIN = 3.465V 150 µA OEA, OEB VDD = 3.465V, VIN = 0V -150 µA F_SEL0, F_SEL1, F_SEL2, MR VDD = 3.465V, VIN = 0V -5 µA ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 4 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Table 4C. Differential DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units CLK VDD = VIN = 3.465V 150 µA nCLK VDD = VIN = 3.465V 5 µA CLK VDD = 3.465V, VIN = 0V -5 µA nCLK VDD = 3.465V, VIN = 0V -150 µA 0.15 1.3 V GND + 0.5 VDD – 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. Table 4D. LVDS DC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter VOD Differential Output Voltage ∆VOD VOD Magnitude Change VOS Offset Voltage ∆VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.5 V 50 mV 1.2 1.35 Table 5. AC Characteristics, VDD = VDDA = VDDO = 3.3V ± 5%, TA = 0°C to 70°C Symbol Parameter fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tsk(b) Bank Skew; NOTE 1, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Maximum Units 320 MHz 35 ps 145 ps 55 ps 275 725 ps 47 53 % 98 Bank A 20% to 80% Typical NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions. ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 5 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information VDD SCOPE 3.3V±5% POWER SUPPLY + Float GND – VDD, nCLK Qx V V Cross Points PP VDDO CMR CLK VDDA nQx GND 3.3V LVDS Output Load AC Test Circuit Differential Input Level nQA[0:1], nQB0 nQA0 QA0 QA[0:1], QB0 ➤ ➤ nQA1 ➤ tcycle n tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles QA1 tsk(b) Bank Skew Cycle-to-Cycle Jitter nQx nQA[0:1], nQB0 Qx QA[0:1], QB0 t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Skew ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 6 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Parameter Measurement Information, continued VDD nQA[0:1], nQB0 out 80% VOD QA[0:1], QB0 DC Input LVDS ➤ 80% 20% 20% tR tF out ➤ VOS/∆ VOS ➤ Output Rise/Fall Time Offset Voltage Setup VDD LVDS 100 ➤ VOD/∆ VOD out ➤ DC Input ➤ out Differential Output Voltage Setup ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 7 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Applications Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS874003-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA Figure 1. Power Supply Filtering Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 8 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. The differential signal must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω Differential Input LVHSTL R1 50Ω IDT LVHSTL Driver Differential Input LVPECL nCLK R2 50Ω R2 50Ω R1 50Ω R2 50Ω Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3A.CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver 3.3V 3.3V 3.3V R3 125Ω 3.3V 3.3V R4 125Ω Zo = 50Ω Zo = 50Ω CLK CLK R1 100Ω Zo = 50Ω nCLK R1 84Ω R2 84Ω Receiver LVDS Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V nCLK Zo = 50Ω Differential Input LVPECL Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 2.5V *R3 33Ω R3 120Ω Zo = 50Ω R4 120Ω Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK nCLK HCSL *R4 33Ω R1 50Ω R2 50Ω Differential Input SSTL R1 120Ω R2 120Ω Differential Input *Optional – R3 and R4 can be 0Ω Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 9 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins LVDS Outputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVDS Driver Termination A general LVDS interface is shown in Figure 4. Standard termination for LVDS type output structure requires both a 100Ω parallel resistor at the receiver and a 100Ω differential transmission line environment. In order to avoid any transmission line reflection issues, the 100Ω resistor must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 4 can be used with either type of output structure. If using a non-standard termination, it is recommended to contact IDT and confirm if the output is a current source or a voltage source type structure. In addition, since these outputs are LVDS compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. + LVDS Driver LVDS Receiver 100Ω – 100Ω Differential Transmission Line Figure 4. Typical LVDS Driver Termination ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 10 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Power Considerations This section provides information on power dissipation and junction temperature for the ICS874003-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS74003-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 12mA) = 301.45mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.87mW Total Power_MAX = 301.45mW + 259.87mW = 561.32mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.561W * 66.6°C/W = 107.3°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection θJA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 11 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Reliability Information Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP θJA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS874003-02 is: 1408 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 12 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Ordering Information Table 9. Ordering Information Part/Order Number 874003AG-02 874003AG-02T 874003AG-02LF 874003AG-02LFT Marking ICS874003A02 ICS874003A02 ICS74003A02L ICS74003A02L Package 20 Lead TSSOP 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 13 ©2010 Integrated Device Technology, Inc. ICS874003-02 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR Revision History Sheet Rev B Table Page T1 T4C T5 1 3 5 5 5 6-7 8 9 10 13 Description of Change Date Updated General Description and Features section. Pin Description Table - corrected MR description Differential DC Characteristics Table - updated notes. Added Units to IIH/IIL rows. Corrected IIH (nCLK) spec from 5uA min to 5uA max. Corrected IIL CLK from 150uA max to -5uA min. AC Characteristics Table - added thermal note, corrected NOTE 2. Parameter Measurement Information - corrected Bank Skew labels, corrected Output Rise/Fall Time diagram. Updated Wiring the Differential Input to Accept Single-ended Levels. Updated Differential Clock Input Interface. Updated LVDS Driver Termination. Ordering Information Table - deleted "ICS" prefix in Part/Order column, added "ICS" prefix to marking column. Converted datasheet format. ICS874003AG-02 REVISION B SEPTEMBER 14, 2010 14 9/14/10 ©2010 Integrated Device Technology, Inc. ICS874003-04 Data Sheet PCI EXPRESS™ JITTER ATTENUATOR We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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