874003AGLFT

PCI EXPRESS™ JITTER ATTENUATOR ICS874003I-02 GENERAL DESCRIPTION FEATURES The ICS874003I-02 is a high performance Dif-ferential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS874003I02 has a bandwidth of 400kHz. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. • Three Differential LVDS output pairs • One Differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 320MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 35ps (maximum) • Supports PCI-Express Spread-Spectrum Clocking The ICS874003I-02 uses IDT’s 3rd Generation FemtoClockTM PLL technology to achive the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. • The 400kHz bandwidth mode allows the system designer to make jitter attenuation/tracking skew design trade-offs • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Lead-free (RoHS 6) packaging F_SEL[2:0] FUNCTION TABLE F_SEL2 0 Inputs F_SEL1 0 F_SEL0 0 1 0 0 ÷5 ÷2 0 1 0 ÷4 ÷2 ÷4 BLOCK DIAGRAM OEA Outputs QA0, nQA0:QA1, nQA1 ÷2 1 1 0 ÷2 0 0 1 ÷2 ÷5 1 0 1 ÷5 ÷4 0 1 1 ÷4 ÷5 1 1 1 ÷4 ÷4 Pullup F_SEL2:0 Pulldown PIN ASSIGNMENT 3 QA0 ÷5 ÷4 ÷2 (default) nQA0 QA1 CLK Pulldown nCLK Pullup Phase Detector VCO nQA1 490 - 640MHz M = ÷5 (fixed) 3 ÷5 ÷4 ÷2 (default) Pullup IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR QB0 QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003I-02 20-Lead TSSOP nQB0 6.5mm x 4.4mm x 0.92mm package body G Package Top View MR Pulldown OEB QB0, nQB0 ÷2 1 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 20 QA1, nQA1 Output Type Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output 5 MR Input 6, 9, 16 7 F_SEL0, F_SEL1, F_SEL2 nc Unused 8 VDDA Power 10 VDD Power 11 OEA Input Input 12 CLK Input 13 nCLK Input 14 GND Power 15 OEB Input 17, 18 nQB0, QB0 Output Description Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Frequency select pin for QAx/nQAx and QBx0/nQB0 outputs. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance Pullup state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pullup Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are active. When LOW, the QBx/nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3. OUTPUT ENABLE FUNCTION TABLE Inputs Outputs OEA OEB QA0/nQA0, QA1/nQA1 QB0/nQB0 0 0 HiZ HiZ 1 1 Enabled Enabled IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 2 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum VDD Core Supply Voltage VDDA Analog Supply Voltage VDDO Output Supply Voltage 3.135 IDD Power Supply Current Units 3.135 3.3 3.465 V VDD – 0.12 3.3 VDD V 3.3 3.465 V 75 mA IDDA Analog Supply Current 12 mA IDDO Output Supply Current 75 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VDD = VIN = 3.465V 5 µA IIH Input High Current VDD = VIN = 3.465V 150 µA IIL Input Low Current OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR Minimum Typical VDD = 3.465V, VIN = 0V -150 µA VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol IIH Parameter Input High Current Test Conditions CLK nCLK VDD = VIN = 3.465V CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V IIL Input Low Current VPP Peak-to-Peak Input Voltage Minimum VDD = VIN = 3.465V Typical Maximum Units 15 0 µA 15 0 µA 1.3 V 5 -150 0.15 Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VDD - 0.85 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK and FB_IN, nFB_IN is VDD + 0.3V. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 3 V ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.2 1.35 1.5 V 50 mV Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical fMAX Output Frequency 320 MHz tjit(cc) Cycle-to-Cycle Jitter, NOTE 1 35 ps tsk(o) Output Skew; NOTE 2, 3 145 ps tsk(b) Bank Skew; NOTE 1, 4 tR / tF Output Rise/Fall Time 98 Bank A 20% to 80% 275 odc Output Duty Cycle 47 NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 4 55 ps 725 ps 53 % ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR PARAMETER MEASUREMENT INFORMATION VDD SCOPE VDD, VDDO 3.3V±5% POWER SUPPLY + Float GND – nCLK Qx VDDA V V Cross Points PP LVDS CMR CLK nQx GND 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQA0, nQA1, nQB0 nQx Qx QA0, QA1, QB0 ➤ ➤ ➤ tcycle n tcycle n+1 ➤ nQy t jit(cc) = tcycle n –tcycle n+1 Qy 1000 Cycles tsk(o) CYCLE-TO-CYCLE JITTER OUTPUT SKEW nQXx QXx nQA0, nQA1, nQB0 nQXy QA0, QA1, QB0 QXy t PW t tsk(b) Where X = A or B odc = PERIOD t PW x 100% t PERIOD BANK SKEW IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 5 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR VDD out 80% VSW I N G Clock Outputs DC Input LVDS ➤ 80% 20% 20% tR tF out ➤ VOS/Δ VOS ➤ OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP VDD LVDS 100 ➤ VOD/Δ VOD out ➤ DC Input ➤ out DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 6 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR APPLICATION INFORMATION POWER SUPPLY F ILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS874003I-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a 0.01μF bypass capacitor should be connected to each VCCA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 7 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50Ω Zo = 50Ω CLK CLK Zo = 50Ω nCLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Differential Input LVPECL R1 50Ω R2 50Ω R2 50Ω FIGURE 3A. CLK/NCLK INPUT DRIVEN BY ICS LVHSTL DRIVER FIGURE 3B. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V Zo = 50Ω CLK CLK R1 100Ω nCLK Zo = 50Ω Differential Input LVPECL RECOMMENDATIONS FOR UNUSED INPUT INPUTS: Receiver LVDS FIGURE 3C. CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER nCLK FIGURE 3D. CLK/NCLK INPUT DRIVEN BY 3.3V LVDS DRIVER AND OUTPUT PINS OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR LVDS All unused LVDS output pairs can be either left floating or ter minated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 8 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR LVDS DRIVER TERMINATION receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to ter minate the unused outputs. A general LVDS inteface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 9 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS874003I-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS874003I-02 is the sum of the core power plus the power dissipated due to the load. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (75mA + 12mA) = 301.45mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.87mW Total Power_MAX = 301.45mW + 259.87mW = 561.32mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.561W * 66.6°C/W = 122.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 20-LEAD TSSOP, FORCED CONVECTION θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 10 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θ JA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS874003I-02 is: 1408 IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 11 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 12 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 8. ORDERING INFORMATION Part/Order Number 874003AGI-02LF 874003AGI-02LFT Marking ICS4003AI02L ICS4003AI02L IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR Package 20 lead "Lead Free" TSSOP 20 lead "Lead Free" TSSOP 13 Shipping Packaging Tube Tape and Reel Temperature -40°C to +85°C -40°C to +85°C ICS874003AGI-02 REV A MAY 1, 2013 ICS874003I-02 PCI EXPRESS™ JITTER ATTENUATOR TABLE 9. REVISION HISTORY REV A TABLE Function T PAGE 1 1 8 10 CHANGE Corrected typo 'QA0, nQA0:QA1, nQA1'. Removed HiPerClockS logo. Removed HiPerClockS references from drawings Removed HiPerClockS reference from Power Considerations IDT ™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR 14 DATE 5/1/2013 ICS874003AGI-02 REV A MAY 1, 2013 ICS874003-02 PCI EXPRESS™ JITTER ATTENUATOR IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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