874003DGI-02LFT

874003DI-02 PCI Express™ Jitter Attenuator DATA SHEET PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 • Three differential LVDS output pairs GENERAL DESCRIPTION • One differential clock input The 874003DI-02 is a high performance Dif-ferential-to-LVDS Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874003DI-02 has a bandwidth of 3MHz. The 3MHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 874003DI-02 uses IDT’s 3 rd Generation FemtoClock TM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 20 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 320MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 30ps (maximum) • Supports PCI-Express Spread-Spectrum Clocking • 3MHz PLL loop bandwidth • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package FEATURES F_SEL[2:0] FUNCTION TABLE F_SEL2 0 Inputs F_SEL1 0 Outputs QA0, nQA0:QA1, nQA1 ÷2 (default) F_SEL0 0 1 0 0 ÷5 ÷2 0 1 0 ÷4 ÷2 1 1 0 ÷2 ÷4 0 0 1 ÷2 ÷5 1 0 1 ÷5 ÷4 0 1 1 ÷4 ÷5 1 1 1 ÷4 ÷4 QB0, nQB0 ÷2 (default) BLOCK DIAGRAM PIN ASSIGNMENT QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nQA1 DDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA 874003DI-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View 874003DI-02 REVISION A 7/17/15 1 ©2015 Integrated Device Technology, Inc. 874003DI-02 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name 1, 20 QA1, nQA1 Type Description Output Differential output pair. LVDS interface levels. 2, 19 VDDO Power Output supply pins. 3, 4 QA0, nQA0 Output Differential output pair. LVDS interface levels. 5 MR Input Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (Qx) to go low and the inverted outputs Pulldown (nQx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. 6, 9, 16 F_SEL0, F_SEL1, F_SEL2 Input Pulldown 7 nc Unused 8 VDDA Power 10 VDD Power Core supply pin. Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx/nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. 11 OEA Input 12 CLK Input 13 nCLK Input 14 GND Power 15 OEB Input 17, 18 nQB0, QB0 Output Frequency select pin for QAx/nQAx and QB0/nQB0 outputs. LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pullup Pulldown Non-inverting differential clock input. Pullup Inverting differential clock input. Power supply ground. Pullup Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are active. When LOW, the QB0/nQB0 outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. OEA OUTPUT ENABLE FUNCTION TABLE Minimum Typical Units TABLE 3B. OEB OUTPUT ENABLE FUNCTION TABLE Inputs Outputs Inputs Outputs OEA QA0/nQA0, QA1/nQA1 OEB QB0/nQB0 0 High Impedance 0 High Impedance 1 Enabled 1 Enabled PCI EXPRESS™ JITTER ATTENUATOR Maximum 2 REVISION A 7/17/15 874003DI-02 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VDDA Analog Supply Voltage VDD – 0.15 3.3 VDD V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 75 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions 2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VDD = VIN = 3.465V 5 µA IIH Input High Current VDD = VIN = 3.465V 150 µA IIL Input Low Current OEA, OEB F_SEL0, F_SEL1 F_SEL2, MR Minimum Typical OEA, OEB VDD = 3.465V, VIN = 0V -150 µA F_SEL0, F_SEL1 F_SEL2, MR VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current Test Conditions CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical Maximum Units 150 µA 5 µA 150 -150 µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. REVISION A 7/17/15 3 µA PCI EXPRESS™ JITTER ATTENUATOR 874003DI-02 DATA SHEET TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.2 1.35 1.5 V 50 mV Maximum Units TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical fMAX Output Frequency 320 MHz tjit(cc) Cycle-to-Cycle Jitter, NOTE 1, 3 30 ps tsk(o) Output Skew; NOTE 2 185 ps tsk(b) Bank Skew; NOTE 1, 4 tR / tF Output Rise/Fall Time odc Output Duty Cycle 98 Bank A 20% to 80% 65 ps 250 700 ps 47 53 % TA, Ambient Temperature applied using forced air flow. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 4: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. PCI EXPRESS™ JITTER ATTENUATOR 4 REVISION A 7/17/15 874003DI-02 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL CYCLE-TO-CYCLE JITTER OUTPUT SKEW BANK SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD REVISION A 7/17/15 5 PCI EXPRESS™ JITTER ATTENUATOR 874003DI-02 DATA SHEET OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP DIFFERENTIAL OUTPUT VOLTAGE SETUP PCI EXPRESS™ JITTER ATTENUATOR 6 REVISION A 7/17/15 874003DI-02 DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 874003DI-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and V DDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/ R1 = 0.609. FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT REVISION A 7/17/15 7 PCI EXPRESS™ JITTER ATTENUATOR 874003DI-02 DATA SHEET DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω FIGURE 3A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER LVHSTL DRIVER FIGURE 3B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 3D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 2.5V 3.3V 3.3V 2.5V R3 120Ω *R3 R4 120Ω Zo = 60Ω CLK CLK Zo = 60Ω nCLK HCSL *R4 nCLK Differential Input SSTL R1 120Ω Differential Input FIGURE 3F. CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER PCI EXPRESS™ JITTER ATTENUATOR R2 120Ω 8 REVISION A 7/17/15 874003DI-02 DATA SHEET RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS LVDS OUTPUTS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. LVDS DRIVER TERMINATION A general LVDS inteface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION REVISION A 7/17/15 9 PCI EXPRESS™ JITTER ATTENUATOR 874003DI-02 DATA SHEET SCHEMATIC EXAMPLE the power pin. The input is driven by a 3.3V LVPECL driver. Two examples of LVDS terminations are shown in this schematic. Figure 5 shows an example of 874003DI-02 application schematic. In this example, the device is operated at VDD = VDDO = 3.3V. The decoupling capacitors should be located as close as possible to Logic Control Input Examples Set Logic Input to '1' VDD Set Logic Input to '0' VDD RU1 1K RU2 Not Install To Logic Input pins To Logic Input pins RD1 Not Install 1 2 3 4 5 6 7 8 9 10 VDDO QA0 nQA0 MR F_SEL0 VDD = 3.3V VDDA 10 R2 + nQA0 U1 VDDO = 3.3V VDD Zo = 50 Ohm QA0 RD2 1K C1 0.1u F_SEL1 C2 10u VDDO = 3.3V QA1 VDDO QA0 nQA0 MR F_SEL0 nc VDDA F_SEL1 VDD nQA1 VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA 20 19 18 17 16 15 14 13 12 11 R1 100 Zo = 50 Ohm - VDDO QB0 nQB0 F_SEL2 OEB GND nCLK CLK OEA ICS874003DI-02 Zo = 50 Ohm Zo = 50 Ohm LVPECL Driv er QB0 CLK Zo = 50 Ohm R4 50 nCLK R6 50 R7 50 R8 50 VDDO VDD (U1:2)VDDO (U1:19) C4 .1uf C5 .1uf nQB0 Zo = 50 Ohm C3 0.1uF R5 50 + - VDD (U1:10) C6 10uf C7 .1uf Alternate LVDS Termination FIGURE 5. 874003DI-02 SCHEMATIC EXAMPLE PCI EXPRESS™ JITTER ATTENUATOR 10 REVISION A 7/17/15 874003DI-02 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 874003DI-02. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 874003DI-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 15mA) = 329.175mW • Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 75mA = 259.87mW Total Power_MAX = 329.2mW + 259.9mW = 589.1mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.589W * 66.6°C/W = 124.2°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. REVISION A 7/17/15 11 PCI EXPRESS™ JITTER ATTENUATOR 874003DI-02 DATA SHEET RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for 874003DI-02 is: 1408 PCI EXPRESS™ JITTER ATTENUATOR 12 REVISION A 7/17/15 874003DI-02 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN N MAX 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 REVISION A 7/17/15 13 PCI EXPRESS™ JITTER ATTENUATOR 874003DI-02 DATA SHEET TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 874003DGI-02LF ICS4003DI02L 20 Lead “Lead-Free” TSSOP tube -40°C to 85°C 874003DGI-02LFT ICS4003DI02L 20 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS complaint. PCI EXPRESS™ JITTER ATTENUATOR 14 REVISION A 7/17/15 874003DI-02 DATA SHEET REVISION HISTORY Rev Table Page Funtion T 1 1 8 14 A A T8 A REVISION A 7/17/15 1 Description of Change Corrected typo ‘QA0, nQA0:QA1, nQA1’. Removed HiPerClockS logo. Removed HiPerClockS references from drawings. Ordering Information - removed leaded devices. Updated data sheet format. Product Discontinuation Notice - Last time buy expires September 7, 2016. PDN N-16-02. 15 PCI EXPRESS™ JITTER ATTENUATOR Date 5/1/13 7/17/15 3/11/16 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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