874005AGLFT

874005 PCI Express™ Jitter Attenuator DATA SHEET GENERAL DESCRIPTION FEATURES The 874005 is a high performance Differential-to-LVDS Jitter Attenuator designed for use in PCI Express systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 874005 has 3 PLL bandwidth modes: 200kHz, 400kHz, and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have than x25 multipliers, the 874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins. • Five differential LVDS output pairs The 874005 uses IDT’s 3 rd Generation FemtoClock ® PLL technology to achive the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express add-in cards. PLL BANDWIDTH • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 160MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 30ps (maximum) • 3.3V operating supply • 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • 0°C to 70°C ambient operating temperature • Available in lead-free RoHS compliant package BW_SEL 0 = PLL Bandwidth: ~200kHz Float = PLL Bandwidth: ~400kHz (Default) 1 = PLL Bandwidth: ~800kHz PIN ASSIGNMENT BLOCK DIAGRAM nQB2 nQA1 QA1 VDDO QA0 nQA0 MR BW_SEL VDDA F_SELA VDD OEA 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 QB2 VDDO QB1 nQB1 QB0 nQB0 F_SELB OEB GND GND nCLK CLK 874005 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View 874005 REVISION B 7/20/15 1 ©2015 Integrated Device Technology, Inc. 874005 DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name 1, 24 nQB2, QB2 Output Type Description Differential output pair. LVDS interface levels. 2, 3 nQA1, QA1 Output Differential output pair. LVDS interface levels. 4, 23 VDDO Power Output supply pins. 5, 6 QA0, nQA0 Output Differential output pair. LVDS interface levels. 7 MR Input 8 BW_SEL Input 9 VDDA Power 10 F_SELA Input 11 VDD Power 12 OEA Input 13 CLK Input 14 nCLK Input 15, 16 GND Power Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inverted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pullup/ PLL Bandwidth input. See Table 3B. Pulldown Analog supply pin. Pulldown Frequency select pin for QAx,nQAx outputs. LVCMOS/LVTTL interface levels. Core supply pin. Pullup Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are active. When LOW, the QAx,nQAx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inverting differential clock input. Pullup Inverting differential clock input. Power supply ground. Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are Pullup active. When LOW, the QBx,nQBx outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Frequency select pin for QBx,nQBx outputs. Pulldown LVCMOS/LVTTL interface levels. 17 OEB Input 18 F_SELB Input 19, 20 nQB0, QB0 Output Differential output pair. LVDS interface levels. 21, 22 nQB1, QB1 Output Differential output pair. LVDS interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance 4 RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs Minimum Typical Units pF TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Outputs Inputs OEA/OEB QAx/nQAx QBx/nQBx PLL_BW PLL Bandwidth 0 HiZ HiZ 0 ~200kHz 1 Enabled Enabled 1 ~800kHz Float ~400kHz PCI Express™ Jitter Attenuator Maximum 2 REVISION B 7/20/15 874005 DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 85 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 115 mA Maximum Units VDD + 0.3 V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol VIH Parameter Input High Voltage Test Conditions OEA, OEB, MR, F_SELA, F_SELB Input Low Voltage Typical 2 BW_SEL VIL Minimum VDD - 0.4 OEA, OEB, MR, F_SELA, F_SELB -0.3 0.8 V 0.4 V VDD/2 + 0.1 V VDD = VIN = 3.465V 5 µA VDD = VIN = 3.465V 150 µA BW_SEL VIM Input Mid Voltage IIH Input High Current IIL Input Low Current REVISION B 7/20/15 BW_SEL OEA, OEB F_SELA, F_SELB MR, BW_SEL BW_SEL, OEA, OEB MR, F_SELA, F_SELB V VDD/2 - 0.1 VDD = 3.465V, VIN = 0V -150 µA VDD = 3.465V, VIN = 0V -5 µA 3 PCI Express™ Jitter Attenuator 874005 DATA SHEET TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol IIH Parameter Input High Current Test Conditions Minimum Typical Maximum Units 150 µA 5 µA CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V CLK VDD = VIN = 3.465V -5 µA nCLK VDD = VIN = 3.465V -150 µA IIL Input Low Current VPP Peak-to-Peak Input Voltage 0.15 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. 1.3 V VDD - 0.85 V TABLE 4D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 275 375 485 mV 50 mV 1.2 1.35 1.5 V 50 mV Maximum Units 160 MHz 30 ps TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tjit(cc) Cycle-to-Cycle Jitter, NOTE 1 tsk(o) Output Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical 98 15 20% to 80% 90 ps 300 550 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons. NOTE 1: This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. PCI Express™ Jitter Attenuator 4 REVISION B 7/20/15 874005 DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL CYCLE-TO-CYCLE JITTER OUTPUT SKEW OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD DIFFERENTIAL OUTPUT VOLTAGE SETUP OFFSET VOLTAGE SETUP REVISION B 7/20/15 5 PCI Express™ Jitter Attenuator 874005 DATA SHEET APPLICATIONS INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VDD/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VDD are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50W applications, R3 and R4 can be 100W. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels PCI Express™ Jitter Attenuator 6 REVISION B 7/20/15 874005 DATA SHEET DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 1.8V 3.3V 3.3V 3.3V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 LVPECL R1 50 R2 50 3.3V Zo = 50 Ohm R2 50 R3 50 FIGURE 3A. CLK/nCLK INPUT DRIVEN BY LVHSTL DRIVER 3.3V HiPerClockS Input R3 125 FIGURE 3B. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R4 125 Zo = 50 Ohm LVDS_Driv er CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input Zo = 50 Ohm nCLK Receiv er R2 84 FIGURE 3C. CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. REVISION B 7/20/15 LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. 7 PCI Express™ Jitter Attenuator 874005 DATA SHEET LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION PCI Express™ Jitter Attenuator 8 REVISION B 7/20/15 874005 DATA SHEET SCHEMATIC EXAMPLE DIFFERENTIAL CLOCK INPUT INTERFACE be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The VCC and VCCO filters start to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. Figure 5 is an 874005 application example schematic. The schematic focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. The input is provided by 3.3V LVPECL driver with a Y-termination for simplicity, ease of layout and better control of the termination power over device variations. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 874005 provides separate VDD and VDDO power supplies to isolate any high switching noise from coupling into the internal PLL. In order to achieve the best possible filtering, it is recommended that the placement of the filter components FIGURE 5. 874005 SCHEMATIC EXAMPLE REVISION B 7/20/15 9 PCI Express™ Jitter Attenuator 874005 DATA SHEET POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the 874005. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the 874005 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • • Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (85mA + 15mA) = 346.5mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 115mA = 398.48mW Total Power_MAX = 3.465mW + 398.48mW = 745mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for the devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.745W * 63°C/W = 117°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 24-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W 200 63°C/W 500 60°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. PCI Express™ Jitter Attenuator 10 REVISION B 7/20/15 874005 DATA SHEET RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 70°C/W 63°C/W 60°C/W TRANSISTOR COUNT The transistor count for 874005 is: 1206 REVISION B 7/20/15 11 PCI Express™ Jitter Attenuator 874005 DATA SHEET PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 PCI Express™ Jitter Attenuator 12 REVISION B 7/20/15 874005 DATA SHEET TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 874005AGLF ICS874005AGLF 24 Lead “Lead-Free” TSSOP tube 0°C to 70°C 874005AGLFT ICS874005AGLF 24 Lead “Lead-Free” TSSOP tape & reel 0°C to 70°C NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS complaint. REVISION B 7/20/15 13 PCI Express™ Jitter Attenuator 874005 DATA SHEET REVISION HISTORY SHEET Rev A B B Table Page T9 12 14 1 4C T9 PCI Express™ Jitter Attenuator 1 2 4 7 9 13 Description of Change Updated datasheet’s header/footer with IDT from ICS. Ordering Information Table - removed ICS prefix from Part/Order Number column. Added LF marking. Added Contact Page. Updated datasheet’s header/footer with IDT format. Change Block Diagram to update OEA input to Pullup from Pulldown. Removed nFB_OUT from Pin Descriptions. Added IIH Min and IIL Max ratings. Added new figure 2. Added New Application Schematic. Ordering Information - removed leaded devices. Updated data sheet format. 14 Date 10/5/10 1/12/12 7/20/15 REVISION B 7/20/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. 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