87604AGILF

87604I Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator DATA SHEET GENERAL DESCRIPTION FEATURES The 87604I is a 1:4 PCI/PCI-X Clock Generator. The 87604I has a selectable REF_IN or crystal input. The REF_IN input accepts LVCMOS or LVTTL input levels. The 87604I has a fully integrated PLL along with frequency configurable clock and feedback outputs for multiply-ing and regenerating clocks with “zero delay”. The PLL’s VCO has an operating range of 250MHz - 500MHz, allowing this device to be used in a variety of general purpose clocking applications. For PCI/PCI-X applications in particular, the VCO frequency should be set to 400MHz. This can be accomplished by supplying 33.33MHz, 25MHz, 20MHz, or 16.66MHz on the reference clock or crystal input and by selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback divide value. The divider on the output bank can then be configured to generate 33.33MHz (÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3). • Fully integrated PLL The 87604I is character ized to operate with its core supply at 3.3V and the bank supply at 3.3V or 2.5V. The 87604I is packaged in a small 6.1mm x 9.7mm TSSOP body, making it ideal for use in space-constrained applications. • VCO range: 250MHz to 500MHz • Four LVCMOS/LVTTL outputs, 15Ω typical output impedance • Selectable crystal oscillator interface or LVCMOS/LVTTL REF_IN clock input • Maximum output frequency: 166.67MHz • Maximum crystal input frequency: 38MHz • Maximum REF_IN input frequency: 41.67MHz • Individual banks with selectable output dividers for generating 33.333MHz, 66.66MHz, 100MHz and 133.333MHz • Separate feedback control for generating PCI / PCI-X frequencies from a 16.66MHz or 20MHz crystal, or 25MHz or 33.33MHz reference frequency • Cycle-to-cycle jitter: 120ps (maximum) • Period jitter, RMS: 20ps (maximum) • Output skew: 65ps (maximum) • Static phase offset: 160ps ± 160ps • Voltage Supply Modes: VDD/VDDA/VDDO 3.3/3.3/3.3 3.3/3.3/2.5 • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM • Available in lead-free (RoHS 6) package PIN ASSIGNMENT VDD FB_IN GND FB_OUT REF_OUT VDDO Q3 Q2 GND Q1 Q0 VDDO PLL_SEL VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 FBDIV_SEL1 FBDIV_SEL0 DIV_SEL1 DIV_SEL0 nc MR nc GND GND nc REF_IN XTAL_OUT XTAL_IN XTAL_SEL 87604I 28-Lead TSSOP, 240MIL 6.1mm x 9.7mm x 0.92mm body package G Package Top View 87604I REVISION B 11/11/15 1 ©2015 Integrated Device Technology, Inc. 87604I DATA SHEET TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 VDD Power 2 FB_IN Input 3, 9, 20, 21 GND Power Power supply ground. 4 FB_OUT Output Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels. Core supply pin. Pulldown Feedback input to phase detector for generating clocks with “zero delay”. LVCMOS / LVTTL interface levels. 5 REF_OUT Output Reference clock output. LVCMOS / LVTTL interface levels. 6, 12 VDDO Power Output supply pin 7, 8, 10, 11 Q3, Q2, Q1, Q0 Output 13 PLL_SEL Input 14 VDDA Power 15 XTAL_SEL Input 16, 17 XTAL_IN, XTAL_OUT Input 18 REF_IN Input 19, 22, 24 nc Unused 23 MR Input 25, 26 27, 28 DIV_SEL0, DIV_SEL1 FBDIV_SEL0, FBDIV_SEL1 Input Input Pullup Clock outputs. 15Ω typical output impedance. LVCMOS / LVTTL interface levels. Selects between PLL and bypass mode. When HIGH, selects PLL. When LOW, selects reference clock. LVCMOS / LVTTL interface levels. Analog supply pin. See Applications Note for filtering. Pullup Selects between crystal oscillator or reference clock as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_IN when LOW. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pulldown Reference clock input. LVCMOS / LVTTL interface levels. No connect. Active HIGH Master Reset. When logic HIGH, the internal dividers Pulldown are reset causing the outputs go low. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Selects divide value for clock outputs as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Selects divide value for reference clock output and feedback output. Pulldown LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance RPULLUP Maximum Units Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ CPD Power Dissipation Capacitance (per output); NOTE 1 ROUT Output Impedance Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator Test Conditions Minimum Typical 4 pF VDD, VDDA, VDDO = 3.465V 9 pF VDD, VDDA = 3.465V; VDDO = 2.625V 11 pF 15 2 Ω REVISION B 11/11/15 87604I DATA SHEET TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE Inputs Outputs MR Q0:Q3 FB_OUT, REF_OUT 1 LOW LOW 0 Active Active TABLE 3C. PLL INPUT FUNCTION TABLE TABLE 3B. OPERATING MODE FUNCTION TABLE Inputs Inputs Operating Mode PLL_SEL XTAL_SEL PLL Input 0 Bypass 0 REF_IN 1 PLL 1 XTAL Oscillator TABLE 3D. CONTROL FUNCTION TABLE Outputs Inputs PLL_SEL=1 Frequency FBDIV_SEL1 FBDIV_SEL0 DIV_SEL1 DIV_SEL0 Reference Frequency Range (MHz) 0 0 0 0 16.67 - 41.67 x4 0 0 0 1 16.67 - 41.67 x3 50 - 125 16.67 - 41.67 0 0 1 0 16.67 - 41.67 x2 33.34 - 83.34 16.67 - 41.67 0 0 1 1 16.67 - 41.67 x1 16.67 - 41.67 16.67 - 41.67 0 1 0 0 12.5 - 31.25 x 5.33 66.63 - 166.56 12.5 - 31.25 0 1 0 1 12.5 - 31.25 x4 50 - 125 12.5 - 31.25 0 1 1 0 12.5 - 31.25 x 2.667 33.34 - 83.34 12.5 - 31.25 0 1 1 1 12.5 - 31.25 x 1.33 16.63 - 41.56 12.5 - 31.25 1 0 0 0 10 - 25 x 6.667 66.67 - 166.68 10 - 25 1 0 0 1 10 - 25 x5 50 - 125 10 - 25 1 0 1 0 10 - 25 x 3.33 33.30 - 83.25 10 - 25 1 0 1 1 10 - 25 x 1.66 16.60 - 41.50 10 - 25 1 1 0 0 8.33 - 20.83 x8 66.64 - 166.64 8.33 - 20.83 1 1 0 1 8.33 - 20.83 x6 50 - 125 8.33 - 20.83 1 1 1 0 8.33 - 20.83 x4 33.32 - 83.32 8.33 - 20.83 1 1 1 1 8.33 - 20.83 x2 16.66 - 41.66 8.33 - 20.83 Q0:Q3 Q0:Q3 (MHz) FB_OUT (MHz) 66.68 - 166.68 16.67 - 41.67 NOTE: VCO frequency range for all configurations above is 250MHz to 500MHz. REVISION B 11/11/15 3 Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 87604I DATA SHEET ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VDD -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 64.5°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 185 mA IDDA Analog Supply Current 15 mA IDDO Output Supply Current 20 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL IIH Test Conditions Typical Maximum Units MR, DIV_ SEL0, DIV_SEL1, FBDIV_SEL0, FBDIV_SEL1, XTAL_SEL, FB_IN, PLL_SEL 2 V + 0.3 V REF_IN 2 V + 0.3 V DD DD Input Low Voltage MR, DIV_ SEL0, DIV_SEL1, FBDIV_SEL0, FBDIV_SEL1, XTAL_SEL, FB_IN, PLL_SEL -0.3 0.8 V REF_IN -0.3 1.3 V Input High Current DIV_ SEL0, DIV_SEL1, FBDIV_SEL0, FBDIV_SEL1, MR, FB_IN V =V = 3.465V 150 µA V =V = 3.465V 5 µA DD XTAL_SEL, PLL_SEL IIL Minimum Input Low Current DIV_ SEL0, DIV_SEL1, FBDIV_SEL0, FBDIV_SEL1, MR, FB_IN IN DD IN VDD = 3.465V, -5 µA -150 µA V =V = 3.465V 2.6 V V =V = 2.625V 1.8 V VIN = 0V VDD = 3.465V, XTAL_SEL, PLL_SEL VIN = 0V DD VOH Output High Voltage; NOTE 1 IN DD IN V =V = 3.465V or VOL Output Low Voltage; NOTE 1 2.625V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section, “3.3V Output Load Test Circuit”. DD Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator IN 4 0.5 V REVISION B 11/11/15 87604I DATA SHEET TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 10 Equivalent Series Resistance (ESR) Shunt Capacitance 38 MHz 50 Ω 1 mW 7 pF Drive Level TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fREF Reference Frequency Test Conditions Minimum Typical 8.33 Maximum Units 41.67 MHz Maximum Units 166.67 MHz 325 ps TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical FREF = 25MHz 0 160 fMAX Output Frequency t(Ø) Static Phase Offset; NOTE 1 tsk(o) Output Skew; NOTE 2, 5 65 ps tjit(cc) Cycle-to-Cycle Jitter; 5 120 ps tjit(per) Period Jitter, RMS; NOTE 3, 5, 6 tsl(o) Slew Rate tL PLL Lock Time tR / tF Output Rise/Fall Time 1 20% to 80% 200 20 ps 4 V/ns 10 ms 700 ps odc Output Duty Cycle; NOTE 4 48 52 % NOTE: All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the PLL is locked and the input reference frequency is stable. Measured at VDD/2. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Jitter performance using LVCMOS inputs. NOTE 4: Measured using REF_IN. For XTAL input, refer to Application Note. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: This parameter is defined as an RMS value. TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions t(Ø) Static Phase Offset; NOTE 1 160 ps tsk(o) Output Skew; NOTE 2, 5 50 ps tjit(cc) Cycle-to-Cycle Jitter; 5 170 ps tjit(per) Period Jitter, RMS; NOTE 3, 5, 6 20 ps tsl(o) Slew Rate tL PLL Lock Time tR / tF Output Rise/Fall Time odc Output Duty Cycle; NOTE 4 FREF = 25MHz Minimum -365 1 20% to 80% Typical -105 Maximum Units 166.67 MHz 4 V/ns 10 ms 200 700 ps 48 52 % See Table 7A for notes. REVISION B 11/11/15 5 Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 87604I DATA SHEET PARAMETER MEASUREMENT INFORMATION 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW CYCLE-TO-CYCLE JITTER STATIC PHASE OFFSET OUTPUT RISE/FALL TIME OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 6 REVISION B 11/11/15 87604I DATA SHEET APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The 87604I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, V DDA, and V DDO should be individually connected to the power supply plane through vias, and 0.01μF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. The 10Ω resistor can also be replaced by a ferrite bead. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUT For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. CRYSTAL INPUT INTERFACE The 87604I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the frequency ppm error. The optimum C1 and C2 values can be slightly adjusted for optimum frequency accuracy. XTAL_IN C1 22pF X1 18pF Parallel Crystal XTAL_OUT C2 22pF FIGURE 2. CRYSTAL INPUt INTERFACE REVISION B 11/11/15 7 Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 87604I DATA SHEET OVERDRIVING THE CRYSTAL INTERFACE The XTAL_IN input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The XTAL_OUT pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than .2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 3A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and changing R2 to 50Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. Figure 2 shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the XTAL_IN input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. 3.3V 3.3V R1 100 C1 Zo = 50 Ohm Ro ~ 7 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace FIGURE 3A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm LVPECL 0.1uF XTAL_OUT Cry stal Input Interf ace R2 50 R3 50 FIGURE 3B. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 8 REVISION B 11/11/15 87604I DATA SHEET SCHEMATIC EXAMPLE For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. The logic control inputs are either pull up or pull down depending on the application requirement. If there is space available, it is recommended to provide spare footprints as shown in the schematic for flexibility of choosing pull up or pull down. Figure 4 shows a schematic example of the 87604I. Series termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18 pF parallel resonant 25MHz crystal is used. The C1=22pF and C2=22pF are recommended for frequency accuracy. FIGURE 4. ICS87604I SCHEMATIC EXAMPLE REVISION B 11/11/15 9 Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 87604I DATA SHEET RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 64.5°C/W 1 2.5 60.4°C/W 58.5°C/W TRANSISTOR COUNT The transistor count for 87604I is: 5495 PACKAGE OUTLINE AND PACKAGE DIMENSIONS TABLE 9. PACKAGE DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP SYMBOL Millimeters Minimum N Maximum 28 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 9.60 9.80 E E1 8.10 BASIC 6.00 e 6.20 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 10 REVISION B 11/11/15 87604I DATA SHEET TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 87604AGILF ICS87604AGILF 28 Lead “Lead-Free” TSSOP tube -40°C to 85°C 87604AGILFT ICS87604AGILF 28 Lead “Lead-Free” TSSOP tape & reel -40°C to 85°C NOTE: Parts that are with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION B 11/11/15 11 Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator 87604I DATA SHEET REVISION HISTORY SHEET Rev Table A T7A & T7B 5 AC Characteristics Tables - corrected note sequence. 3/18/05 A 10 10 Ordering Information Table - added marking. 4/12/05 1 5 6 8 Pin Assignment and General Description - corrected package dimension. Crystal Characteristics - added Drive Level. Updated Output Load AC Test Circuit Diagrams. Application Information - added LVCMOS to XTAL Interface and Recommendations for Unused Input and Output Pins sections. Package Dimensions - corrected “E” and “E1” dimensions. Pin Assignment and General Description - corrected package dimension. Package Dimensions - corrected “E” and “E1” dimensions. T5 B T9 B T9 10 1 10 T10 4 9 10 1 5 8 11 T10 11 B T7A B B Page Low Voltage/Low Skew, 1:4 PCI/PCI-X Zero Delay Clock Generator Description of Change Date Absolute Maximum Ratings - updated Package Thermal Impedance. Added Schematic Layout. Reliability Information - updated Package Thermal Impedance. Pin Assignment, corrected 173-MIL to 240-MIL. AC Characteristics Table, added Thermal Note. Updated the Overdriving the Crystal Interface section. Ordering Information Table - deleted “ICS” prefix from Part/Order Number column. Added new Header/Footer in datasheet. Ordering Information - removed leaded devices. Updated data sheet format. 12 3/8/06 8/18/06 1/11/08 4/1/10 11/11/15 REVISION B 11/11/15 Corporate Headquarters 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 or +408-284-8200 Fax: 408-284-2775 www.IDT.com Technical Support email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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