8761
Low Voltage, Low Skew,
PCI / PCI-X Clock Generator
DATASHEET
GENERAL DESCRIPTION
FEATURES
The 8761 is a low voltage, low skew PCI /
PCI-X Clock Generator. The 8761 has a selectable REF_
CLK or crystal input. The REF_CLK input accepts LVCMOS or LVTTL input levels. The 8761 has a fully intgrated PLL along with frequency configurable clock and
feedback outputs for multiplying and regenerating clocks
with “zero delay”. Using a 20MHz or 25MHz crystal or a
33.333MHz or 66.666MHz reference frequency, the 8761 will
generate output frequencies of 33.333MHz, 66.666MHz,
100MHz and 133.333MHz simultaneously.
• Fully integrated PLL
• Seventeen LVCMOS/LVTTL outputs,
15Ω typical output impedance
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_CLK
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_CLK input frequency: 83.33MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz simultaneously
• Separate feedback control for generating PCI / PCI-X
frequencies from a 20MHz or 25MHz crystal or 33.333MHz
or 66.666MHz reference frequency
• Cycle-to-cycle jitter: 70ps (maximum)
• Period jitter, RMS: 17ps (maximum)
• Output skew: 230ps (maximum)
• Bank skew: 40ps (maximum)
• Static phase offset: 0 ± 150ps (maximum)
• Full 3.3V or 3.3V core, 2.5V multiple output supply modes
• 0°C to 85°C ambient operating temperature
The low impedance LVCMOS/LVTTL outputs of the 8761
are designed to drive 50Ω series or parallel terminated
transmission lines.
BLOCK DIAGRAM
• Available in lead-free RoHS-compliant package
QD3
VDDOD
QD2
GND
QD1
VDDOD
QD0
GND
QC3
VDDOC
QC2
GND
QC1
VDDOC
QC0
GND
PIN ASSIGNMENT
REF_CLK
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
GND
2
47
FB_OUT
XTAL1
3
46
VDDOFB
4
45
FB_IN
VDD
5
44
VDD
XTAL_SEL
6
43
FBDIV_SEL0
PLL_SEL
7
42
FBDIV_SEL1
VDDA
8
41
MR
VDD
9
40
VDD
XTAL2
8761
GND
D_SELC0
10
39
D_SELD0
D_SELC1
11
38
D_SELD1
OEC
12
37
OED
OEA
13
36
OEB
D_SELA0
14
35
D_SELB0
D_SELA1
15
34
D_SELB1
GND
QB3
VDDOB
QB2
GND
QB1
VDDOB
QB0
GND
QA3
VDDOA
QA2
GND
QA1
VDDOA
QA0
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GND
GND
64-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
8761 REVISION E 2/18/15
1
©2015 Integrated Device Technology, Inc.
8761 DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
REF_CLK
Input
2, 16, 17, 21,
25, 29, 33, 48,
52, 56, 60, 64
GND
Power
Power supply ground.
3, 4
XTAL1, XTAL2
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
5, 9, 40, 44
VDD
Power
Core supply pins.
6
XTAL_SEL
Input
Pullup
7
PLL_SEL
Input
Pullup
8
VDDA
Power
10, 11
D_SELC0,
D_SELC1
Input
12
OEC
Input
13
OEA
Input
14, 15
18, 20,
22, 24
D_SELA0,
D_SELA1
QA0, QA1,
QA2, QA3
Type
Input
Output
Description
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
Selects between crystal oscillator or reference clock as the PLL reference source. Selects XTAL inputs when HIGH. Selects REF_CLK when
LOW. LVCMOS / LVTTL interface levels.
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
Analog supply pin. See Applications Note for filtering.
Selects divide value for Bank C outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank C outputs. When HIGH, outputs are enabled.
Pullup
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank A outputs. When HIGH, outputs are enabled.
Pullup
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank A outputs as described in Table 3.
Pulldown
LVCMOS / LVTTL interface levels.
Bank A clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Pulldown
19, 23
VDDOA
Power
Output supply pins for Bank A outputs.
26, 28,
30, 32
QB0, QB1,
QB2, QB3
Output
Bank B clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
27, 31
VDDOB
Power
Output supply pins for Bank B outputs.
34, 35
D_SELB1,
D_SELB0
Input
Pulldown
36
OEB
Input
Pullup
37
OED
Input
Pullup
38, 39
D_SELD1,
D_SELD0
Input
Pulldown
41
MR
Input
Pulldown
42
FBDIV_SEL1
Input
Pulldown
43
FBDIV_SEL0
Input
Pullup
45
FB_IN
Input
Pulldown
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
Selects divider value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
Selects divider value for Bank D outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Active HIGH Master reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with “zero delay”.
LVCMOS / LVTTL interface levels.
2
REVISION E 2/18/15
8761 DATA SHEET
Number
Name
46
VDDOFB
Power
Type
47
FB_OUT
Output
49, 51,
53, 55
50, 54
57, 59,
61, 63
QD3, QD2,
QD1, QD0
VDDOD
QC3, QC2,
QC1, QC0
58, 62
VDDOC
Description
Output supply pin for FB_Out output.
Feedback output. Connect to FB_IN. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank D clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output supply pins for Bank D outputs.
Bank C clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Power
Output
Power
Output supply pins for Bank C outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation Capacitance
(per output); NOTE 1
ROUT
Output Impedance
4
pF
VDD, VDDA = 3.465V; VDDOx = 3.465V
9
pF
VDD, VDDA = 3.465V; VDDOx = 2.625V
11
pF
Ω
15
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, VDDOFB.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
MR
OEA
OEB
OEC
OED
QA0:QA3
1
1
1
1
1
LOW
LOW
LOW
LOW
0
1
1
1
1
Active
Active
Active
Active
X
0
0
0
0
HiZ
HiZ
HiZ
HiZ
PLL_SEL
QC0:QC3
TABLE 3C. PLL INPUT FUNCTION TABLE
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
QB0:QB3
Inputs
Operating Mode
XTAL_SEL
PLL Input
0
Bypass
0
REF_CLK
1
PLL
1
XTAL Oscillator
REVISION E 2/18/15
3
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
QD0:QD3
8761 DATA SHEET
TABLE 3D. CONTROL FUNCTION TABLE
Outputs
Inputs
PLL_SEL =1
Frequency
Reference Frequency Range
(MHz)
QX0:QX3
QX0:QX3 (MHz)
FB_OUT
(MHz)
0
41.6 - 83.33
x2
83.33 - 166.67
41.6 - 83.33
0
1
20.83 - 41.67
x4
83.33 - 166.67
20.83 - 41.67
0
1
0
15.62 - 31.25
x 5.33
83.33 - 166.67
15.62 - 31.25
0
1
1
12.5 - 25
x 6.67
83.33 - 166.67
12.5 - 25
0
1
0
0
41.6 - 83.33
x 1.5
62.4 - 125
41.6 - 83.33
0
1
0
1
20.83 - 41.67
x3
62.4 - 125
20.83 - 41.67
0
1
1
0
15.62 - 31.25
x4
62.4 - 125
15.62 - 31.25
0
1
1
1
12.5 - 25
x5
62.4 - 125
12.5 - 25
1
0
0
0
41.6 - 83.33
x1
41.6 - 83.33
41.6 - 83.33
1
0
0
1
20.83 - 41.67
x2
41.6 - 83.33
20.83 - 41.67
1
0
1
0
15.62 - 31.25
x 2.67
41.6 - 83.33
15.62 - 31.25
1
0
1
1
12.5 - 25
x 3.33
41.6 - 83.33
12.5 - 25
1
1
0
0
41.6 - 83.33
÷2
20.8 - 41.67
41.6 - 83.33
1
1
0
1
20.83 - 41.67
÷1
20.8 - 41.67
20.83 - 41.67
1
1
1
0
15.62 - 31.25
x 1.33
20.8 - 41.67
15.62 - 31.25
1
1
1
1
12.5 - 25
x 1.67
20.8 - 41.67
12.5 - 25
D_SELx1
D_SELx0
FBDIV_SEL1 FBDIV_SEL0
0
0
0
0
0
0
0
NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0, D_
SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
TABLE 3E. CONTROL FUNCTION TABLE (PCI CONFIGURATION)
Outputs
Inputs
PLL_SEL = 1
Frequency
D_SELx1
D_SELx0
FBDIV_SEL1
FBDIV_SEL0
0
0
0
0
Reference Frequency
(MHz)
66.67
x2
QX0:QX3
(MHz)
133
0
0
0
1
33.33
x4
133
33.33
0
0
1
0
25
x 5.33
133
25
0
0
1
1
20
x 6.67
133
20
0
1
0
0
66.67
x 1.5
100
66.67
0
1
0
1
33.33
x3
100
33.33
0
1
1
0
25
x4
100
25
0
1
1
1
20
x5
100
20
1
0
0
0
66.67
x1
66.67
66.67
1
0
0
1
33.33
x2
66.67
33.33
1
0
1
0
25
x 2.67
66.67
25
1
0
1
1
20
x 3.33
66.67
20
1
1
0
0
66.67
÷2
33.33
66.67
1
1
0
1
33.33
÷1
33.33
33.33
1
1
1
0
25
x 1.33
33.33
25
QX0:QX3
FB_OUT
(MHz)
66.67
1
1
1
1
20
x 1.67
33.33
20
NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0, D_
SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
4
REVISION E 2/18/15
8761 DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDOx + 0.5V
Package Thermal Impedance, θJA
41.1°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDDOx
Output Supply Voltage; NOTE 1
3.135
3.3
3.465
V
IDD
Power Supply Current
175
mA
IDDA
Analog Supply Current
55
mA
IDDOx
Output Supply Current; NOTE 2
25
mA
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB.
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB.
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 85°C
X
Symbol
Parameter
VDD
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
3.135
3.3
3.465
V
VDDOx
Output Supply Voltage; NOTE 1
2.375
2.5
2.625
V
IDD
Power Supply Current
160
mA
IDDA
Analog Supply Current
50
mA
IDDOx
Output Supply Current; NOTE 2
210
mA
NOTE 1: VDDOx denotes VDDOA, VDDOB, VDDOC, VDDOD, and VDDOFB.
NOTE 2: IDDOx denotes IDDOA, IDDOB, IDDOC, IDDOD, and IDDOFB.
REVISION E 2/18/15
5
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8761 DATA SHEET
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 85°C
Symbol
VIH
VIL
IIH
IIL
VOH
Parameter
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
Test Conditions
Maximum
Units
2
VDD + 0.3
V
2
VDD + 0.3
V
OEA:OED, XTAL_SEL, MR, D_SELA0:D_SELD0, FB_IN,
D_SELA1, D_SELD1, PLL_SEL
-0.3
0.8
V
REF_CLK
-0.3
1.3
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
OEA:OED, XTAL_SEL, MR, D_SELA0:D_SELD0, FB_IN,
D_SELA1:D_SELD1, PLL_SEL,
FBDIV_SEL0, FBDIV_SEL1
REF_CLK
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
FBDIV_SEL1
XTAL_SEL, PLL_SEL, FBDIV_
SEL0, OEA:OED
D_SELA0:D_SELD0, FB_IN, MR,
D_SELA1:D_SELD1, REF_CLK,
FBDIV_SEL1
XTAL_SEL, PLL_SEL, FBDIV_
SEL0, OEA:OED
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IOZL
Output Tristate Current Low
IOZH
Output Tristate Current High
Minimum
Typical
VDD = 3.465V,
VIN = 0V
-5
µA
VDD = 3.465V,
VIN = 0V
-150
µA
VDDOx = 3.465V
2.6
V
VDDOx = 2.625V
1.8
V
VDDOx = 3.465V
or 2.625V
0.5
V
-5
µA
5
µA
NOTE 1: Outputs terminated with 50W to VDDOx/2. See Parameter Measurement Information section,
“Output Load Test Circuit” Diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
10
Equivalent Series Resistance (ESR)
Shunt Capacitance
38
MHz
70
Ω
1
mW
7
pF
Drive Level
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 85°C
X
Symbol
Parameter
fREF
Reference Frequency
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
Test Conditions
Minimum
10
6
Typical
Maximum
Units
83.33
MHz
REVISION E 2/18/15
8761 DATA SHEET
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDOX = 3.3V±5%, TA = 0°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 7
tsk(b)
Bank Skew; NOTE 2, 6
tsk(o)
Output Skew; NOTE 3, 6
Test Conditions
f = 50MHz
Minimum
Typical
Maximum
Units
166.67
MHz
-150
150
ps
40
ps
230
ps
f = 50MHz; NOTE 4, 7
70
ps
f = 25MHz XTAL,
133.3MHz out
190
ps
tjit(cc)
Cycle-to-Cycle Jitter; 6
tjit(per)
Period Jitter, RMS; NOTE 4, 6, 7, 8
17
ps
tL
PLL Lock Time
1
ms
tR
Output Rise Time
20% to 80%
300
800
ps
tF
Output Fall Time
20% to 80%
300
800
ps
odc
Output Duty Cycle; NOTE 5, 7
45
55
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from VDD/2 of the input to
VDDOx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOx/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defined as an RMS value.
%
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 85°C
X
Symbol
Parameter
fMAX
Output Frequency
t(Ø)
Static Phase Offset; NOTE 1, 7
tsk(b)
Bank Skew; NOTE 2, 6
tsk(o)
Output Skew; NOTE 3, 6
Test Conditions
f = 50MHz
Minimum
Typical
Maximum
Units
166.67
MHz
-350
20
ps
40
ps
230
ps
f = 50MHz; NOTE 4, 7
70
ps
f = 25MHz XTAL,
133.3MHz out
190
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 6
tjit(per)
Period Jitter, RMS; NOTE 4, 6, 7, 8
17
ps
tL
PLL Lock Time
1
ms
tR
Output Rise Time
20% to 80%
300
800
ps
tF
Output Fall Time
20% to 80%
300
800
ps
odc
Output Duty Cycle; NOTE 5, 7
45
55
%
See notes in Table 7A above.
REVISION E 2/18/15
7
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8761 DATA SHEET
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
BANK SKEW (Where X denotes outputs in the same Bank)
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
CYCLE-TO-CYCLE JITTER
STATIC PHASE OFFSET
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8
REVISION E 2/18/15
8761 DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 8761 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and
VDDOx should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a ferrite bead along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The 8761 crystal interface is shown in Figure 2. While layout
the PC Board, it is recommended to provide C1 and C2 spare
footprints for frequency fine tuning. For an 18pF parallel res-
onant crystal, the C1 and C2 are expected to be ~10pF and
~5pF respectively.
XTAL2
C1
SPARE
X1
18pF Parallel Cry stal
XTAL1
C2
SPARE
FIGURE 2. CRYSTAL INPUT INTERFACE
REVISION E 2/18/15
9
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8761 DATA SHEET
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
10
REVISION E 2/18/15
8761 DATA SHEET
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the 8761. In this
example, the input is driven by an ICS LVHSTL driver. The
decoupling capacitors should be physically located near
the power pin. For 8761, the unused clock outputs can be
left floating. The optional C1 and C2 are spare footprints for
frequency fine tuning.
Zo = 50
R1
36
VDDO
Receiv er
VDD
1K
X1
25MHz,18pF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FB
C2
SP
VDD
C17
C16
10u
36
Receiv er
GND
FB_OUT
VDDOFB
FB_IN
VDD
FBDIV_SEL0
FBDIV_SEL1
MR
VDD
D_SELD0
D_SELD1
OED
OEB
D_SELB0
D_SELB1
GND
REF_CLK
GND
XTAL1
XTAL2
VDD
XTAL_SEL
PLL_SEL
VDDA
VDD
D_SELC0
D_SELC1
OEC
OEA
D_SELA0
D_SELA1
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDO
VDD
SP = Spare, Not Install
ICS8761
Zo = 50
R3
GND
QA0
VDDOA
QA1
GND
QA2
VDDOA
QA3
GND
QB0
VDDOB
QB1
GND
QB2
VDDOB
QB3
0.1u
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1K
Zo = 50
R2
U1
GND
QC0
VDDOC
QC1
GND
QC2
VDDOC
QC3
GND
QD0
VDDOD
QD1
GND
QD2
VDDOD
QD3
VDD
R6
36
Receiv er
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1
SP
R5
VDDO
Zo = 50
R4
Logic Input Pin Examples
VDD
Set Logic
Input to '1'
VDD
Set Logic
Input to '0'
RU2
SP
RU1
1K
To Logic
Input pins
To Logic
Input pins
RD1
SP
RD2
1K
(U1,5)
(U1,9)
VDD
(U1,40)
36
(U1,44)
C6
C5
C4
C3
0.1u
0.1u
0.1u
0.1u
(U1,23)
(U1,19)
VDDO
Receiv er
VDD=3.3V
VDDO=3.3V
(U1,27)
(U1,31)
(U1,50)
(U1,54)
(U1,58)
(U1,46)
C7
C8
C9
C10
C11
C12
C13
C14
C15
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
FIGURE 3. 8761 CLOCK GENERATOR SCHEMATIC EXAMPLE
REVISION E 2/18/15
(U1,62)
11
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8761 DATA SHEET
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 64 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
58.8°C/W
41.1°C/W
48.5°C/W
35.8°C/W
43.2°C/W
33.6°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 8761 is: 6040
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
12
REVISION E 2/18/15
8761 DATA SHEET
PACKAGE OUTLINE - Y SUFFIX FOR 64 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BCD
MINIMUM
NOMINAL
N
MAXIMUM
64
A
--
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.17
--
0.27
c
0.09
--
0.20
--
D
12.00 BASIC
D1
10.00 BASIC
D2
7.50 Ref.
E
12.00 BASIC
E1
10.00 BASIC
E2
7.50 Ref.
e
1.60
0.50 BASIC
L
0.45
--
0.75
θ
0°
--
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
REVISION E 2/18/15
13
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
8761 DATA SHEET
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8761CYLF
ICS8761CYLF
64 Lead “Lead-Free” LQFP
tray
0°C to 85°C
8761CYLFT
ICS8761CYLF
64 Lead “Lead-Free” LQFP
tape & reel
0°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
14
REVISION E 2/18/15
8761 DATA SHEET
Rev
A
Table
T1
T1
Page
2
2
A
T4B, T4D
6, 8
1
T3D
4
T5A, T5B
7, 9
B
T1
2
T5A, T5B
7, 9
T1
T4A, T4C
10
11
2
5, 7
B
B
10
10
1
T3D
4
T4A
5
T5A & T5B
6&8
C
1
10
14
C
C
T2
T5
14
3
6
9
LVCMOS DC Characteristics table -in the IIH and IIL rows, FBDIV_SEL0 was
deleted from the “pulldown” row and was added to the “pullup” row.
Features section, changed max. output frequency from 200MHz to 183.3MHz,
and max. REF_CLK input frequency from 100MHz to 91.6MHz.
Control Function Table - revised Reference Frequency Range column and Frequency columns to reflect the output frequency change.
AC Characteristics tables - changed Output Frequency from 200MHz max. to
183.3MHz max.
Pin Description Table, revised crystal description.
AC Characteristics tables - changed Period Jitter measurement to
Period Jitter, RMS and added NOTE 8.
Added Crystal information.
Added Schematic Example in the Application Information Section.
Pin Description Table - revised MR description.
Power Supply Tables - changed VDD parameter to read “Core Supply Voltage”
from “Positive Supply Voltage”.
Deleted Crystal Input Interface section.
Updated Schematic Example diagram.
Date
8/15/02
11/05/02
11/06/02
1/20/03
3/25/03
Updated Features to reflect T5A, 3.3V AC Characteristics (see below).
Adjusted Ref. Frequency Range and Frequency columns.
Changed IDD max. from 150mA to 175mA, IDDA max. from 50mA to 55mA, and
IDDO max. from 330mA to 25mA.
Changed fMAX from 183.3MHz max. to 166.67MHz max.
Changed RMS tjit(per) from 20ps max. to 17ps max.
Features Section - added Lead-Free bullet.
Added Crystal Section.
Ordering Information Table - added Lead-Free/Annealed Part Number.
10
11
14
Ordering Information Table - added Lead-Free Part Number.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Crystal Characteristics Table - added Drive Level.
Power Supply Filtering Techniques - corrected last sentence in the paragraph to
read “”Figure 1 illustrates how a ferrite bead along...”” from
“”Figure 1 illustrates how a 10W resistor along...””.
Corrected Power Supply Filtering diagram.
Added Recommendations for Unused Input and Output Pins.
Corrected Schematic Example diagram.
Ordering Information Table - added Lead-Free note.
D
T10
REVISION HISTORY SHEET
Description of Change
Pin Description Table, revised Master Reset description.
Pin Description Table, pin 43 should be labeled at a PULLUP instead of a PULLDOWN.
4/10/03
8/2/04
8/7/04
1/13/06
E
T10
14
16
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
7/26/10
E
T10
14
Ordering Information - removed leaded devices PDN CQ-13-02
2/18/15
REVISION E 2/18/15
15
LOW VOLTAGE, LOW SKEW,
PCI / PCI-X CLOCK GENERATOR
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6024 Silver Creek Valley Road
San Jose, California 95138
Sales
800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
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