87946AYILF

87946I 1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 3.3V Fanout Buffer Datasheet PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017 General Description Features The 87946I is a low skew, ÷1, ÷2 LVCMOS Fanout Buffer. The 87946I has two selectable single ended clock inputs. The 87946I has two selectable single ended clock inputs. The single ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. • • • Ten single-ended LVCMOS outputs, 7 typical output impedance • • • • • • Maximum input/output frequency: 150MHz The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. Selectable CLK0 and CLK1 LVCMOS clock inputs CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL Output skew: 350ps (maximum) 3.3V input, 3.3V outputs -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package For drop-in replacement use 87946i-147 The 87946I is characterized at 3.3V core/3.3V output. Guaranteed output and part-to-part skew characteristics make the 87946I ideal for those clock distribution applications demanding well defined performance and repeatability. Pin Assignment Block Diagram 32 31 30 29 28 27 26 25 DIV_SELA Pulldown 3 QB[0:2] 1 DIV_SELB Pulldown GND VDD 2 23 QB0 CLK0 3 22 VDDB CLK1 4 21 QB1 DIV_SELA 5 20 GND DIV_SELB 6 19 QB2 DIV_SELC 7 18 VDDB GND 8 17 VDDC 9 10 11 12 13 14 15 16 QC3 GND QC2 QC[0:3] 1 QC1 4 VDDC 0 24 GND 0 1 QC0 1 CLK_SEL VDDC ÷2 QA2 1 VDDA 3 QA[0:2] CLK1 Pullup QA1 0 GND ÷1 QA0 0 VDDA CLK0 Pullup GND MR/nOE CLK_SEL Pulldown 87946I DIV_SELC Pulldown 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View MR/nOE Pulldown ©2016 Integrated Device Technology, Inc 1 Revision C, September 20, 2016 87946I Datasheet Table 1. Pin Descriptions Number Name Type Description 1 CLK_SEL Input 2 VDD Power 3, 4 CLK0, CLK1 Input Pullup 5 DIV_SELA Input Pulldown Controls frequency division for Bank A outputs. LVCMOS/LVTTL interface levels. 6 DIV_SELB Input Pulldown Controls frequency division for Bank B outputs. LVCMOS/LVTTL interface levels. 7 DIV_SELC Input Pulldown Controls frequency division for Bank C outputs. LVCMOS/LVTTL interface levels. 8, 11, 15, 20, 24, 27, 31 GND Power 9, 13, 17 VDDC Power Positive supply pins for Bank C outputs. 10, 12, 14, 16 QC0, QC1, QC2, QC3 Output Bank C clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 18, 22 VDDB Power Positive supply pins for Bank B outputs. 19, 21, 23 QB2, QB1, QB0 Output Bank B clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 25, 29 VDDA Power Positive supply pins for Bank A outputs. 26, 28, 30 QA2, QA1, QA0 Output Bank A clock outputs. LVCMOS/LVTTL interface levels. 7 typical output impedance. 32 MR/nOE Input Pulldown Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. LVCMOS/LVTTL clock inputs. Power supply ground. Pulldown Master reset and output enable. When LOW, output drivers are enabled. When HIGH, output drivers are in High-Impedance and dividers are reset. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor Test Conditions RPULLDOWN Input Pulldown Resistor CPD Power Dissipation Capacitance (per output); NOTE 1 ROUT Output Impedance VDD, VDDX = 3.6V Minimum Typical Maximum Units 4 pF 51 k 51 k 25 pF 7  NOTE 1: VDDx denotes VDDA, VDDB, VDDC. © 2016 Integrated Device Technology, Inc 2 Revision C, September 20, 2016 87946I Datasheet Table 3. Function Table Inputs Outputs MR/nOE DIV_SELA DIV_SELB DIV_SELC QA0:QA2 QB0:QB2 QC0:QC3 1 X X X High-Impedance High-Impedance High-Impedance 0 0 X X fIN/1 Active Active 0 1 X X fIN/2 Active Active 0 X 0 X Active fIN/1 Active 0 X 1 X Active fIN/2 Active 0 X X 0 Active Active fIN/1 0 X X 1 Active Active fIN/2 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VDD -0.5V to VDD + 0.5V Outputs, VDD -0.5V to VDDX+ 0.5V Package Thermal Impedance, JA 47.9C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = VDDX = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.0 3.3 3.6 V VDDX Output Supply Voltage; NOTE 1 3.0 3.3 3.6 V IDD Power Supply Current 85 mA NOTE 1: VDDX denotes VDDA, VDDB, VDDC. ©2016 Integrated Device Technology, Inc 3 Revision C, September 20, 2016 87946I Datasheet Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDX = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE 2 VDD + 0.3 V CLK0, CLK1 2 VDD + 0.3 V DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE -0.3 0.8 V CLK0, CLK1 -0.3 1.3 V DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE VDD = VIN = 3.6V 120 µA CLK0, CLK1 VDD = VIN = 3.6V 5 µA DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE VDD = 3.6V, VIN = 0V -5 µA CLK0, CLK1 VDD = 3.6V, VIN = 0V -120 µA 2.5 V VOH Output High Voltage IOH = -20mA VOL Output Low Voltage IOH = 20mA © 2016 Integrated Device Technology, Inc 4 0.4 V Revision C, September 20, 2016 87946I Datasheet AC Electrical Characteristics Table 5. AC Characteristics, VDD = VDDX = 3.3V ± 0.3V, TA = -40°C to 85°C Symbol Parameter fIN Input Frequency tpLH Propagation Delay Low to High; NOTE 1 tpHL Propagation Delay High to Low; NOTE 1 tsk(o) Output Skew; NOTE 2, 6 Test Conditions Minimum Typical Maximum Units 150 MHz 2 12 ns 2.0 11.5 ns 350 ps fMAX < 100MHz 350 ps fMAX > 100MHz 450 ps 4.5 ns 1.0 ns tsk(w) Multiple Frequency Skew; NOTE 3, 6 tsk(pp) Part-to-Part Skew; NOTE 4, 6 tR / tF Output Rise/Fall Time; NOTE 5 tEN Output Enable Time; NOTE 5 11 ns tDIS Output Disable Time; NOTE 5 11 ns 0.8V to 2.0V 0.1 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: VDDX denotes VDDA, VDDB, VDDC. NOTE 1: Measured from VDD/2 of the input to VDDX/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDX/2. NOTE 3: Defined as skew across banks of outputs operating at different frequencies with the same supply voltage and equal load conditions. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDX/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65. ©2016 Integrated Device Technology, Inc 5 Revision C, September 20, 2016 87946I Datasheet Parameter Measurement Information 1.65V ± 0.15V V SCOPE VDD, VDDA, VDDB, VDDC DDx Qx 2 Qx V DDx Qy 2 tsk(o) GND -1.65V ± 0.15V 3.3V Output Load AC Test Circuit Output Skew Par t 1 V QBx, QCx DDx Qx 2 Par t 2 V DDx QAx Qy tsk(ω) Multiple Frequency Skew 2 tsk(pp) Part-to-Part Skew VDDx 2 CLK0, CLK1 2V QAx, QBx, QCx VDDx 2 QAx, QBx, QCx t 2V 0.8V 0.8V tR tF PD Propagation Delay © 2016 Integrated Device Technology, Inc Output Rise/Fall Time 6 Revision C, September 20, 2016 87946I Datasheet Application Information Recommendations for Unused Input and Output Pins Inputs: Outputs: CLK Inputs LVCMOS Outputs For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. All unused LVCMOS output can be left floating. There should be no trace attached. LVCMOS Control Inputs All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. Reliability Information Table 6. JA vs. Air Flow Table JA vs. Air Flow (Linear Feet per Minute) Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 55.9°C/W 50.1°C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 42.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for 87946I is: 1204 ©2016 Integrated Device Technology, Inc 7 Revision C, September 20, 2016 87946I Datasheet Package Outline and Package Dimensions Package Outline - Y Suffix for 32 Lead LQFP Table 7. Package Dimensions for 32 Lead LQFP JEDEC Variation: All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75  0° 7° ccc 0.10 Reference Document: JEDEC Publication 95, MS-026 © 2016 Integrated Device Technology, Inc 8 Revision C, September 20, 2016 87946I Datasheet Ordering Information Table 8. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 87946AYILF ICS87946AYIL “Lead-Free” 32 Lead LQFP Tray -40C to 85C 87946AYILFT ICS87946AYIL “Lead-Free” 32 Lead LQFP Tape & Reel -40C to 85C ©2016 Integrated Device Technology, Inc 9 Revision C, September 20, 2016 87946I Datasheet Revision History Sheet Rev Table Page A T1 1 2 6 Features section added Max Input/Output frequency bullet. Revised MR/nOE description. Revised Output Rise & Fall time diagram 8/14/02 B T5 4 AC Characteristics Table changed: (CLK0, CLK1) TPLH from 6.0ns max. to 12.0ns max, deleted typical value (CLK0, CLK1) TPHL from 6.0ns max. to 11.5ns max, deleted typical value 10/22/02 T5 5 3/17/10 T8 6 7 8 9 AC Characteristics Table - changed symbol fOUT to fIN. Moved 150MHz min. to max. column. Added Thermal Note. Corrected NOTE 2. Updated parameter Measurement Information section. Added Recommendations for Unused Input and Output Pins section. Updated Package Outline drawing. Ordering Information Table - deleted ICS prefix from Part/Order Number column. Added lead-free marking. 1 Deleted HiperClocks logo from General Description. Update Header / Footer of the datasheet. 6/22/12 T8 9 Ordering Information - removed leaded devices, PDN CQ-13-02. Updated data sheet format. 2/18/15 T8 9 Ordering Information - Deleted LF note below table. Product Discontinuation Notice - Last time buy expires May 6, 2017. PDN CQ-16-01 Updated header and footer. 6/28/16 Corrected datasheet title. Corrected General Description, first sentence from Clock Generator to Fanout Buffer. 9/20/16 B B B B 1 C Description of Change © 2016 Integrated Device Technology, Inc Date 10 Revision C, September 20, 2016 87946I Datasheet Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved. ©2016 Integrated Device Technology, Inc 11 Revision C, September 20, 2016 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.