87950I
Low Skew, 1-to-9
LVCMOS / LVTTL Clock Multiplier
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES NOVEMBER 2, 2016
GENERAL DESCRIPTION
FEATURES
The 87950I is a low voltage, low skew 1-9 LVCMOS/LVTTL
Clock Generator. With output frequencies up to 250MHz the
87950I is targeted for high performance clock applications.
Along with a fully integrated PLL the 87950I contains frequency
configurable outputs.
• Fully integrated PLL
DATA SHEET
• 9 single ended 3.3V LVCMOS/LVTTL outputs
• Selectable CLK or single ended crystal inputs
• Maximum output frequency: 250MHz
• Maximum VCO range: 240MHz to 500MHz
• Cycle-to-cycle jitter: ±100 (typical)
PIN ASSIGNMENT
• 3.3V operating supply
GND
QB
VDDO
QA
GND
CLK
PLL_SEL
CLK_SEL
• Output skew: 375ps (maximum) all outputs @ same frequency
• -40°C to 85°C ambient operating temperature
32 31 30 29 28 27 26 25
VDDA
1
24
QC0
• Available in lead-free (RoHS 6) package
FBDIV_SEL
2
23
VDDO
DIV_SELA
3
22
QC1
• For functional replacement part use 87973i
21
GND
20
QD0
19
VDDO
18
QD1
17
GND
DIV_SELB
4
DIV_SELC
5
DIV_SELD
6
GND
7
XTAL_IN
8
87950I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
9 10 11 12 13 14 15 16
QD2
VDDO
QD3
GND
QD4
VDDO
MR/nOE
XTAL_OUT
BLOCK DIAGRAM
DIV_SELA Pulldown
Pulldown
PLL_SEL
CLK Pulldown
Pulldown
CLK_SEL
1
÷2
0
XTAL_IN
XTAL_OUT
OSC
PHASE
DETECTOR
VCO
240-500MHz
0
0
QA
÷4
1
÷8
1
0
LPF
÷8/÷16
FBDIV_SEL Pulldown
DIV_SELB Pulldown
QB
1
0
1
QC0
QC1
DIV_SELC Pulldown
MR/nOE Pulldown
QD0
Power-On Reset
0
1
QD1
QD2
QD3
DIV_SELD Pulldown
QD4
REVISION C 11/6/15
1
©2015 Integrated Device Technology, Inc.
87950I DATA SHEET
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
1
VDDA
Power
2
FBDIV_SEL
Input
Pulldown
3
DIV_SELA
Input
Pulldown
4
DIV_SELB
Input
Pulldown
5
DIV_SELC
Input
Pulldown
6
DIV_SELD
Input
Pulldown
7, 13, 17,
21, 25, 29
8,
9
GND
Power
XTAL_IN, XTAL_
OUT
Input
10
MR/nOE
Input
11, 15, 19,
VDDO
23, 27
12, 14,
QD4, QD3,
16, 18, 20 QD2, QD1, QD0
Power
Output
22, 24
QC1, QC0
Output
26
QB
Output
28
QA
Output
30
CLK
Input
31
PLL_SEL
Input
32
CLK_SEL
Input
Description
Analog supply pin.
Selects divide value for Bank feedback output as described in
Table 3E. LVCMOS / LVTTL interface levels.
Selects divide value for Bank A output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank B output as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank C outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Selects divide value for Bank D outputs as described in Table 3D.
LVCMOS / LVTTL interface levels.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Active High Master Reset. Active Low Output Enable. When logic HIGH,
the internal dividers are reset and the outputs are tri-stated (HiZ). When
Pulldown
logic LOW, the internal dividers and the outputs are enabled. LVCMOS /
LVTTL interface levels.
Output supply pins.
Bank D clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank B clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Bank A clock output. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Pulldown LVCMOS / LVTTL phase detector reference clock input.
Selects between the PLL and the reference clock as the input to the
Pulldown dividers. When HIGH, selects PLL. When LOW, selects the reference
clock. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK. When LOW,
Pulldown
selects XTAL_IN, XTAL _OUT. LVCMOS / LVTTL interface levels.
NOTE: refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pulldown
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
CPD
Power Dissipation Capacitance (per output)
RPULLDOWN
Input Pulldown Resistor
ROUT
Output Impedance
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
Test Conditions
Minimum
Typical
Maximum
4
VDDA, VDDO = 3.47V
5
2
Units
pF
25
pF
51
kΩ
7
12
Ω
REVISION C 11/6/15
87950I DATA SHEET
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
MR/nOE
QA
QB
QC0, QC1
QD0:QD4
1
HiZ
HiZ
HiZ
HiZ
0
Enabled
Enabled
Enabled
Enabled
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
CLK_SEL
PLL Input
0
Bypass
0
XTAL Oscillator
1
PLL
1
CLK
TABLE 3D. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE FOR FBDIV-SEL
Inputs
FBDIV_SEL
Function
1
÷8
0
÷16
REVISION C 11/6/15
3
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
TABLE 3E. PROGRAMMABLE OUTPUT FREQUENCY FUNCTION TABLE
Inputs
Outputs
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
QA
QB
QCx
QDx
0
0
0
0
VCO/2
VCO/4
VCO/4
VCO/4
0
0
0
1
VCO/2
VCO/4
VCO/4
VCO/8
0
0
1
0
VCO/2
VCO/4
VCO/8
VCO/4
0
0
1
1
VCO/2
VCO/4
VCO/8
VCO/8
0
1
0
0
VCO/2
VCO/8
VCO/4
VCO/4
0
1
0
1
VCO/2
VCO/8
VCO/4
VCO/8
0
1
1
0
VCO/2
VCO/8
VCO/8
VCO/4
0
1
1
1
VCO/2
VCO/8
VCO/8
VCO/8
1
0
0
0
VCO/4
VCO/4
VCO/4
VCO/4
1
0
0
1
VCO/4
VCO/4
VCO/4
VCO/8
1
0
1
0
VCO/4
VCO/4
VCO/8
VCO/4
1
0
1
1
VCO/4
VCO/4
VCO/8
VCO/8
1
1
0
0
VCO/4
VCO/8
VCO/4
VCO/4
1
1
0
1
VCO/4
VCO/8
VCO/4
VCO/8
1
1
1
0
VCO/4
VCO/8
VCO/8
VCO/4
1
1
1
1
VCO/4
VCO/8
VCO/8
VCO/8
TABLE 3F. INPUT REFERENCE VS. OUTPUT FREQUENCY RELATIONSHIP
Inputs
Outputs
FBDIV_SEL = 1
FBDIV_SEL = 0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
QA
QB
QCx
QDx
QA
QB
QCx
QDx
0
0
0
0
4x
2x
2x
2x
8x
4x
4x
4x
0
0
0
1
4x
2x
2x
x
8x
4x
4x
2x
0
0
1
0
4x
2x
x
2x
8x
4x
2x
4x
0
0
1
1
4x
2x
x
x
8x
4x
2x
2x
0
1
0
0
4x
x
2x
2x
8x
2x
4x
4x
0
1
0
1
4x
x
2x
x
8x
2x
4x
2x
0
1
1
0
4x
x
x
2x
8x
2x
2x
4x
0
1
1
1
4x
x
x
x
8x
2x
2x
2x
1
0
0
0
2x
2x
2x
2x
4x
4x
4x
4x
1
0
0
1
2x
2x
2x
x
4x
4x
4x
2x
1
0
1
0
2x
2x
x
2x
4x
4x
2x
4x
1
0
1
1
2x
2x
x
x
4x
4x
2x
2x
1
1
0
0
2x
x
2x
2x
4x
2x
4x
4x
1
1
0
1
2x
x
2x
x
4x
2x
4x
2x
1
1
1
0
2x
x
x
2x
4x
2x
2x
4x
1
1
1
1
2x
x
x
x
4x
2x
2x
2x
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
4
REVISION C 11/6/15
87950I DATA SHEET
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDDA + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
42.1°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDDA
Analog Supply Voltage
Test Conditions
3.135
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDDA
Analog Supply Current
15
mA
IDDO
Output Supply Current
115
mA
Maximum
Units
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
2
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
±120
µA
IIN
Input Current
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Test Conditions
Minimum
Typical
VDDA =VIN = 3.465V
2.6
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2.
TABLE 5. CRYSTAL CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical Maximum
Units
Fundamental
Frequency
15
40
MHz
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fREF
Input Reference Frequency; NOTE 1
Test Conditions
Minimum
15
Typical
Maximum
Units
62.5
MHz
NOTE 1: Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the
CLK input.
REVISION C 11/6/15
5
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
TABLE 7. AC CHARACTERISTICS, VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
÷4
125
MHz
÷8
62.5
MHz
÷2
fMAX
fVCO
Output Frequency
PLL VCO Lock Range
240
500
MHz
375
ps
QA fMAX < 150MHz
500
ps
QA fMAX > 150MHz
750
ps
10
mS
Same Frequency
T sk(o)
Output Skew;
NOTE 1, 4
Different Frequency
T jit(cc)
Cycle-to-Cycle Jitter; NOTE 2, 4
tL
PLL Lock Time; NOTE 4
t R / tF
Output Rise/Fall Time
tPW
Output Pulse Width; NOTE 3
tPZL, tPZH
tPLZ,, tPHZ
±100
0.8V to 2V
ps
0.1
1
ns
tPERIOD/2 - 1000
tPERIOD/2 + 1000
ps
Output Enable Time
6
ns
Output Disable Time
7
ns
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Jitter performance using Xtal inputs.
NOTE 3: Measured using CLK.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
6
REVISION C 11/6/15
87950I DATA SHEET
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
3.3V OUTPUT LOAD AC TEST CIRCUIT
t jit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT PULSE WIDTH/PERIOD
CYCLE-TO-CYCLE JITTER
OUTPUT RISE/FALL TIME
REVISION C 11/6/15
7
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The 87950I provides separate
power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDDO and VDDA should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each VDDA pin.
3.3V
VDDO
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The 87950I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
These same capacitor values will tune any 18pF parallel resonant crystal over the frequency range and other parameters
specified in this data sheet. The optimum C1 and C2 values can
be slightly adjusted for different board layouts.
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
ICS84332
FIGURE 2. CRYSTAL INPUT INTERFACE
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
8
REVISION C 11/6/15
87950I DATA SHEET
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 87950I is: 2674
REVISION C 11/6/15
9
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
N
MAXIMUM
32
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
10
REVISION C 11/6/15
87950I DATA SHEET
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
87950BYILF
ICS87950BYIL
87950BYILFT
ICS87950BYIL
32 Lead “Lead-Free” LQFP
tray
-40°C to 85°C
32 Lead “Lead-Free” LQFP
1000 tape & reel
-40°C to 85°C
NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
REVISION C 11/6/15
11
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
REVISION HISTORY SHEET
Rev
Table
Page
B
T5
T10
1
5
11
Features Section - added Lead-Free bullet.
Crystal Characteristics Table - added Drive Level.
Ordering Information Table - added Lead-Free part number and note.
Changed XTAL1/2 naming convention to XTAL_IN/_OUT throughout the datasheet.
6/14/05
B
T10
11
Ordering Information - Added Lead-Free Marking.
9/8/08
C
T10
11
13
11
C
C
T10
1
LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
Description of Change
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
Ordering Information - removed leaded devices, PDN CQ-13-02
Updated data sheet format
Product Discontinuation Notice - Last time buy expires November 2, 2016.
PDN# CQ-15-05.
12
Date
7/16/10
2/18/15
11/6/15
REVISION C 11/6/15
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800-345-7015 or +408-284-8200
Fax: 408-284-2775
www.IDT.com
Technical Support
email: clocks@idt.com
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