87952AYI-147LFT

Low Skew, 1-to-11 LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer ICS87952I-147 DATA SHEET GENERAL DESCRIPTION FEATURES The ICS87952I-147 is a low voltage, low skew ICS LVCMOS/LVTTL Clock Generator and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from IDT. With output frequencies up to 180MHz, the ICS87952I-147 is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87952I-147 contains frequency configurable outputs and an external feedback input for regenerating clocks with “zero delay”. • Fully integrated PLL • Eleven LVCMOS / LVTTL outputs, 7Ω typical output impedance • LVCMOS / LVTTL REF_CLK input • Output frequency range up to 180MHz at VDD = 3.3V ± 5% • VCO range: 240MHz - 480MHz • External feedback for “zero delay” clock regeneration • Cycle-to-cycle jitter: 100ps (maximum) For test and system debug purposes, the nPLL_EN input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state. • 3.3V supply voltage • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages The low impedance LVCMOS/LVTTL outputs of the ICS87952I147 are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines. 1 FB_IN LFP VCO_SEL GNDO QA3 VDDO QB2 26 15 QA2 QA2 QB3 27 14 QA1 QA3 GNDO 28 13 GNDO QA4 GNDO 29 12 QA0 QC0 30 11 VDD QC1 31 10 VDDA VDDO 32 9 F_SELA ÷4/÷2 QB0 QB1 F_SELB ICS87952I-147 1 2 3 4 5 6 7 nPLL_EN 8 ÷2/÷4 QC0 QC1 FB_IN GNDI REF_CLK QB2 QB3 F_SELC QA4 16 QA1 MR/nOE ÷2 25 F_SELA 0 VDDO F_SELB VCO 240 - 480MHz QA0 F_SELC ÷4/÷6 PHASE DETECTOR VDDO 24 23 22 21 20 19 18 17 0 VCO_SEL 1 REF_CLK VDDO GNDO nPLL_EN QB0 PIN ASSIGNMENT QB1 BLOCK DIAGRAM 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y package Top View MR/nOE ICS87952AYI-147 REVISION C AUGUST 4, 2009 1 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCO_SEL Input Type 2 F_SELC Input 3 F_SELB Input 4 F_SELA Input 5 MR/nOE Input Description Pulldown VCO select input. LVCMOS / LVTTL interface levels. Determines output divider values for Bank C as described in Table 3A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank B as described in Table 3A. Pulldown LVCMOS / LVTTL interface levels. Determines output divider values for Bank A as described in Table 3A. Pulldown LVCMOS / LVTTL interface levels. Active High Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are in Hi-Z. Pulldown When logic LOW, the internal dividers and the outputs are enabled. Reset not required on power-up. LVCMOS / LVTTL interface levels. Pulldown Reference clock input. LVCMOS / LVTTL interface levels. 6 REF_CLK Input 7 GNDI Power 8 FB_IN Input 9 nPLL_EN Input 10 VDDA Power 11 12, 14, 15, 18, 19 13, 17, 24, 28, 29 16, 20, 21, 25, 32 22, 23, 26, 27 VDD QA0, QA1, QA2, QA3, QA4 Power 30, 31 Internal power supply ground. Feedback input to phase detector for generating clocks with Pulldown "zero delay". LVCMOS / LVTTL interface levels. PLL select input. Selects between REF_CLK and the PLL. Pulldown When HIGH, selects REF_CLK. When LOW, selects PLL. LVCMOS / LVTTL interface levels. Analog supply pin. Core supply pin. Bank A clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Output GNDO Power Output power supply ground. VDDO Power Output supply pins. QB0, QB1, QB2, QB3 Output QC0, QC1 Output Bank B clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 kΩ 25 pF 7 Ω CPD ROUT VDD, VDDO = 3.465V TABLE 3A. F_SELX CONTROL INPUT FUNCTION TABLE TABLE 3B. VCO_SEL CONTROL SELECT FUNCTION TABLE Input Output Input Output Input Output Control Input Logic 0 Logic 1 F_SELA QA0:QA4 F_SELB QB0:QB3 F_SELC QC0:QC1 VCO_SEL fVCO fVCO/2 0 ÷4 0 ÷4 0 ÷2 MR/nOE Output Enable High-Impedance 1 ÷6 1 ÷2 1 ÷4 nPLL_EN Enable PLL Disable PLL ICS87952AYI-147 REVISION C AUGUST 4, 2009 2 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD VDDA Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 V 160 mA 20 mA Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 12 0 µA VDDO Output Supply Voltage IDD Power Supply Current IDDA Analog Supply Current Test Conditions 15 TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL VOH Input Low Voltage REF_CLK, Input MR/nOE, FB_IN, VCO_SEL, High Current F_SELA:F_SELC, nPLL_EN REF_CLK, Input MR/nOE, FB_IN, VCO_SEL, Low Current F_SELA:F_SELC, nPLL_EN Output High Voltage VOL Output Low Voltage IIH IIL Test Conditions Minimum Typical VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -120 IOH = -20mA 2.4 µA V IOL = 20mA 0.5 V Maximum Units 100 MHz TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Input Reference Frequency NOTE: Input reference frequency is limited by fREF the divider selection and the VCO lock range. ICS87952AYI-147 REVISION C AUGUST 4, 2009 Test Conditions 3 Minimum Typical ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 6. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Maximum Output Frequency (PLL Mode) tPD fVCO Test Conditions MHz 120 MHz 80 MHz REF_CLK = 50MHz -100 200 ps 240 480 MHz 150 ps Within QA Bank 100 ps Within QB Bank 100 ps Cycle-to-Cycle Jitter; NOTE 3 All Outputs tjit(per) Period Jitter All Outputs tL PLL Lock Time t R / tF Output Rise/Fall Time Units 180 Any Frequency Within QC Bank tjit(cc) Maximum QC, QB (÷2) QA (÷6) Propagation Delay, REF_CLK to FB_IN Delay, (Static Phase Offset); NOTE 1 PLL VCO Lock Range Output Skew; NOTE 2, 3 Typical QA, QB, QC (÷4) All Outputs tsk(o) Minimum Output Frequencies Mixed Same Frequency Input Frequency = 20MHz, QAx = FB_IN = 20MHz, QBx = QCx = 30MHz, VCO_SEL = Logic 1 (÷2), F_SELA = Logic 1 (÷6), F_SELB = Logic 0 (÷4), F_SELC = Logic 1 (÷4) Output Frequencies Mixed Same Frequency 0.8V to 2.0V 0.10 50 ps 400 100 ps ps 250 ps 450 100 ps ps 10 ms 1.0 ns tPLZ, tPHZ Output Disable Time 1.5 8 ns tPZL Output Enable Time 2 10 ns o dc Output Duty Cycle 47 53 % 50 NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditons. NOTE: All parameters measured at fMAX unless noted otherwise. NOTE: All outputs loaded at 50Ω to VDDO/2. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. ICS87952AYI-147 REVISION C AUGUST 4, 2009 4 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V±5% SCOPE VDD, VDDO V DDO Qx 2 Qx LVCMOS V DDO Qy GND 2 tsk(o) -1.65V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW VOH V DDO 2 DDO 2 ➤ tcycle n ➤ VREF V V DDO ➤ QAx, QBx, QCx 2 tcycle n+1 VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements ➤ tjit(cc) = tcycle n – tcycle n+1 1000 Cycles Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) PERIOD JITTER CYCLE-TO-CYCLE JITTER VDD 2 REF_CLK 2V QAx, QBx, QCx VDDO 2 FB_IN t 0.8V 0.8V tR tF PD REF_CLK TO FB_IN DELAY QAx, QBx, QCx 2V OUTPUT RISE/FALL TIME VDDO VDDO VDDO 2 2 2 t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD ICS87952AYI-147 REVISION C AUGUST 4, 2009 5 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS87952I-147 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01µF 10Ω .01µF 10µF VDDA FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS87952AYI-147 REVISION C AUGUST 4, 2009 LVCMOS OUTPUTS All unused LVCMOS output can be left floating. There should be no trace attached. 6 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER LAYOUT GUIDELINE The schematic of the ICS87952I-147 layout example is shown in Figure 2A. This layout example is used as a general guideline. The layout in the actual system will depend on the selected com- ponent types, the density of the components, the density of the traces, and the stack up of the P.C. board. R1 43 Zo = 50 Receiv er VDD U1 VDDO QC1 QCO GNDO GNDO QB3 QB2 VDDO R4 1K 32 31 30 29 28 27 26 25 VDDO VDD Ro ~ 7 Ohm Zo = 50 R3 43 1 2 3 4 5 6 7 8 VCO_SEL F_SELC F_SELB F_SELA MR/nOE REF_CLK GNDI FB_IN nPLL_EN VDDA VDD QA0 GNDO QA1 QA2 VDDO F_SELC F_SELB F_SELA Q1 Driv er_LVCMOS ICS87952 R7 10 - 15 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 VDD GNDO QB1 QB0 VDDO VDDO QA4 QA3 GNDO Logic Input Pin Examples RU1 1K Set Logic Input to '0' VDD RU2 Not Install To Logic Input pins RD1 Not Install Zo = 50 C16 10u C11 0.01u VDD Set Logic Input to '1' VDD R2 43 R5 1K Receiv er C1 0.1u To Logic Input pins VDD=3.3V (U1-16) VDD (U1-20) (U1-21) (U1-25) (U1-32) RD2 1K C2 0.1uF C3 0.1uF C4 0.1uF C5 0.1uF C6 0.1uF FIGURE 2A. ICS87952I-147 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER SCHEMATIC EXAMPLE ICS87952AYI-147 REVISION C AUGUST 4, 2009 7 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER The following component footprints are used in this layout example: cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. All the resistors and capacitors are size 0603. POWER AND GROUNDING Place the decoupling capacitors as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • The 50Ω output traces should have same length. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the trans mission lines. • Keep the clock traces on the same layer. Whenever pos sible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic imped ance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VDDA pin as possible. CLOCK TRACES AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can • The series termination resistors should be located as close to the driver pins as possible. 50 Ohm Trace GND VDD R1 C6 VIA C5 Other signals U1 Pin 1 C4 C3 C2 VCCA R2 R7 C16 C11 C1 50 Ohm Trace FIGURE 2B. PCB BOARD LAYOUT FOR ICS87952I-147 ICS87952AYI-147 REVISION C AUGUST 4, 2009 8 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W 200 500 42.1°C/W 39.4°C/W TRANSISTOR COUNT The transistor count for ICS87952I-147 is: 2882 Compatible with MPC952, MPC9352, MPC93R52 ICS87952AYI-147 REVISION C AUGUST 4, 2009 9 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC 0.75 L 0.45 0.60 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 ICS87952AYI-147 REVISION C AUGUST 4, 2009 10 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 87952AYI-147 ICS87952AI147 32 Lead LQFP tray -40°C to 85°C 87952AYI-147T ICS87952AI147 32 Lead LQFP 1000 tape & reel -40°C to 85°C 87952AYI-147LF ICS7952AI147L 32 Lead "Lead-Free" LQFP tray -40°C to 85°C 87952AYI-147LFT ICS7952AI147L 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS87952AYI-147 REVISION C AUGUST 4, 2009 11 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER REVISION HISTORY SHEET Rev Table Page B T6 T6 4 4 T9 11 C Description of Change Date AC Characteristics Table - tPD, deleted 0ps typical and deleted tPW row. AC Characteristics Table - added row to CC Jitter, 250ps max. Added Thermal NOTE. Ordering Information Table - deleted "ICS" prefix in Par t/Order Number column. Updated Header/Footer format throughout the datasheet. ICS87952AYI-147 REVISION C AUGUST 4, 2009 12 4/10/06 8/4/09 ©2009 Integrated Device Technology, Inc. ICS87952I-147 Data Sheet LOW SKEW, 1-TO-11 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER www.IDT.com 6024 Silver Creek Valley Road San Jose, CA 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Techical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.