Low Skew, 1-to-12 LVCMOS / LVTTL
Clock Multiplier/Zero Delay Buffer
87973
Data Sheet
GENERAL DESCRIPTION
FEATURES
The 87973 is a LVCMOS/LVTTL clock generator.
The 87973 has three selectable inputs and provides
fourteen LVCMOS/LVTTL outputs.
• Fully integrated PLL
The 87973 is a highly flexible device. The three selectable inputs (1 differential and 2 single ended inputs) are often used in
systems requiring redundant clock sources. Up to three
different output frequencies can be generated among the three
output banks.
• Selectable LVCMOS/LVTTL or differential CLK, nCLK inputs
• Fourteen LVCMOS/LVTTL outputs; twelve clock outputs,
one feedback, one sync
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. The output
frequency range is 8.33MHz to125MHz. The input frequency
range is 5MHz to 120MHz.
• Output frequency range: 8.33MHz to 125MHz
• VCO range: 200MHz to 480MHz
• Output skew: 550ps (maximum)
• Cycle-to-cycle jitter: ±100ps (typical)
• Full 3.3V supply voltage
The 87973 also has a QSYNC output which can by used for
system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications
where Bank A and Bank C are running at different frequencies,
and is particularly useful when they are running at non-integer
multiples of one another.
• -40°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package
• Compatible with PowerPC™ and Pentium™ Microprocessors
PIN ASSIGNMENT
Example Applications:
1. System Clock generator: Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
2. Line Card Multiplier: Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
3. Zero Delay buffer for Synchronous memory: Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory module with zero delay.
©2015 Integrated Device Technology, Inc
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87973 Data Sheet
BLOCK DIAGRAM
VCO_SEL
PLL_SEL
REF_SEL
CLK
1
nCLK
D
0
CLK0
0
CLK1
1
Q
0
PHASE
DETECTOR
1
VCO
LPF
CLK_SEL
EXT_FB
D
Q
SYNC
FRZ
QA0
SYNC
FRZ
QA1
SYNC
FRZ
QA2
SYNC
FRZ
QA3
SYNC
FRZ
QB0
SYNC
FRZ
QB1
SYNC
FRZ
QB2
SYNC
FRZ
QB3
FSEL_FB2
nMR/OE
D
POWER-ON
RESET
Q
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
D
Q
÷2, ÷4, ÷6, ÷8
FSEL_A0:1
FSEL_B0:1
FSEL_C0:1
FSEL_FB0:2
2
0
÷4, ÷6, ÷8, ÷10
÷2
2
2
D
Q
D
Q
QC0
SYNC
FRZ
QC1
SYNC
FRZ
QC2
SYNC
FRZ
QC3
QFB
1
SYNC PULSE
3
SYNC
FRZ
QSYNC
DATA GENERATOR
FRZ_CLK
FRZ_DATA
OUTPUT DISABLE
CIRCUITRY
12
INV_CLK
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87973 Data Sheet
SIMPLIFIED BLOCK DIAGRAM
nMR/OE
FSEL_A[0:1]
2
CLK
1
nCLK
CLK0
0
CLK1
1
0
CLK_SEL
PLL
VCO RANGE
200MHz - 480MHz
0
REF_SEL
÷2
QAx
÷4
÷6
÷8
÷12
0
EXT_FB
1
÷1
FSEL_
A1 A0
0 0
0 1
1 0
1 1
1
PLL_SEL
QA0
SYNC
FRZ
QA1
SYNC
FRZ
QA2
SYNC
FRZ
QA3
SYNC
FRZ
QB0
SYNC
FRZ
QB1
SYNC
FRZ
QB2
SYNC
FRZ
QB3
FSEL_B[0:1]
2
FSEL_
B1 B0
0 0
0 1
1 0
1 1
VCO_SEL
SYNC
FRZ
QBx
÷4
÷6
÷8
÷10
FSEL_C[0:1]
2
FSEL_
C1 C0
0 0
0 1
1 0
1 1
QCx
÷2
÷4
÷6
÷8
QC0
0
1
SYNC
FRZ
QC1
SYNC
FRZ
QC2
SYNC
FRZ
QC3
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
0
0
0
÷4
0
0
1
÷6
0
1
0
÷8
0
1
1 ÷10
1
0
0
÷8
1
0
1 ÷12
1
1
0 ÷16
1
1
1 ÷20
FRZ_CLK
FRZ_DATA
©2015 Integrated Device Technology, Inc
3
OUTPUT DISABLE
CIRCUITRY
QFB
SYNC
FRZ
QSYNC
December 7, 2015
87973 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
GNDI
Power
Type
Description
2
nMR/OE
Input
Pullup
3
FRZ_CLK
Input
Pullup
Clock input for freeze circuitry. LVCMOS / LVTTL interface levels.
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
4
FRZ_DATA
Input
Pullup
Configuration data input for freeze circuitry.
LVCMOS / LVTTL interface levels.
5, 26, 27
FSEL_FB2,
FSEL_FB1,
FSEL_FB0
Input
Pullup
Select pins control Feedback Divide value.
LVCMOS / LVTTL interface levels.
6
PLL_SEL
Input
Pullup
7
REF_SEL
Input
Pullup
8
CLK_SEL
Input
Pullup
9, 10
CLK0,CLK1
Input
Pullup
Reference clock inputs. LVCMOS / LVTTL interface levels.
11
CLK
Input
Pullup
Non-inverting differential clock input.
12
nCLK
Input
13
VDDA
Power
14
INV_CLK
Input
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL. LVCMOS / LVTTL interface levels.
Selects between CLK0 or CLK1 and CLK, nCLK inputs.
When HIGH, selects CLK, nCLK. When LOW, selects CLK0 or CLK1.
LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 and CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1. LVCMOS
/ LVTTL interface levels.
Pullup/
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Analog supply pin.
Pullup
Inverted clock select for QC2 and QC3 outputs.
LVCMOS / LVTTL interface levels.
15, 24, 30, 35,
39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
GNDO
Power
Power supply ground.
QC3, QC2,
QC1, QC0
Output
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
VDDO
Power
Output supply pins.
19, 20
FSEL_C1,
FSEL_C0
Input
25
QSYNC
Output
Synchronization output for Bank A and Bank C. Refer to Figure 1, Timing
Diagrams. LVCMOS / LVTTL interface levels.
Pullup
Select pins for Bank C outputs. LVCMOS / LVTTL interface levels.
28
VDD
Power
Core supply pins.
29
QFB
Output
Feedback clock output. LVCMOS / LVTTL interface levels.
31
EXT_FB
Input
32, 34,
36, 38
44, 46,
48, 50
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
52
VCO_SEL
40, 41
42, 43
Pullup
Extended feedback. LVCMOS / LVTTL interface levels.
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Input
Pullup
Select pins for Bank B outputs. LVCMOS / LVTTL interface levels.
Input
Pullup
Select pins for Bank A outputs. LVCMOS / LVTTL interface levels.
Output
Input
Pullup
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
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87973 Data Sheet
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
4
Maximum
pF
RPULLUP /
RPULLDOWN
Input Pullup/Pulldown Resistor
51
kW
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
VDD, VDDA, VDDO = 3.465V
5
7
Units
18
pF
12
W
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
Inputs
Outputs
Inputs
Outputs
FSEL_A1
FSEL_A0
QA
FSEL_B1
FSEL_B0
QB
FSEL_C1
FSEL_C0
QC
0
0
÷4
0
0
÷4
0
0
÷2
0
1
÷6
0
1
÷6
0
1
÷4
1
0
÷8
1
0
÷8
1
0
÷6
1
1
÷12
1
1
÷10
1
1
÷8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
0
0
0
÷4
0
0
1
÷6
0
1
0
÷8
0
1
1
÷10
1
0
0
÷8
1
0
1
÷12
1
1
0
÷16
1
1
1
÷20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin
Logic 0
Logic 1
VCO_SEL
VCO/2
VCO
REF_SEL
CLK0 or CLK1
CLK, nCLK
CLK_SEL
CLK0
CLK1
PLL_SEL
BYPASS PLL
Enable PLL
nMR/OE
Master Reset/Output Hi Z
Enable Outputs
INV_CLK
Non-Inverted QC2, QC3
Inverted QC2, QC3
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87973 Data Sheet
fVCO
1:1 MODE
QA
QC
QSYNC
2:1 MODE
QA
QC
QSYNC
3:1 MODE
QC(÷2)
QA(÷4)
QSYNC
3:2 MODE
QC(÷2)
QA(÷8)
QSYNC
4:1 MODE
QC(÷2)
QA(÷8)
QSYNC
4:3 MODE
QA(÷6)
QC(÷8)
QSYNC
6:1 MODE
QA(÷12)
QC(÷2)
QSYNC
FIGURE 1. TIMING DIAGRAMS
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87973 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
42.3°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VDD
VDDA
Test Conditions
Minimum
Typical
Maximum
Units
Core Supply Voltage
3.135
3.3
3.465
V
Analog Supply Voltage
2.935
3.3
3.465
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
IDDA
Analog Supply Current
All power pins
225
mA
20
mA
Maximum
Units
3.6
V
NOTE: Special thermal handling may be required in some configurations.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
VIH
Input High Voltage
Test Conditions
Minimum
Typical
2
VIL
Input Low Voltage
IIN
Input Current
VOH
Output High Voltage
IOH = -20mA
VOL
Output Low Voltage
IOL = 20mA
VPP
Peak-to-Peak Input Voltage; NOTE 1, 2
CLK, nCLK
VCMR
Common Mode Input Voltage; NOTE 1, 2
CLK, nCLK
0.8
V
±120
µA
2.4
V
0.5
V
0.3
1
V
VDD - 2V
VDD - 0.6V
V
Maximum
Units
CLK0, CLK1,
CLK, nCLK; NOTE 1
120
MHz
FRZ_CLK
20
MHz
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2. For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fIN
Input Frequency
Test Conditions
Minimum
Typical
NOTE 1: Input frequency depends on the feedback divide ratio to ensure “clock * Feedback Divide” is in the VCO range of
200MHz to 480MHz.
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87973 Data Sheet
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Output Frequency
Maximum
Units
÷2
125
MHz
÷4
120
MHz
÷6
80
MHz
÷8
60
MHz
CLK0
t(Ø)
Static Phase
Offset;
NOTE 1
CLK1
CLK,
nCLK
tsk(o)
Output Skew; NOTE 2
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 3, 4
fVCO
PLL VCO Lock Range
tLOCK
PLL Lock Time; NOTE 3
tR / tF
Output Rise/Fall Time; NOTE 3
tPW
Output Pulse Width
tPZL, tPZH
Output Enable Time; NOTE 3
tPLZ, tPHZ
Output Disable TIme; NOTE 3
QFB ÷8
Minimum
Typical
-70
130
330
ps
-130
70
270
ps
-225
-25
175
ps
550
ps
In Frequency = 50MHz
±100
200
0.8V to 2V
ps
480
MHz
10
mS
1.2
ns
tPERIOD/2 +
750
ps
2
10
ns
2
8
ns
0.15
tPERIOD/2 750
tPERIOD/2 ±
500
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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87973 Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
STATIC PHASE OFFSET (DIFFERENTIAL)
STATIC PHASE OFFSET (LVCMOS)
OUTPUT RISE/FALL TIME
tPW & tPeriod
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87973 Data Sheet
APPLICATION INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output
of 87973 (Except QC0 and QFB) can be individually frozen
(stopped in the logic “0” state) using a simple serial interface
to a 12 bit shift register. A serial interface was chosen to eliminate the need for each output to have its own Output Enable
pin, which would dramatically increase pin count and package
cost. Common sources in a system that can be used to drive
the 87973 serial interface are FPGA’s and ASICs.
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which
can be frozen has its own freeze enable bit in the 12 bit shift
register. The sequence is started by supplying a logic “0” start
bit followed by 12NRZ freeze enable bits. The period of each
FRZ_DATA bit equals the period of the FRZ_CLK signal. The
FRZ_DATA serial transmission should be timed so the 87973 can
sample each FRZ_DATA bit with the rising edge of the FRZ_CLK
©2015 Integrated Device Technology, Inc
signal. To place an output in the freeze state, a logic “0” must be
written to the respective freeze enable bit in the shift register. To
unfreeze an output, a logic “1” must be written to the respective
freeze enable bit. Outputs will not become enabled/disabled until
all 12 data bits are shifted into the shift register. When all 12 data
bits are shifted in the register, the next rising edge of FRZ_CLK
will enable or disable the outputs. If the bit that is following the
12th bit in the register is a logic “0”, it is used for the start bit of
the next cycle; otherwise, the device will wait and won’t start the
next cycle until it sees a logic “0” bit. Freezing and unfreezing of
the output clock is synchronous (see the timing diagram below).
When going into a frozen state, the output clock will go LOW
at the time it would normally go LOW, and the freeze logic will
keep the output low until unfrozen. Likewise, when coming out
of the frozen state, the output will go HIGH only when it would
normally go HIGH. This logic, therefore, prevents runt pulses
when going into and out of the frozen state.
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December 7, 2015
87973 Data Sheet
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 87973 providesseparate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω resistor
can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
10Ω
VDDA
.01μF
10 μF
FIGURE 3. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 4 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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87973 Data Sheet
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must mee
t the VPP and VCMR input requirements. Figures 5A to 5D show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 5A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
1.8V
3.3V
3.3V
3.3V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
HiPerClockS
Input
R2
50
R3
50
3.3V
Zo = 50 Ohm
R1
50
R2
50
FIGURE 5A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
3.3V
LVPECL
R3
125
FIGURE 5B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
R4
125
Zo = 50 Ohm
LVDS_Driv er
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
Zo = 50 Ohm
nCLK
Receiv er
R2
84
FIGURE 5C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 5D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should
be no trace attached.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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87973 Data Sheet
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
58.0°C/W
42.3°C/W
47.1°C/W
36.4°C/W
42.0°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for 87973 is: 8364
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87973 Data Sheet
PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BCC
MINIMUM
NOMINAL
N
MAXIMUM
52
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.22
0.32
0.38
c
0.09
--
0.20
D
12.00 BASIC
D1
10.00 BASIC
E
12.00 BASIC
E1
10.00 BASIC
e
0.65 BASIC
L
0.45
--
0.75
θ
0°
--
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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87973 Data Sheet
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
87973DYILF
ICS87973DYILF
52 Lead “Lead-Free” LQFP
tray
-40°C to 85°C
87973DYILFT
ICS87973DYILF
52 Lead “Lead-Free” LQFP
tape & reel
-40°C to 85°C
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87973 Data Sheet
REVISION HISTORY SHEET
Rev
Table
A
T1
B
Description of Change
4
Pin Description Table - added pins 20 and 21.
Block Diagram - added missing dividers to the Data Generator.
10/18/02
T4B
7
DC Characteristics table - updated VCMR values from GND + 1.5V min.,
VDD max. to VDD - 2V min., VDD - 0.6V max.
10/23/02
T1
4
Pin Description Table - corrected CLK Type to read Pullup from Pulldown.
T8
12
1
Revised Package Drawing. Corrected Package Dimensions table to correspond
with the Package Drawing.
Added LVTTL to title.
12
5
7
Corrected Package Outline to correspond with the Package Dimensions table.
Pin Characteristics - changed the CPD limit from 25pF typical to 18pf max.
Power Supply Table - changed the IDD limit from 215mA max. to 225mA max.
B
T2
T4A
T2
5
Application Information:
Added sections, “Power Supply Filtering Techniques” and
“Wiring the Differential Level...”
Added “Differential Clock Input Interface” section.
Pin Characteristics - changed CIN from 4pF max. to 4pF typical.
D
T4A
10
7
Corrected Freeze Data labeling on Figure 2A.
Power Supply Table - changed VDDA minimum from 3.135V to 2.935V.
D
T1
T2
D
T9
4
5
1
12
15
D
T9
Pin Characteristics Table - added Pullup/Pulldown to pin 12, nCLK.
Pin Characteristics Table - added to ROUT 5Ω min. and 12Ω max.
Features section - added lead-free bullet.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking and note.
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS”prefix from Part/Order Number column.
Added Contact Page.
Ordering Information - removed leaded devices, quantity for tape & reel and LF
suffix note.
Updated DS header and footer.
C
11
12
C
T9
D
Date
2
A
B
Page
15
17
15
©2015 Integrated Device Technology, Inc
16
9/9/02
11/18/02
12/10/02
3/21/03
5/7/03
6/27/03
7/9/03
5/19/06
8/15/10
12/7/15
December 7, 2015
87973 Data Sheet
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