89H24NT24G2ZCHLG

® IDT™ 89EB-LOGAN-19 Evaluation Board Manual (Evaluation Board: 18-692-001) February 2011 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2011 Integrated Device Technology, Inc. DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a Failure Analysis be performed. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc. Table of Contents ® Notes Description of the EB-LOGAN-19 Evaluation Board Introduction ..................................................................................................................................... 1-1 Board Features ............................................................................................................................... 1-2 Hardware ................................................................................................................................ 1-2 Software.................................................................................................................................. 1-2 Other....................................................................................................................................... 1-2 Revision History .............................................................................................................................. 1-2 Installation of the EB-LOGAN-19 Evaluation Board EB-LOGAN-19 Installation .............................................................................................................. 2-1 PCI Express Mezzanine and Edge Adapters.................................................................................. 2-1 Hardware Description ..................................................................................................................... 2-3 Reference Clocks............................................................................................................................ 2-4 Global Reference Input Clocks ............................................................................................... 2-4 Local Port Input Clocks........................................................................................................... 2-6 Power Sources ....................................................................................................................... 2-8 PCI Express Analog Power Voltage Regulator....................................................................... 2-8 PCI Express Digital Power Voltage Converter........................................................................ 2-8 PCI Express Transmitter Analog Voltage Converter .............................................................. 2-8 Core Logic Voltage Converter ................................................................................................ 2-8 3.3V I/O Voltage Regulator.....................................................................................................2-8 Power-up Sequence for PES24NT24G2 ................................................................................ 2-8 Heatsink Requirement .................................................................................................................... 2-9 Reset............................................................................................................................................... 2-9 Fundamental Reset ................................................................................................................ 2-9 Downstream Reset ................................................................................................................. 2-9 Stack Configuration ................................................................................................................ 2-9 Boot Configuration Vector............................................................................................................. 2-10 SMBus Interfaces.......................................................................................................................... 2-11 SMBus Slave Interface ......................................................................................................... 2-11 SMBus Master Interface ....................................................................................................... 2-12 JTAG Header ................................................................................................................................ 2-12 PCI Express Connectors............................................................................................................... 2-12 EB-LOGAN-19 Board Figure ........................................................................................................ 2-15 Software for the EB-LOGAN-19 Eval Board Introduction ..................................................................................................................................... 3-1 Device Management Software........................................................................................................ 3-1 Device Drivers................................................................................................................................. 3-1 Schematics Schematics ..................................................................................................................................... 4-1 89EB-LOGAN-19 Evaluation Board 1 February 16, 2011 IDT Table of Contents Notes 89EB-LOGAN-19 Evaluation Board 2 February 16, 2011 List of Tables ® Notes Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 Table 2.12 Table 2.13 Table 2.14 Table 2.15 Table 2.16 Table 2.17 89EB-LOGAN-19 Evaluation Board EB-LOGAN-19 Global Clock Select .................................................................................... 2-4 Clock Buffer Input Sources ................................................................................................. 2-5 Global Reference Input Clock Frequency Select ................................................................ 2-6 Onboard Clock Generator Frequency Select ......................................................................2-6 Onboard Reference Clock Generator Access Points ......................................................... 2-6 EB-LOGAN-23 Port 8 Clock Source Select ........................................................................ 2-6 EB-LOGAN-23 Port 16 Clock Source Select ......................................................................2-7 EB-LOGAN-19 Slot Clock Select ........................................................................................ 2-7 CLKMODE Selection PES24NT24G2 ................................................................................ 2-7 EPS12V 24-pin Power Connector - J69 ............................................................................. 2-8 Ports in Each Stack .......................................................................................................... 2-10 Boot Configuration Vector Signals .................................................................................... 2-10 Boot Configuration Vector Switch SW10 .......................................................................... 2-10 Slave SMBus Interface Connector .................................................................................... 2-11 SMBus Slave Interface Address Configuration ................................................................. 2-11 JTAG Connector Pin Out .................................................................................................. 2-12 PCI Express x8 Connector Pinout .................................................................................... 2-12 3 February 16, 2011 IDT List of Tables Notes 89EB-LOGAN-19 Evaluation Board 4 February 16, 2011 List of Figures ® Notes Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 2.9 89EB-LOGAN-19 Evaluation Board Function Block Diagram of the EB-LOGAN-19 Evaluation Board ......................................1-1 Bifurcated and Merged Mezzanine Cards ..........................................................................2-1 MiniSAS Mezzanine Adapter ............................................................................................2-2 EB-LOGAN-19 iSAS-to-SATA Breakout Cable ..................................................................2-2 PCIe x1 Edge-to-SATA Adapter ........................................................................................2-3 EB-LOGAN-19 Evaluation Main Board ..............................................................................2-3 12PACK PCIe Slots Breakout Daughter Board .................................................................2-4 Differential Jumper Arrangement .......................................................................................2-5 Reference Clock Configuration ..........................................................................................2-5 EB24NT24G2 Evaluation Board ......................................................................................2-15 5 February 16, 2011 IDT List of Figures Notes 89EB-LOGAN-19 Evaluation Board 6 February 16, 2011 Chapter 1 Description of the EB-LOGAN-19 Evaluation Board ® Notes Introduction The 89HPES24NT24G2 switch is a member of the IDT PCI Express® Inter-Domain Switch family of products. It is a PCIe® Base Specification 2.1 compliant (Gen2) 24-lane, 24-port switch. The EB-LOGAN19 Evaluation Board provides an evaluation platform for the PES24NT24G2 switch and for other members of this switch family including PES16NT16G2 and PES12NT12G2. Detailed information related to configuration of number of ports and lanes in the switch device can be found in the Device User Manual and the Device Datasheet. The evaluation board, along with additional adapters and daughter boards provided by IDT, can be configured to test every possible combination of the number of lanes and ports offered by the switch. Advanced capabilities such as switch partitioning, NTB, DMA and local port clocking can be evaluated with the evaluation board. The EB-LOGAN-19 brings out all 24 lanes of the device to two Mezzanine connectors and two SAS connectors (see Figure 1.1) located close to the device - one connector per stack of 4 lanes. Various types of daughter cards (provided by IDT) can then be plugged into the Mezzanine connectors to facilitate connectivity to one x8 or two x4 or four x2 or eight x1 link partners. Link partners may be plugged directly into these daughter cards or they can be connected to these daughter cards via SAS or SATA cables and a different board with PCIe slots known as the 12-PACK board (provided by IDT). Given that majority of the hosts / servers offer PCIe standard slots, IDT provides the necessary adapter cards that may be plugged into these host / server slots as well as the cables that connect such adapters to the daughter cards which in turn are plugged into the main evaluation board on which the IDT PCIe switch device is populated. The EB-LOGAN-19 is also used by IDT to reproduce system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EBLOGAN-19 board. Figure 1.1 Function Block Diagram of the EB-LOGAN-19 Evaluation Board 89EB-LOGAN-19 Evaluation Board 1-1 February 16, 2011 IDT Description of the EB-LOGAN-19 Evaluation Board Notes Board Features Hardware ‹ PES24NT24G2 PCIe 24-port switch – Twenty four ports (each x1) - for port 8 and higher, adjacent ports may be combined to create x2, x4 or x8 ports – PCIe Base Specification Revision 2.1 compliant (Gen2 SerDes speeds of 5 GT/S) – Up to 2048 byte maximum Payload Size – Automatic lane reversal and polarity inversion supported on all lanes – Automatic per port link width negotiation to x8, x4, x2, x1 – Power on reconfiguration via optional serial EEPROM connected to the SMBUS Master interface ‹ Upstream, Downstream Ports – The EB-LOGAN-19 has minimum of one port configured as upstream port to be plugged into a host slot through an adaptor and a cable. – Up to 23 ports can be configured as downstream ports, for PCIe endpoint add-on cards to be plugged in. The slot connectors can be configured to be x1, x2, x4 or x8, but are mechanically open-ended on one side to allow card widths greater than x8 (e.g. x16) to be populated. – When used in multi-partition mode, the device can be programmed through the serial EEPROM to generate the appropriate number of upstream and downstream ports per partition. ‹ Numerous user selectable configurations set using onboard jumpers and DIP-switches – Source of clock - host clock or onboard clock generator – Two clock rates (100/125 MHz) from an onboard clock generator – Flexible clocking modes • Common clock • Non-common clock • Local port clocking on ports that support this feature – Boot mode selection ‹ SMBUS Slave Interface (4 pin header) ‹ SMBUS Master Interface connected to the Serial EEPROMs through I/O expander ‹ Push button for Warm Reset ‹ Many LEDs to display status, reset, power, hotplug, etc. ‹ JTAG connector to the PES24NT24G2 JTAG pins. Software There is no software or firmware executed on the board. However, useful software is provided along with the Evaluation Board to facilitate configuration and evaluation of the PES24NT24G2 within host systems running popular operating systems. ‹ Installation programs – Operating Systems Supported: WindowsServer200x, WindowsXP, Vista, Linux GUI based application for Windows and Linux ‹ – Allows users to view and modify registers in the PES24NT24G2 – Binary file generator for programming the serial EEPROMs attached to the SMBUS. Other ‹ SMBUS cable may be required for certain evaluation exercises. ‹ SMA connectors are provided on the EB-LOGAN-19 board for clock outputs. Revision History April 13, 2010: Initial publication of evaluation board manual. 89EB-LOGAN-19 Evaluation Board 1-2 February 16, 2011 IDT Description of the EB-LOGAN-19 Evaluation Board Notes April 23, 2010: Updated Schematics in Chapter 4. August 18, 2010: Updated the manual for Rev. 2.0 board February 16, 2011: Changed default settings from Off to On in Tables 2.3 and 2.4. 89EB-LOGAN-19 Evaluation Board 1-3 February 16, 2011 IDT Description of the EB-LOGAN-19 Evaluation Board Notes 89EB-LOGAN-19 Evaluation Board 1-4 February 16, 2011 Chapter 2 Installation of the EB-LOGAN-19 Evaluation Board ® Notes EB-LOGAN-19 Installation This chapter discusses the steps required to configure and install the EB-LOGAN-19 evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1. Configure jumper/switch options suitable for the evaluation or application requirements. 2. Connect PCI Express endpoint cards to the downstream port PCIe slots on the evaluation board. 3. Make sure that the host system (motherboard with root complex chipset) is powered off. 4. Connect the evaluation board to the host system. 5. Apply power to the host system. The EB-LOGAN-19 board is typically shipped with all jumpers and switches configured to their default settings. In most cases, the board does not require further modification or setup however please visit IDT website and fill out the Technical Support Request form at http://www.idt.com/?app=TechSupport for other configurations. PCI Express Mezzanine and Edge Adapters The PCI Express lanes are broken out to four Mezzanine connectors on EB-LOGAN-19 Evaluation Board. The adapter cards are used to convert Mezzanine connector into PCI Express slot connector(s) or Internal mini SAS (iSAS) connectors or both. A Bifurcated Mezzanine Card has two mechanical x8 PCIe Slots (x4 electrically) while a Merged Mezzanine Card has single x8 PCIe Slot. Pictured in Figure 2.1. Figure 2.1 Bifurcated and Merged Mezzanine Cards 89EB-LOGAN-19 Evaluation Board 2-1 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Pictured in Figure 2.2 is the mini-SAS Mezzanine card which consists of two iSAS and two SATA connectors. Each iSAS connector supports up to PCI Express x4 width and the SATA connectors are used for clock and reset signals of each x4 or less stack/port. An iSAS-to-SATA breakout cable shown in Figure 2.3 is used connect from iSAS to edge adapter and/or 12PACK. Figure 2.2 MiniSAS Mezzanine Adapter SAS (x4) – four SATA (x1) breakout cable Figure 2.3 EB-LOGAN-19 iSAS-to-SATA Breakout Cable The PCI Express Edge to SATA Adapter, pictured in Figure 2.4, can be inserted into any physical PCIe slot on a host system and in combination with mini-SAS Mezzanine Card, such as the one in Figure 2.2, to form a link between evaluation main board and the host system. There are 5 SATA connectors which one connector (J7) is for clock and reset, and the rest supports one PICe lane per SATA connector. The edge adapters can be inserted into a mechanical x1 or greater slot. 89EB-LOGAN-19 Evaluation Board 2-2 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Figure 2.4 PCIe x1 Edge-to-SATA Adapter Hardware Description The PES24NT24G2 is a 24-lane, 24-port PCI Express® switch. It is a peripheral chip that performs PCI Express based switching with a feature set optimized for high performance applications such as servers and storage. It provides fan-out and switching functions between a PCI Express upstream port and downstream ports or peer-to-peer switching between downstream ports. Furthermore, up to eight ports can be configured as NTB ports for multi-root application. The EB-LOGAN-19 Main Board, shown in Figure 2.5, will support up to 4 PCI Express downstream ports and up to 23 ports when using two 12PACK Daughter Boards. Basic requirements for the board to run are: – Host system with a PCI Express root complex supporting x1 configuration through a PCI Express x1 slot. – – x1, x2, x4, or x8 PCI Express Endpoint Cards. DUT on bottom side Mezz to two x4 slot connectors x4 iSAS connectors Figure 2.5 EB-LOGAN-19 Evaluation Main Board 89EB-LOGAN-19 Evaluation Board 2-3 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes 8-P IN EPS 12V 24-PIN ATX +3.3 +12 +12 SMA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA clk[0:11] SATA SATA CLK CLK CLK CLK CLK CLK CLK CL K CLK CLK CL K CLK 1:12 Buffer On-Board Clock Gen SATA S A T A S A T A S A T A x2 Data S L O T 1 1 S A T A S A T A S A T A S A T A S A T A S L O T 1 0 x4 Data S A T A S L O T S A T A S A T A x2 Data S A T A S A T A S A T A S A T A S A T A 8 9 S A T A S L O T S A T A x8 Data S A T A S A T A S L O T S A T A S A T A 7 x2 Data S L O T S A T A 6 S A T A x4 Data S L O T S A T A S A T A x2 Data S L O T S A T A x8 Data S A T A S A T A S A T A S A T A S A T A S A T A S A T A 4 5 S A T A S A T A S L O T S A T A S A T A 3 x2 Data S L O T S A T A 2 S A T A x4 Data S L O T S A T A S A T A 1 S A T A x2 Data S A T A S L O T S A T A S A T A 0 S A T A S A T A x8 Data Figure 2.6 12PACK PCIe Slots Breakout Daughter Board Reference Clocks Global Reference Input Clocks The PES24NT24G2 requires two differential reference clocks. The EB-LOGAN-19 derives these clocks from SMA connectors (J17, J20, J66, J67), clock buffer (U50), or SATA connectors (J21, J22) as described in Table 2.1 and Figures 2.7 and 2.8. Both reference clocks are mandatory and must come from the same reference clock source. The switch will not function normally if only one clock is used. Global Clock# Jumper 0 J18 [1-3 / 2-4] SMA (J66/J67) [5-7 /6-8] From Clock Buffer U51 [7-9 / 8-10] SATA, J21 1 J19 [1-3 / 2-4] SMA (J17/J20) [5-7 /6-8] From Clock Buffer U51 [7-9 / 8-10] SATA, J22 Selection Table 2.1 EB-LOGAN-19 Global Clock Select 89EB-LOGAN-19 Evaluation Board 2-4 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes 1 2 3 4 5 6 7 8 9 10 11 12 IOA IOB IOC CONNECTION JMP1 JMP2 IOA COM 1-3 2-4 IOB COM 3-5 4-6 IOC COM 7-9 8-10 IOD COM 9-11 10-12 IOD Figure 2.7 Differential Jumper Arrangement Figure 2.8 Reference Clock Configuration By default the clock buffer derives its clock from a common source. The common source can be the host system’s reference clock, the onboard clock generator, or SATA connector (J8). See Table 2.2. . Jumper J6 Selection [1-3 / 2-4] SMA (J5/J7) [5-7 / 6-8] Onboard Clock Generator (U49) [7-9 / 8-10] SATA (J8) Table 2.2 Clock Buffer Input Sources The frequency of the global reference clock input may be selected by the Clock Frequency Select (GCLKFEL) pin to be either 100 MHz or 125 MHz as described in Table 2.3. 89EB-LOGAN-19 Evaluation Board 2-5 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Global Clock Frequency Switch - SW10[2 SW10[2] Clock Frequency ON 100 MHz (Default) OFF 125 MHz Table 2.3 Global Reference Input Clock Frequency Select The source for the onboard clock is the ICS841484 clock generator device (U49) connected to a 25MHz oscillator (X1). When using the onboard clock generator, the output frequency is fixed at 100MHz. Therefore, ICS_FS (S10, bit 1) is ON as the default setting. See Table 2.4. Onboard Clock Frequency Switch - S10[1] S10[1] Clock Frequency ON 100 MHz (Default) OFF 125 MHz Table 2.4 Onboard Clock Generator Frequency Select The output of the onboard clock generator is accessible through two yellow colored loop connectors located on the Evaluation Board. See Table 2.5. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source. Onboard Reference Clock Output (Differential) J119 Positive Reference Clock (SMA) J120 Negative Reference Clock (SMA) J121 Differential Reference Clock (SATA) Table 2.5 Onboard Reference Clock Generator Access Points Local Port Input Clocks Associated with some ports is a port reference clock input (PxCLK). Depending on the port clocking mode, a differential reference clock is driven into the device on the corresponding PxCLKP and PxCLKN pins. The frequency of a port reference clock input MUST always be 100 MHz. Table 2.6 and Table 2.7 list the possible sources for ports 8 and 16 reference clock input, and Table 2.8 lists the possible sources for the slot clock input. Additional information on port clocking usage and configuration can be found in the Device User Manuals and in IDT’s Application Note AN-715. Local port clock sources for ports 8 and 16 are selected by DIP Switch (S17 and S19) via clock mux/buffer. Port 8 Clock Source Select - S19[1] S19[1] Clock Source OFF SATA J62 ON Port 8 Clock Generator (U118) Table 2.6 EB-LOGAN-23 Port 8 Clock Source Select 89EB-LOGAN-19 Evaluation Board 2-6 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Port 16 Clock Source Select - S17[1] S17[1] Clock Source OFF SATA J64 ON Port 16 Clock Generator (U120) Table 2.7 EB-LOGAN-23 Port 16 Clock Source Select Slot # Header Selection 8 J31 [1-3 / 2-4] Onboard Clock Generator (U118) [3-5 / 4-6] From Clock Buffer [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J35) 12 J32 [1-3 / 2-4] P08CLK Clock Mux (U18) [3-5 / 4-6] From Clock Buffer [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J36) 16 J33 [1-3 / 2-4] P16CLK Clock Mux (U16) [3-5 / 4-6] From Clock Buffer [7-9 / 8-10] Onboard Clock Generator (U120) [9-11 / 10-12] SATA (J37) 20 J34 [1-3 / 2-4] P08CLK Clock Mux (U18) [3-5 / 4-6] From Clock Buffer [7-9 / 8-10] P16CLK Clock Mux (U16) [9-11 / 10-12] SATA (J38) Table 2.8 EB-LOGAN-19 Slot Clock Select CLKMODE Selection All ports in the PES24NT24G2 device (upstream and downstream) use global clocked mode. The port clocking mode of a port is determined by the state of the CLKMODE[1:0] pins in the boot configuration vector as shown in Table 2.9. This field determines the initial value of the Slot Clock Configuration (SCLK) field in each port’s PCI Express Link Status (PCIELSTS) register. The SCLK field controls the advertisement of whether or not the port uses the same reference clock source as the link partner. A one in the SCLK field indicates that the port and its link partner use the same reference clock source. This is defined as Common Clock Configuration by the PCI Express Base Specification. A zero in the SCLK field indicates that the port and its link partner do not use the same reference clock source. SW10[8] CLKMODE[0] SW10[7] CLKMODE[1] Port 0 SCLK Port[23:1] SCLK ON ON 0 0 OFF ON 1 0 ON OFF 0 1 OFF OFF 1 1 Table 2.9 CLKMODE Selection PES24NT24G2 89EB-LOGAN-19 Evaluation Board 2-7 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Power Sources Power for the PES24NT24G2 and all downstream ports will be generated from the 12V from an external power connector. See Table 2.10. A 12V to 3.3V DC-DC converter will be used to provide power to five switching regulators to generate VDDCORE, VDDPEA, VDDPETA, VDDPEHA, and VDDIO voltages. The 3.3V from the DC-DC converter will be used to power the clock buffers and circuitries. The external power supply connector is a 24-pin (J69) molex connector as described in Tables 2.10. Pin Signal Pin Signal 1 +3.3V 13 +3.3V 2 +3.3V 14 -12V 3 GND 15 GND 4 +5V 16 PS_ON 5 GND 17 GND 6 +5V 18 GND 7 GND 19 GND 8 PWR_OK 20 NC 9 5VSB 21 +5V 10 +12V3 22 +5V 11 +12V3 23 +5V 12 +3.3V 24 GND Table 2.10 EPS12V 24-pin Power Connector - J69 The power on switch located at S1 can be used to control the supply power from the external power supply connector. Add a shunt to W27 to enable power on switch. PCI Express Analog Power Voltage Regulator A voltage regulator (U65) provides a 2.5V PCI Express analog power voltage (shown as VDDPEHA) to the PES24NT24G2. PCI Express Digital Power Voltage Converter A separate voltage regulator (U62) provides a 1.0V PCI Express analog power voltage (shown as VDDPEA) to the PES24NT24G2. PCI Express Transmitter Analog Voltage Converter A separate voltage regulator (U68) provides a 1.0V PCI Express transmitter analog voltage (shown as VDDPETA) to the PES24NT24G2. Core Logic Voltage Converter A separate voltage regulator (U59) provides the 1.0V core voltage (VDDCORE) to the PES24NT24G2. 3.3V I/O Voltage Regulator A separate voltage regulator (U56) provides the 3.3V I/O voltage (VDDIO) to the PES24NT24G2. Power-up Sequence for PES24NT24G2 During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There are no other power-up sequence requirements for the various operating supply voltages. 89EB-LOGAN-19 Evaluation Board 2-8 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Heatsink Requirement The EB-LOGAN-19 evaluation board utilizes a heatsink with integrated fan. Reset The PES24NT24G2 supports two types of reset mechanisms as described in the PCI Express specification: – Fundamental Reset: This is a system-generated reset that propagates along the PCI Express tree through a single side-band signal PERST# which is connected to the Root Complex, the PES24NT24G2, and the endpoints. – Hot Reset: This is an In-band Reset, communicated downstream via a link from one device to another. Hot Reset may be initiated by software. This is further discussed in the PES24NT24G2 User Manual. The EB-LOGAN-19 evaluation board provides seamless support for Hot Reset. Fundamental Reset There are two types of Fundamental Resets which may occur on the EB-LOGAN-19 evaluation board: – Cold Reset: During initial power-on, the onboard voltage monitor (TLC7733D) will assert the PCI Express Reset (PERSTN) input pin of the PES24NT24G2. – Warm Reset: This is triggered by hardware while the device is powered on. Warm Reset can be initiated by two methods: • Pressing a push-button switch (S3) located on EB-LOGAN-19 board • The host system board IO Controller Hub asserting PERST# signal, which propagates through the PCIe upstream edge connector of the EB-LOGAN-19. Both events cause the onboard voltage monitor (TLC7733D) to assert the PCI Express Reset (PERSTN) input of the PES24NT24G2 while power is on. Downstream Reset Single Partition Mode without Hot Plug: When the evaluation board initially powers on is assumes the following: ‹ The switch is configured in single partition mode. ‹ Port 0 is the root port and controls the downstream port resets. ‹ Ports 1-23 are downstream ports. ‹ Hot Plug is disabled. The following behavior should be observed: ‹ The resets to slots 1-23 should initially be asserted and remain this way until after the fundamental reset is initially de-asserted. ‹ The assertion of a fundamental reset should propagate to slots 1-23. Stack Configuration The PES24NT24G2 contains four stack blocks labeled Stack 0, Stack 1, Stack 2, and Stack 3. Stacks 0 and 1 have four x1 ports each, and stacks 2 and 3 have eight x1 ports each. This provides a total of 24 ports in the device labeled port 0 through port 23. Table 2.11 lists the ports associated with each stack. Stacks 0 and 1 have non-mergeable x1 ports. Stacks 2 and 3 may be configured as eight x1 ports, four x2 ports, two x4 ports, one x8 port, and any combinations in between. The configuration of each stack is controlled by the Stack Configuration (STK[3:2]CFG) registers. For possible configurations please refer to the device user manual. 89EB-LOGAN-19 Evaluation Board 2-9 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Stack Ports Associated with the Stack Stack 0 0, 1, 2, 3 Stack 1 4, 5, 6, 7 Stack 2 8, 9, 10, 11, 12, 13, 14, 15 Stack 3 16, 17, 18, 19, 20, 21, 22, 23 Table 2.11 Ports in Each Stack Boot Configuration Vector A boot configuration vector consisting of the signals listed in Table 2.12 is sampled by the PES24NT24G2 during a fundamental reset (while PERSTN is active). The boot configuration vector defines the essential parameters for switch operation and is set using DIP switches S5, SW8, SW9 and SW10 as defined in Table 2.13. Signal GCLKFSEL Description Global Clock Frequency Select. This pin specifies the frequency of the GCLKP and GCLKN signals.. Default: low CLKMODE[1:0] Clock Mode. These pins specify the clocking mode used by switch ports. See Table 2.9 for a definition of the encoding of these signals. The value of these signals may be overridden by modifying the Port Clocking Mode (PCLKMODE) register. RSTHALT Reset Halt. When this pin is asserted during a switch fundamental reset sequence, the switch remains in a quasi-reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the quasi-reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. Refer to section Switch Fundamental Reset on page 3-2 for further details. Default: low SSMBADDR[2:1] Slave SMBus Address. SMBus address of the switch on the slave SMBus. Default: 0x3 SWMODE[3:0] Switch Mode. These pins specify the switch operating mode. STK2CFG[4:0] Stack 2 Configuration. These pins select the configuration of stack 2 during a switch fundamental reset. STK3CFG[4:0] Stack 3 Configuration. These pins select the configuration of stack 3 during a switch fundamental reset. Table 2.12 Boot Configuration Vector Signals Location Signal Default SW10[2] GCLKFSEL ON SW10[4] RSTHALT ON SW10[5] SSMBADDR[2] OFF SW10[6] SSMBADDR[1] OFF Table 2.13 Boot Configuration Vector Switch SW10 89EB-LOGAN-19 Evaluation Board 2 - 10 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes SMBus Interfaces The System Management Bus (SMBus) is a two-wire interface through which various system component chips can communicate. It is based on the principles of operation of I2C. Implementation of the SMBus signals in the PCI Express connector is optional and may not be present on the host system. The SMBus interface consists of an SMBus clock pin and an SMBus data pin. The PES24NT24G2 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface. The slave SMBus interface allows a SMBus Master device full access to all software-visible registers. The Master SMBus interface provides a connection to the external serial EEPROM used for initialization and the I/O expanders used for hot-plug signals. SMBus Slave Interface On the PES24NT24G2 board, the slave SMBus interface is accessible through a 4-pin header as described in Table 2.14. . Slave SMBus Interface Connector J71 Pin Signal 1 SDA 2 GND 3 SCL 4 NC Table 2.14 Slave SMBus Interface Connector For a fixed address, the SMBus address of the PES24NT24G2 slave interface is 0b1110111 by default and is configurable using DIP Switches SW10[5] and SW10[6] as described in Table 2.15. Slave Interface Address Configuration Address Bit Signal 1 SSMBUSADDR[1] 2 SSMBUSADDR[2] 3 1 4 0 5 1 6 1 7 1 Table 2.15 SMBus Slave Interface Address Configuration The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions: – Byte and Word Write/Read – Block Write/Read 89EB-LOGAN-19 Evaluation Board 2 - 11 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes SMBus Master Interface Connected to the master SMBus interface are twenty-two 16-bit I/O Expanders (MAX7311AUG) and a serial EEPROM, U77 (24LC512). The I/O Expanders are used as the interface for the onboard hot-plug controllers (MIC2591B). The lower three bits of the bus address for the I/O Expander 0 through I/O Expander 20 are fixed through the stuffing resistor as 0x20, 0x22, 0x24, 0x26, 0x28, 0x2A, 0x2C, 0x2E, 0x50, 0x52, x54, 0x56, 0x58, 0x5A, 0x5C, 0x5E, 0xB0, 0xA2, 0xA4, 0xA6, 0xA8, and 0xAA, respectively. Note: Hot-plug is not implemented when the PES24NT24G2 is installed. The seven bits address for the selected EEPROM device is fixed at 0b1010_000 by default. JTAG Header The EB-LOGAN-19 provides a JTAG connector J73 for access to the PES24NT24G2 JTAG interface. The connector is a 2.54 x 2.54 mm pitch male 14-pin connector. Refer to Table 2.16 for the JTAG Connector J73 pin out. JTAG Connector J73 Pin Signal Direction Pin Signal Direction 1 /TRST - Test reset Input 2 GND — 3 TDI - Test data Input 4 GND — 5 TDO - Test data Output 6 GND — 7 TMS - Test mode select Input 8 GND — 9 TCK - Test clock Input 10 GND — 11 3.3V 12 N/C — 13 GND 14 3.3V — Table 2.16 JTAG Connector Pin Out PCI Express Connectors Pin Side A Side B 1 +12V 12V power PRSNT1# 2 +12V 12V power +12V 12V power 3 RSVD Reserved +12V 12V power 4 GND Ground GND Ground 5 SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p 6 SMDAT SMBus Data JTAG TDI (Test Data Input) 7 GND Ground JTAG TDO (Test Data Output) 8 +3.3V 3.3V power JTAG TMS (Test Mode Select) 9 JTAG1 TRST# (Test/Reset) resets JTAG i/f +3.3V 3.3V power 10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power 11 WAKE# Signal for Link reactivation PERST# Hot-Plug presence detect Fundamental Reset Mechanical Key Table 2.17 PCI Express x8 Connector Pinout (Part 1 of 3) 89EB-LOGAN-19 Evaluation Board 2 - 12 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Pin Side A Side B 12 RSVD Reserved GND 13 GND Ground REFCLK+ REFCLK Reference clock 14 PETp0 Transmitter differential REFCLK- (differential pair) 15 PETn0 pair, Lane 0 16 GND 17 PRSNT2# 18 GND 19 GND Ground Ground Ground PERp0 Receiver differential Hot-Plug presence detect PERn0 pair, Lane 0 Ground GND Ground PETp1 Transmitter differential RSVD Reserved 20 PETn1 pair, Lane 1 GND Ground 21 GND Ground PERp1 Receiver differential 22 GND Ground PERn1 pair, Lane 1 23 PETp2 Transmitter differential GND Ground 24 PETn2 pair, Lane 2 GND Ground 25 GND Ground PERp2 Receiver differential 26 GND Ground PERn2 pair, Lane 2 27 PETp3 Transmitter differential GND Ground 28 PETn3 pair, Lane 3 GND Ground 29 GND Ground PERp3 Receiver differential 30 RSVD Reserved PERn3 pair, Lane 3 31 PRSNT2# 32 GND 33 Hot-Plug presence detect GND Ground Ground RSVD Reserved PETp4 Transmitter differential RSVD Reserved 34 PETn4 pair, Lane 4 GND Ground 35 GND Ground PERp4 Receiver differential 36 GND Ground PERn4 pair, Lane 4 37 PETp5 Transmitter differential GND Ground 38 PETn5 pair, Lane 5 GND Ground 39 GND Ground PERp5 Receiver differential 40 GND Ground PERn5 pair, Lane 5 41 PETp6 Transmitter differential GND Ground 42 PETn6 pair, Lane 6 GND Ground 43 GND Ground PERp6 Receiver differential 44 GND Ground PERn6 pair, Lane 6 45 PETp7 Transmitter differential GND Ground 46 PETn7 pair, Lane 7 GND Ground Table 2.17 PCI Express x8 Connector Pinout (Part 2 of 3) 89EB-LOGAN-19 Evaluation Board 2 - 13 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Pin Side A 47 GND 48 PRSNT2# 49 GND Side B Ground PERp7 Receiver differential Hot-Plug presence detect PERn7 pair, Lane 7 Ground GND Ground Table 2.17 PCI Express x8 Connector Pinout (Part 3 of 3) 89EB-LOGAN-19 Evaluation Board 2 - 14 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes EB-LOGAN-19 Board Figure Figure 2.9 EB24NT24G2 Evaluation Board 89EB-LOGAN-19 Evaluation Board 2 - 15 February 16, 2011 IDT Installation of the EB-LOGAN-19 Evaluation Board Notes 89EB-LOGAN-19 Evaluation Board 2 - 16 February 16, 2011 Chapter 3 Software for the EB-LOGAN-19 Eval Board ® Notes Introduction This chapter discusses some of the main features of the available software to give users a better understanding of what can be achieved with the EB-LOGAN-19 evaluation board using the device management software. Device management software and related user documentation are available on a CD which is included in the Evaluation Board Kit. This information is also available on IDT FTP site and also at my.idt.com. For more information, please go to: http://www.idt.com/?app=TechSupport&prodFamily=PCIe%20Switches or email IDT at ssdhelp@idt.com. Device Management Software The primary use of the Device Management Software package is to enable users of the evaluation board to access all the registers in the PES24NT24G2 device. This access can be achieved using the PCI Express in-band configuration cycles through the upstream port on the PES24NT24G2 or through the SMBUS salve interface available on the IDT PCIe switch. This software also enables users to save a snapshot of the current register set into a dump file which can be used for debugging purposes. An export/import facility is also available to create and use “Configuration” files which can be used to initialize the switch device with specific values in specific registers. A conversion utility is also provided to translate a configuration file into an EEPROM programmable data structure. This enables the user to program an appropriate serial EEPROM with desirable register settings for the PES24NT24G2, and then to populate that EEPROM onto the Evaluation Board. It is also possible to program the EEPROM directly on the Evaluation Board using a feature provided by the software package. The front-end of the Device Management Software is a user-friendly Graphical User Interface which allows the user to quickly read or write the registers of interest. The GUI also permits the user to run the software in “simulation” mode with no real hardware attached, allowing the creation of configuration files for the PES24NT24G2 in the absence of the actual device. Much of the Device Management Software is written with device-independent and OS-independent code. The software is expected to work on Linux (/sys interface) and MS Windows XP. It may function well on various flavors of MS Windows, but may not be validated on all. The fact that the software is device-independent assures its scalability to future PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc. The actual program name of the Device Management Software is “PCIeBrowser” (an executable file under Windows or Linux). Revision 5.0.1 or later is required for devices in the PES24NT24G2 product family family. Device Drivers The PES24NT24G2 and other members of this switch family offer Non-Transparent Bridging and built-in DMA capability inside the device. Device drivers are needed to take advantage of these features. Sample code for these drivers is available from IDT for the Linux operating system. Additionally, there a few other software packages available from IDT. These packages are not related to the evaluation board per se, and therefore not listed here. However, several of these packages may prove to be useful for specific device or system functionality. For more information, please go to http://www.idt.com/?app=TechSupport&prodFamily=PCIe%20Switches or email IDT at ssdhelp@idt.com. 89EB-LOGAN-19 Evaluation Board 3-1 February 16, 2011 IDT Software for the EB-LOGAN-19 Eval Board Notes 89EB-LOGAN-19 Evaluation Board 3-2 February 16, 2011 Chapter 4 Schematics ® Notes Schematics 89EB-LOGAN-19 Evaluation Board 4-1 February 16, 2011 8 7 6 5 4 3 2 1 REVISIONS DCN REV 1.0 DESCRIPTION CHANGE BY DATE INITIAL RELEASE 2009-12-05 T. TRAN 1. TITLE PAGE / TABLE OF CONTENTS D C D 22. POWER CONNECTORS, MIN LOAD RESISTORS 8, 12 23. POWER REGULATOR - VDDIO 4. MEZZANINE CONNECTOR PORTS 16, 20 24. POWER REGULATOR - VDDCORE 5. 24NT24G2 - SERDES 25. POWER REGULATOR - VDDPEA 6. 24NT24G2 - CLK, CONFIG, GPIO 26. POWER REGULATOR - VDDPEHA 7. 24NT24G2 - POWER, GND 27. POWER REGULATOR - VDDPETA 8. IOEXPANDER 0-3 28. RESET, SMBUS, EEPROM, JTAG 9. IOEXPANDER 4-7 29. DIP SWITCHES 10. IOEXPANDER 8-11 30. LED - PORT STATUS (1 OF 7) 11. IOEXPANDER 12-13 31. LED - PORT STATUS (2 OF 7) 12. IOEXPANDER 16-19 32. LED - PORT STATUS (3 OF 7) 13. IOEXPANDER 20-21 33. LED - PORT STATUS (4 OF 7) 14. HOT PLUG CONTROL PORTS 8-12 34. LED - PORT STATUS (5 OF 7) 15. HOT PLUG CONTROL PORTS 16-20 35. LED - PORT STATUS (6 OF 7) 16. SLOT RESETS AND WAKE PULL-UPS 36. LED - PORT STATUS (7 OF 7) 17. CLOCK 37. 12PK RIBBON CONNECTORS 18. CLOCK BUFFER 38 PARTITION RESET SELECT HEADERS 19. CLOCK SELECTOR - DUT PCLK 8 39. SLOT RESET SELECT HEADERS 20. CLOCK SELECTOR - DUT PCLK 16 40. PORT 8 CLOCK GENERATOR 21. CLOCK SELECTOR - SLOTS 0-20, GCLK 41. PORT 16 CLOCK GENERATOR 2. SAS CONNECTOR PORTS 3. MEZZANINE CONNECTOR PORTS 0-7 B C B A A TITLE EB-LOGAN-19 SIZE B DRAWING NO. FAB P/N SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. CHECKED BY Thu Jun 10 11:24:42 2010 8 7 6 5 4 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) 2010 IDT REV. 18-692-001 2 SHEET 1 OF 41 1 8 7 6 5 4 3 2 1 1 MOLEX_IPASS_36 D 5 5 5 5 5 5 5 5 OUT OUT OUT OUT A1 GND1 GND7 B1 A2 RX0P TX0P B2 A3 RX0N TX0N B3 A4 GND2 GND8 B4 PE01RP0 PE01RN0 A5 RX1P TX1P B5 A6 RX1N TX1N B6 A7 GND3 GND9 B7 A8 SB7 A9 PE03RP0 PE03RN0 OUT OUT 0.1UF 0.1UF C28 0.1UF 0.1UF C36 C32 C38 PE00TP0 PE00TN0 PE01TP0 PE01TN0 IN IN 5 5 5 5 IN IN 5 5 5 5 OUT OUT OUT OUT A1 GND1 GND7 B1 PE04RP0 PE04RN0 A2 RX0P TX0P B2 A3 RX0N TX0N B3 A4 GND2 GND8 B4 PE05RP0 PE05RN0 A5 RX1P TX1P B5 A6 RX1N TX1N B6 A7 GND3 GND9 B7 A8 SB7 A9 SB0 B8 SB0 B8 SB3 SB1 B9 SB3 SB1 B9 A10 SB4 SB2 B10 A10 SB4 SB2 B10 A11 SB5 SB6 B11 A11 SB5 SB6 B11 A12 GND4 GND10 B12 A12 GND4 GND10 B12 A13 RX2P TX2P B13 A13 RX2P TX2P B13 A14 RX2N TX2N B14 A15 GND5 GND11 B15 A16 RX3P TX3P B16 A17 RX3N TX3N B17 A18 GND6 GND12 B18 MTG1 MTG1 MTG6 MTG6 MTG2 MTG2 MTG7 MTG7 MTG3 MTG3 MTG8 MTG9 MTG4 C MOLEX_IPASS_36 PE00RP0 PE00RN0 PE02RP0 PE02RN0 OUT OUT MTG5 MTG4 0.1UF 0.1UF C50 C56 PE02TP0 PE02TN0 IN IN 5 5 PE06RP0 PE06RN0 OUT OUT A14 RX2N TX2N B14 A15 GND5 GND11 B15 A16 RX3P TX3P B16 A17 RX3N TX3N B17 A18 GND6 GND12 B18 MTG1 MTG1 MTG6 MTG6 MTG2 MTG2 MTG7 MTG7 MTG8 MTG3 MTG3 MTG8 MTG8 MTG9 MTG4 MTG4 MTG9 MTG9 MTG5 MTG5 0.1UF 0.1UF C58 C59 PE03TP0 PE03TN0 IN IN 5 5 5 5 5 5 PE07RP0 PE07RN0 OUT OUT MTG5 J39 1 J40 VERT SMT 0.1UF 0.1UF C63 0.1UF 0.1UF C68 0.1UF 0.1UF C73 0.1UF 0.1UF C80 C67 C71 C76 C81 PE04TP0 PE04TN0 PE05TP0 PE05TN0 PE06TP0 PE06TN0 PE07TP0 PE07TN0 IN IN 5 IN IN 5 IN IN 5 IN IN 5 D 5 5 5 5 C VERT SMT B B A A TITLE EB-LOGAN-19 SAS CONNECTOR PORTS 0-7 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:42 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 2 OF 41 1 8 7 6 5 4 3 2 1 S8_3VAUX S12_3VAUX S8_12V D S8_3V S12_12V D S12_3V 470-1075-600 (1 of 2) 470-1075-600 (2 of 2) Wafer 0 OUT F12 G11 H12 H12 J11 J11 K12 K12 L11 L11 M12 M12 P2 N11 N11 P12 P12 T2 T2 R11 R11 T12 T12 V2 V2 U11 U11 V12 V12 W11 W11 A13 A13 B14 B14 C13 C13 D14 D14 E13 E13 F14 F14 G13 G13 H14 H14 J13 J13 K14 K14 L13 L13 M14 M14 P14 P14 T14 T14 V14 V14 D2 D2 5 F2 F2 H2 H2 5 K2 K2 5 M2 M2 P2 E1 G1 G1 J1 J1 L1 L1 N1 N1 R1 R1 PE10RN0 PE10RP0 OUT OUT U1 U1 STK2CFG1 W1 W1 PE14TN0 PE14TP0 A3 A3 B4 B4 5 C3 C3 D4 D4 5 E3 E3 F4 F4 G3 G3 H4 H4 5 J3 J3 K4 K4 5 M4 M4 P4 P4 N13 N13 T4 T4 R13 R13 V4 V4 U13 U13 W13 W13 A15 A15 B16 B16 C15 C15 D16 D16 E15 E15 F16 F16 G15 G15 H16 H16 J15 J15 K16 K16 L15 L15 M16 M16 P16 P16 T16 T16 V16 V16 Wafer 1 IN IN 5 37 30 8 P8_PDN OUT OUT L3 N3 N3 R3 R3 U3 U3 M812_ID W3 W3 PE13TN0 PE13TP0 A5 A5 B6 B6 5 IN IN 5 C5 C5 D6 D6 5 E5 E5 F6 F6 H6 H6 5 K6 K6 5 M6 M6 P6 P6 N15 N15 T6 T6 R15 R15 V6 V6 U15 U15 W15 W15 A17 A17 B18 B18 C17 C17 D18 D18 F18 F18 H18 H18 K18 K18 M18 M18 P18 P18 T18 T18 V18 V18 J5 L5 L5 N5 N5 R5 R5 U5 W5 W5 A7 A7 B8 B8 21 C7 C7 D8 D8 21 E7 E7 F8 F8 G7 G7 H8 H8 J7 J7 K8 K8 L7 L7 M8 M8 N7 N7 P8 R7 R7 T8 U7 U7 V8 W7 W7 A9 A9 B10 B10 21 C9 C9 D10 D10 21 E9 E9 F10 F10 G9 G9 H10 H10 K10 K10 M10 M10 3 P10 P10 3 T10 T10 V10 V10 IN IN PE08RN0 PE08RP0 OUT OUT Wafer 3 5 Wafer 8 IN IN S12_CLKN S12_CLKP E17 G17 G17 R28 J17 J17 L17 L17 P8 N17 N17 T8 R17 R17 V8 U17 U17 M812_ID W17 W17 S8_CLKN S8_CLKP A19 A19 B20 B20 C19 C19 D20 D20 F20 F20 H20 H20 K20 K20 M20 M20 P20 P20 T20 T20 V20 V20 38 35 6 37 16 IN OUT OUT SLOT_HDR_RSTN12 SLOT_WAKEN12 100 100 Wafer 4 5 PE11TN0 PE11TP0 IN IN 5 L9 N9 N9 R9 R9 U9 U9 W9 38 35 37 29 W9 6 16 6 IN OUT BI IN OUT SLOT_HDR_RSTN8 SLOT_WAKEN8 MEZZ_SMBCLK3 MEZZ_SMBDAT3 100 100 E19 E19 R29 G19 G19 R30 J19 J19 L19 L19 N19 N19 R19 R19 U19 U19 W19 W19 STK2CFG0 Common Power J9 L9 39 IN IN Signal J9 +3V3 B Wafer 9 Common Power 5 PE11RN0 PE11RP0 OUT OUT Signal 5 Common Power E17 R27 39 Signal Common Power 5 PE12RN0 PE12RP0 OUT OUT Signal 5 B PE12TN0 PE12TP0 IN IN Common Power G5 J5 PE08TN0 PE08TP0 Signal OUT OUT G5 U5 5 X8 - STK2CFG1 = 0, STK2CFG0 = 0 Wafer 7 Common Power 5 PE13RN0 PE13RP0 Signal 5 C STK2CFG1 & STK2CFG0 SET BY MEZZ CARDS X4 - STK2CFG1 = 0, STK2CFG0 = 1 Wafer 2 5 Common Power C PE09RN0 PE09RP0 OUT OUT Signal L3 Common Power 5 PE14RN0 PE14RP0 OUT OUT Signal 5 Wafer 6 PE09TN0 PE09TP0 IN IN R32 5 1K 6 F12 C1 R31 29 OUT D12 E11 G11 C1 IN IN Common Power 8 D12 5 Signal 30 P12_PDN B12 C11 E11 B2 Common Power 5 OUT OUT B12 C11 B2 E1 PE15RN0 PE15RP0 A11 A1 Signal 5 Wafer 5 PE10TN0 PE10TP0 A11 A1 1K 5 37 PE15TN0 PE15TP0 IN IN MEZZ_SMBCLK3 J51 5 MEZZ_SMBDAT3 OUT BI 3 3 J3 J3 A A TITLE EB-LOGAN-19 MEZZANINE CONNECTOR PORTS 8/12 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:42 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 3 OF 41 1 8 7 6 5 4 3 2 1 S16_3VAUX S20_3VAUX S16_12V S16_3V D S20_12V D S20_3V 470-1075-600 (1 of 2) 470-1075-600 (2 of 2) Wafer 0 OUT F12 G11 H12 H12 J11 J11 K12 K12 L11 L11 M12 M12 P2 N11 N11 P12 P12 T2 T2 R11 R11 T12 T12 V2 V2 U11 U11 V12 V12 W11 W11 A13 A13 B14 B14 C13 C13 D14 D14 E13 E13 F14 F14 G13 G13 H14 H14 J13 J13 K14 K14 L13 L13 M14 M14 P14 P14 T14 T14 V14 V14 D2 D2 5 F2 F2 H2 H2 5 K2 K2 5 M2 M2 P2 E1 G1 G1 J1 J1 L1 L1 N1 N1 R1 R1 PE18RN0 PE18RP0 OUT OUT U1 U1 STK3CFG1 W1 W1 PE22TN0 PE22TP0 A3 A3 B4 B4 5 C3 C3 D4 D4 5 E3 E3 F4 F4 G3 G3 H4 H4 5 J3 J3 K4 K4 5 M4 M4 P4 P4 N13 N13 T4 T4 R13 R13 V4 V4 U13 U13 W13 W13 A15 A15 B16 B16 C15 C15 D16 D16 E15 E15 F16 F16 G15 G15 H16 H16 J15 J15 K16 K16 L15 L15 M16 M16 P16 P16 T16 T16 V16 V16 Wafer 1 IN IN 5 37 30 8 P16_PDN OUT OUT L3 N3 N3 R3 R3 U3 U3 M1620_ID W3 W3 PE21TN0 PE21TP0 A5 A5 B6 B6 5 IN IN 5 C5 C5 D6 D6 5 E5 E5 F6 F6 H6 H6 5 K6 K6 5 M6 M6 P6 P6 N15 N15 T6 T6 R15 R15 V6 V6 U15 U15 W15 W15 A17 A17 B18 B18 C17 C17 D18 D18 F18 F18 H18 H18 K18 K18 M18 M18 P18 P18 T18 T18 V18 V18 J5 L5 L5 N5 N5 R5 R5 U5 W5 W5 A7 A7 B8 B8 21 C7 C7 D8 D8 21 E7 E7 F8 F8 G7 G7 H8 H8 J7 J7 K8 K8 L7 L7 M8 M8 N7 N7 P8 R7 R7 T8 U7 U7 V8 W7 W7 A9 A9 B10 B10 21 C9 C9 D10 D10 21 E9 E9 F10 F10 G9 G9 H10 H10 K10 K10 M10 M10 4 P10 P10 4 T10 T10 V10 V10 IN IN PE16RN0 PE16RP0 OUT OUT Wafer 3 5 Wafer 8 IN IN S20_CLKN S20_CLKP E17 G17 G17 R39 J17 J17 L17 L17 P8 N17 N17 T8 R17 R17 V8 U17 U17 M1620_ID W17 W17 S16_CLKN S16_CLKP A19 A19 B20 B20 C19 C19 D20 D20 F20 F20 H20 H20 K20 K20 M20 M20 P20 P20 T20 T20 V20 V20 38 35 6 37 16 IN OUT OUT SLOT_HDR_RSTN20 SLOT_WAKEN20 100 100 Wafer 4 5 PE19TN0 PE19TP0 IN IN 5 L9 N9 N9 R9 R9 U9 U9 W9 38 35 37 29 W9 6 16 6 IN OUT BI IN OUT SLOT_HDR_RSTN16 SLOT_WAKEN16 MEZZ_SMBCLK4 MEZZ_SMBDAT4 100 100 E19 E19 R40 G19 G19 R41 J19 J19 L19 L19 N19 N19 R19 R19 U19 U19 W19 W19 STK3CFG0 Common Power J9 L9 39 IN IN Signal J9 +3V3 B Wafer 9 Common Power 5 PE19RN0 PE19RP0 OUT OUT Signal 5 Common Power E17 R38 39 Signal Common Power 5 PE20RN0 PE20RP0 OUT OUT Signal 5 B PE20TN0 PE20TP0 IN IN Common Power G5 J5 PE16TN0 PE16TP0 Signal OUT OUT G5 U5 5 X8 - STK3CFG1 = 0, STK3CFG0 = 0 Wafer 7 Common Power 5 PE21RN0 PE21RP0 Signal 5 C STK3CFG1 & STK3CFG0 SET BY MEZZ CARDS X4 - STK3CFG1 = 0, STK3CFG0 = 1 Wafer 2 5 Common Power C PE17RN0 PE17RP0 OUT OUT Signal L3 Common Power 5 PE22RN0 PE22RP0 OUT OUT Signal 5 Wafer 6 PE17TN0 PE17TP0 IN IN R43 5 1K 6 F12 C1 R42 29 OUT D12 E11 G11 C1 IN IN Common Power 8 D12 5 Signal 30 P20_PDN B12 C11 E11 B2 Common Power 5 OUT OUT B12 C11 B2 E1 PE23RN0 PE23RP0 A11 A1 Signal 5 Wafer 5 PE18TN0 PE18TP0 A11 A1 1K 5 37 PE23TN0 PE23TP0 IN IN MEZZ_SMBCLK4 J52 5 MEZZ_SMBDAT4 OUT BI 4 4 J4 J4 A A TITLE EB-LOGAN-19 MEZZANINE CONNECTOR PORTS 16/20 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:42 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 4 OF 41 1 8 7 6 5 4 3 2 1 D D 89HPES24NT24G2 (3/8) 2 2 2 2 2 2 2 2 2 2 2 2 2 C 2 2 2 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN 89HPES24NT24G2 (5/8) PE00RP0 PE00RN0 M15 PE00RP0 PE00TP0 K18 M16 PE00RN0 PE00TN0 K17 PE01RP0 PE01RN0 L15 PE01RP0 PE01TP0 J18 L16 PE01RN0 PE01TN0 J17 PE02RP0 PE02RN0 H15 PE02RP0 PE02TP0 F18 H16 PE02RN0 PE02TN0 F17 PE03RP0 PE03RN0 G15 PE03RP0 PE03TP0 E18 G16 PE03RN0 PE03TN0 E17 PE04RP0 PE04RN0 D14 PE04RP0 PE04TP0 A16 C14 PE04RN0 PE04TN0 B16 PE05RP0 PE05RN0 D13 PE05RP0 PE05TP0 A15 C13 PE05RN0 PE05TN0 B15 PE06RP0 PE06RN0 D8 PE06RP0 PE06TP0 A10 C8 PE06RN0 PE06TN0 B10 PE07RP0 PE07RN0 D7 PE07RP0 PE07TP0 A9 C7 PE07RN0 PE07TN0 B9 PE00TP0 PE00TN0 PE01TP0 PE01TN0 PE02TP0 PE02TN0 PE03TP0 PE03TN0 PE04TP0 PE04TN0 PE05TP0 PE05TN0 PE06TP0 PE06TN0 PE07TP0 PE07TN0 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 OUT OUT 2 4 2 4 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN PE16RP0 PE16RN0 R5 PE16RP0 PE16TP0 V3 T5 PE16RN0 PE16TN0 U3 PE17RP0 PE17RN0 R6 PE17RP0 PE17TP0 V4 T6 PE17RN0 PE17TN0 U4 PE18RP0 PE18RN0 R9 PE18RP0 PE18TP0 V7 T9 PE18RN0 PE18TN0 U7 PE19RP0 PE19RN0 R10 PE19RP0 PE19TP0 V8 T10 PE19RN0 PE19TN0 U8 PE20RP0 PE20RN0 R13 PE20RP0 PE20TP0 V14 T13 PE20RN0 PE20TN0 U14 PE21RP0 PE21RN0 R16 PE21RP0 PE21TP0 V15 T16 PE21RN0 PE21TN0 U15 PE22RP0 PE22RN0 P17 PE22RP0 PE22TP0 V17 R17 PE22RN0 PE22TN0 U17 PE23RP0 PE23RN0 N18 PE23RP0 PE23TP0 U18 P18 PE23RN0 PE23TN0 T18 PE16TP0 PE16TN0 PE17TP0 PE17TN0 PE18TP0 PE18TN0 PE19TP0 PE19TN0 PE20TP0 PE20TN0 PE21TP0 PE21TN0 PE22TP0 PE22TN0 PE23TP0 PE23TN0 OUT OUT 4 OUT OUT 4 OUT OUT 4 OUT OUT 4 OUT OUT 4 OUT OUT 4 OUT OUT 4 OUT OUT 4 4 4 4 4 4 4 C 4 4 U1 U1 89HPES24NT24G2 (4/8) 3 3 3 3 B 3 3 3 3 3 3 3 3 3 3 3 3 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN PE08RP0 PE08RN0 B5 PE08RP0 PE08TP0 A2 B4 PE08RN0 PE08TN0 A3 PE09RP0 PE09RN0 C4 PE09RP0 PE09TP0 B1 C3 PE09RN0 PE09TN0 B2 PE10RP0 PE10RN0 E4 PE10RP0 PE10TP0 G1 E3 PE10RN0 PE10TN0 G2 PE11RP0 PE11RN0 F4 PE11RP0 PE11TP0 H1 F3 PE11RN0 PE11TN0 H2 PE12RP0 PE12RN0 J4 PE12RP0 PE12TP0 L1 J3 PE12RN0 PE12TN0 L2 PE13RP0 PE13RN0 K4 PE13RP0 PE13TP0 M1 K3 PE13RN0 PE13TN0 M2 PE14RP0 PE14RN0 N4 PE14RP0 PE14TP0 R1 N3 PE14RN0 PE14TN0 R2 PE15RP0 PE15RN0 P4 PE15RP0 PE15TP0 T1 P3 PE15RN0 PE15TN0 T2 PE08TP0 PE08TN0 PE09TP0 PE09TN0 PE10TP0 PE10TN0 PE11TP0 PE11TN0 PE12TP0 PE12TN0 PE13TP0 PE13TN0 PE14TP0 PE14TN0 PE15TP0 PE15TN0 OUT OUT 3 OUT OUT 3 OUT OUT 3 OUT OUT 3 OUT OUT 3 OUT OUT 3 OUT OUT 3 OUT OUT 3 3 3 B 3 3 3 3 3 3 U1 A A TITLE EB-LOGAN-19 24NT24G2 - SERDES SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:43 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 5 OF 41 1 8 7 6 5 4 3 2 1 D D 89HPES24NT24G2 (1/8) 21 21 21 21 DUT RESET 29 IN IN IN IN IN GCLK0P A12 GCLKP0 P08CLKP D1 GCLK0N B12 GCLKN0 P08CLKN D2 GCLK1P V12 GCLKP1 P16CLKP V11 GCLK1N U12 GCLKN1 P16CLKN U11 N2 GCLKFSEL 39 38 35 28 3 39 38 35 3 39 38 35 4 39 38 35 4 MAIN_RSTN SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 IN IN IN IN IN 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 12 12 11 YEL TP108 E14 PERSTN 29 IN 29 3 29 3 IN IN IN IN IN 29 J118 29 29 29 4 29 4 C 29 29 29 29 29 29 29 29 29 IN IN IN IN IN IN IN IN IN IN IN PERSTN 28 28 13 13 12 12 11 11 10 10 9 9 8 8 OUT BI R24 R55 1K 1K G3 A8 G2 A4 G1 B8 G3 G2 G1 RSTHALT T3 RSTHALT STK2CFG0 R4 STK2CFG0 STK2CFG1 C5 STK2CFG1 STK2CFG2 B6 STK2CFG2 STK2CFG3 D6 STK2CFG3 STK2CFG4 D5 STK2CFG4 STK3CFG0 U2 STK3CFG0 REFRES00 M18 REFRES00 STK3CFG1 C6 STK3CFG1 REFRES01 G17 REFRES01 STK3CFG2 B7 STK3CFG2 REFRES02 C12 REFRES02 STK3CFG3 A5 STK3CFG3 REFRES03 C9 REFRES03 STK3CFG4 E5 STK3CFG4 REFRES04 H4 REFRES04 REFRES05 L4 REFRES05 SWMODE0 N1 SWMODE0 REFRES06 U6 REFRES06 SWMODE1 R3 SWMODE1 REFRES07 U16 SWMODE2 P5 SWMODE2 SWMODE3 T4 SWMODE3 REFRESPLL C10 CLKMODE0 U1 CLKMODE0 CLKMODE1 C15 19 IN IN 20 19 20 29 IN IN IN 29 29 PLACE RESISTORS AS CLOSE TO U1 AS POSSIBLE 1% 1% 1% 1% 1% 1% 1% 1% R46 REFRES07 3.01K 3.01K 3.01K 3.01K 3.01K 3.01K 3.01K 3.01K REFRESPLL 3.01K 1% R54 R47 R48 C R49 R50 R51 R52 R53 CLKMODE1 U1 +3V3 B P16CLKP P16CLKN IN IN GCLKFSEL HDR_2x6 39 P08CLKP P08CLKN 89HPES24NT24G2 (2/8) 29 28 28 IN BI DUT_JTAG_TCK JTAG_TDI E15 DUT_JTAG_TDI MSMBCLK JTAG_TDO B17 DUT_JTAG_TDO D16 MSMBDAT JTAG_TMS D15 DUT_JTAG_TMS JTAG_TRST_N C16 DUT_JTAG_TRST_N SSMBADDR1 R18 SSMBADDR1 SSMBADDR2 F15 SSMBADDR2 GPIO_00 T14 GPIO0 GPIO_01 R14 GPIO1 SSMBCLK C18 SSMBCLK GPIO_02 T15 GPIO2 SSMBDAT C17 SSMBDAT GPIO_03 R15 GPIO3 GPIO_04 N16 GPIO4 GPIO5 MSMBDAT IN IN D17 B18 0 MSMBCLK 29 B JTAG_TCK R45 B14 NC1 GPIO_05 P16 M17 NC2 GPIO_06 N15 GPIO6 GPIO_07 N14 GPIO7 GPIO_08 N17 GPIO8 IN IN OUT IN IN BI BI BI BI BI OUT IN BI BI 28 28 28 28 28 30 30 30 30 30 30 30 30 30 U1 A A TITLE EB-LOGAN-19 24NT24G2 - CLK, CONFIG, GPIO SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:43 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 6 OF 41 1 8 7 6 5 4 3 2 1 5 6 7 8 5 6 7 8 CP10 D 4 3 3 5 2 2 6 1 1 7 0.1UF 4 5 C118 0.1UF 6 C115 0.1UF 4 C111 0.1UF 7 C109 0.1UF 3 C107 5 C104 0.1UF 0.1UF 8 C97 2 C93 0.1UF 0.1UF 1 C90 0.1UF 6 C87 0.1UF 7 C82 0.1UF 5 C74 0.1UF 6 C65 0.1UF 4 C61 0.1UF 7 C57 0.1UF 8 C47 0.1UF 3 C42 0.1UF 0.1UF 0.1UF 2 C39 0.1UF 0.1UF 1 C34 0.01UF CP7 5 C21 47UF CP4 6 C16 3 CP2 7 C11 47UF 2 47UF W31 1 C6 W30 47UF LABEL: FAN LABEL: 1 GND 2 12V/5V 3 NC +5V0_PS C1 +12V3_PS D 1.0UF +1V0_CORE C54 0.1UF 8 8 8 0.1UF 0.1UF 0.1UF 5 C31 0.01UF 0.1UF 6 C27 0.01UF CP8 4 C23 47UF CP5 7 C18 47UF CP3 3 C13 47UF CP1 2 C8 47UF +3V3_IO C3 +1V0_CORE 1.0UF 8 +1V0_PEA E2 VSS16 VSS59 L18 E16 VDDCORE14 VDDPEA3 E8 VSS17 VSS60 M3 K7 VDDCORE15 VDDPEA4 E11 F1 VSS18 VSS61 M4 K9 VDDCORE16 VDDPEA5 E12 F2 VSS19 VSS62 M5 K11 VDDCORE17 VDDPEA6 E13 F8 VSS20 VSS63 M8 K12 VDDCORE18 VDDPEA7 F6 F12 VSS21 VSS64 M10 F14 VSS22 VSS65 M12 F16 VSS23 VSS66 N8 L7 VDDCORE19 VDDPEA8 F13 L9 VDDCORE20 VDDPEA9 G6 VDDCORE21 VDDPEA10 G13 G3 VSS24 VSS67 N12 M7 VDDCORE22 VDDPEA11 M6 G4 VSS25 VSS68 P1 M9 G8 VDDPEA12 M13 VSS26 VSS69 P2 VDDCORE24 VDDPEA13 N5 G10 VSS27 VSS70 R7 N7 VDDCORE25 VDDPEA14 N6 G12 VSS28 VSS71 R8 N9 VDDCORE26 VDDPEA15 N13 G14 VSS29 VSS72 V9 VDDCORE27 VDDPEA16 P6 G18 VSS30 VSS73 V10 VDDPEA17 P7 H3 VSS31 VSS74 R12 VDDPEA18 P11 H6 VSS32 VSS75 T7 VDDPEA19 P12 H8 VSS33 VSS76 T8 VDDPEA20 P13 H10 VSS34 VSS77 V13 H13 VSS35 VSS78 T17 H17 VSS36 VSS79 U5 H18 VSS37 VSS80 U9 J1 VSS38 VSS81 U10 J2 VSS39 VSS82 U13 J6 VSS40 VSS83 V5 J8 VSS41 VSS84 V6 J10 VSS42 VSS85 V16 J13 VSS43 VSS86 V18 U1 A K5 VDDPETA8 K14 VDDPEHA9 VDDPETA9 L5 R11 VDDPEHA10 VDDPETA10 L6 T11 VDDPEHA11 VDDPETA11 N10 T12 VDDPEHA12 VDDPETA12 P8 VDDPETA13 P9 VDDPETA14 P10 TITLE 1 4 3 1 4 2 0.1UF 0.1UF 1 CP9 EB-LOGAN-19 24NT24G2 - POWER SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6 5 2010 4 IDT 2.0 Derek Huang Thu Jun 10 11:24:44 2010 3 REV. 18-692-001 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 7 CP6 A U1 8 3 2 1 4 3 2 C92 VDDPETA7 VDDPEHA8 M14 0.1UF VDDPEHA7 L14 C86 L13 0.1UF J14 C69 VDDPETA6 0.1UF VDDPEHA6 C51 J5 H5 0.1UF VDDPETA5 C46 VDDPEHA5 0.1UF H14 G5 C44 F10 VDDPETA4 0.1UF E10 VDDPETA3 VDDPEHA4 C33 VDDPETA2 VDDPEHA3 F5 0.01UF VDDPEHA2 D12 C29 D11 0.01UF E9 C25 VDDPETA1 47UF VDDPEHA1 C20 89HPES24NT24G2 (7/8) C11 47UF 1.0UF U1 C15 8 +1V0_PETA 47UF +2V5_PEHA B +1V0_PETA C10 N11 C5 B VDDCORE23 M11 +2V5_PEHA 47UF L11 5 E7 6 VDDPEA2 J12 4 L17 VDDCORE13 J11 3 VSS58 7 VSS15 2 E1 8 E6 1 VDDPEA1 5 VDDCORE12 4 L12 J9 6 VSS57 3 VSS14 7 D18 2 VDDCORE11 C114 L10 J7 0.1UF VSS56 C106 L8 VSS13 0.1UF VSS55 D10 C96 VSS12 VDDCORE10 0.1UF L3 VDDCORE9 H12 C91 K16 VSS54 0.1UF VSS53 VSS11 D9 H11 C66 VSS10 D4 +1V0_PEA 0.1UF D3 V2 C77 V1 VDDIO8 0.1UF VDDIO7 VDDCORE8 C62 VDDCORE7 H9 0.1UF H7 C +3V3_IO C45 K15 0.1UF VSS52 C40 VSS9 0.1UF C2 C41 P15 0.01UF VDDIO6 C35 VDDCORE6 0.01UF K13 G11 C37 VSS51 0.01UF VSS8 C26 K10 C1 0.01UF VSS50 P14 C24 VSS7 VDDIO5 47UF VDDIO4 VDDCORE5 C22 K8 VDDCORE4 G9 C 47UF VSS49 C19 VSS6 B13 47UF B11 A18 C17 A17 47UF VDDIO3 G7 C14 VDDCORE3 F11 47UF B3 C12 A14 A7 47UF K6 A6 VDDIO2 C9 K2 VSS48 VDDIO1 VDDCORE2 47UF VSS47 VSS5 VDDCORE1 F9 C7 VSS4 F7 47UF K1 C4 J16 VSS46 1.0UF J15 VSS45 VSS3 C2 VSS44 VSS2 A13 1.0UF VSS1 A11 A1 89HPES24NT24G2 (6/8) 1 89HPES24NT24G2 (8/8) 2 SHEET 7 OF 41 1 8 7 6 5 4 3 +3V3 2 1 +3V3 28 13 13 12 12 11 11 10 10 9 8 9 8 6 6 IN BI 21 R60 2 R61 3 MSMBCLK MSMBDAT 0 0 A0 A1 A2 P0 4 P1 5 P2 6 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 R65 22 SCL P9 14 R66 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 C184 28 R59 V+ 0.1UF C 12 P0_APN P0_PDN P0_PFN P0_PWRGDN P0_AIN P0_PIN P0_PEP P0_RSTN P4_APN P4_PDN P4_PFN P4_PWRGDN P4_AIN P4_PIN P4_PEP P4_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT MAX7311AUG 24 30 30 37 31 37 31 0 2.7K 0 37 32 R71 21 R72 2 R73 3 1 R1612 0 IOEXPINTN OUT 4 P1 5 A0 P2 6 A1 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 A2 32 33 37 13 16 33 30 30 37 28 13 12 11 10 9 8 6 31 37 28 13 12 11 10 9 8 6 31 37 IN BI MSMBCLK MSMBDAT 0 0 R77 22 SCL P9 14 R78 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 32 32 33 37 13 16 33 VSS INT_N P0 V+ C186 0 0 0 24 U22 +3V3 0.1UF MAX7311AUG PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 10.0K U20 8 9 10 11 12 13 30 12 1 12 12 11 11 10 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT R63 2 3 0 0 5 A0 P2 6 A1 P3 7 A2 8 P5 9 P6 10 P7 11 P8 13 R67 22 SCL P9 14 R68 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 0.1UF A P4 12 37 31 37 32 32 33 37 13 16 33 30 30 37 31 37 31 37 32 32 33 37 13 16 C 33 0 R1614 IOEXPINTN 9 10 11 12 13 30 P8_APN P8_PDN P8_PFN P8_PWRGDN P8_AIN P8_PIN P8_PEP P8_RSTN P16_APN P16_PDN P16_PFN P16_PWRGDN P16_AIN P16_PIN P16_PEP P16_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 24 30 3 30 1 R1613 0 IOEXPINTN OUT P0 4 P1 5 A0 P2 6 V+ 37 14 31 37 14 31 37 2.7K 2.7K 0 32 R74 21 R75 2 A1 P3 7 R76 3 A2 P4 8 P5 9 14 33 37 P6 10 13 16 33 P7 11 P8 13 32 30 4 30 37 15 31 37 15 31 37 28 13 12 11 10 9 8 6 28 13 12 11 10 9 8 6 IN BI MSMBCLK MSMBDAT 0 0 R79 22 SCL P9 14 R80 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 32 32 15 33 37 13 16 33 VSS INT_N 10.0K MAX7311AUG C187 13 21 4 P1 C185 13 R62 P0 V+ U23 +3V3 0.1UF 28 8 37 31 R106 R94 MAX7311AUG 24 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 10.0K U21 +3V3 28 OUT 30 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD R64 30 ADDR: 0X24 +3V3 2.7K 0 0 IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT IOEXPANDER 2 ADDR: 0X20 B P2_APN P2_PDN P2_PFN P2_PWRGDN P2_AIN P2_PIN P2_PEP P2_RSTN P6_APN P6_PDN P6_PFN P6_PWRGDN P6_AIN P6_PIN P6_PEP P6_RSTN VSS INT_N IOEXPANDER 0 D 10.0K R69 R105 D 8 9 10 11 12 13 30 12 B P12_APN P12_PDN P12_PFN P12_PWRGDN P12_AIN P12_PIN P12_PEP P12_RSTN P20_APN P20_PDN P20_PFN P20_PWRGDN P20_AIN P20_PIN P20_PEP P20_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 30 3 30 37 14 31 37 14 31 37 32 32 14 33 37 13 16 33 30 4 30 37 15 31 37 15 31 37 32 32 15 33 37 13 16 33 VSS INT_N 1 IOEXPANDER 1 IOEXPANDER 3 ADDR: 0X22 ADDR: 0X26 TITLE 0 R1615 IOEXPINTN OUT 8 9 10 11 12 13 30 A EB-LOGAN-19 IOEXPANDER 0-3 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:44 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 8 OF 41 1 8 7 6 5 4 3 +3V3 2 1 +3V3 24 0 0 2.7K 28 13 13 12 12 11 11 10 10 9 8 9 8 6 6 IN BI 21 R84 2 R85 3 MSMBCLK MSMBDAT 0 0 A0 A1 A2 P0 4 P1 5 P2 6 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 R89 22 SCL P9 14 R90 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 C188 28 R83 V+ 0.1UF C 12 MAX7311AUG P1_APN P1_PDN P1_PFN P1_PWRGDN P1_AIN P1_PIN P1_PEP P1_RSTN P3_APN P3_PDN P3_PFN P3_PWRGDN P3_AIN P3_PIN P3_PEP P3_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 24 30 30 37 31 37 31 0 2.7K 2.7K 37 32 R95 21 R96 2 R97 3 1 R1616 0 IOEXPINTN OUT 4 P1 5 A0 P2 6 A1 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 A2 32 33 37 13 16 33 30 30 37 28 13 12 11 10 9 8 6 31 37 28 13 12 11 10 9 8 6 31 37 IN BI MSMBCLK MSMBDAT 0 0 R101 22 SCL P9 14 R102 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 32 32 33 37 13 16 33 VSS INT_N P0 V+ 8 9 10 11 12 13 30 12 1 11 11 10 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT R87 2 R88 3 0 0 5 A0 P2 6 A1 P3 7 A2 P4 8 P5 9 P6 10 P7 11 P8 13 R91 22 SCL P9 14 R92 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 0.1UF 12 37 32 32 33 37 13 16 33 30 30 37 31 37 31 37 32 32 33 37 13 16 C 33 0 R1618 IOEXPINTN OUT 8 9 10 11 12 13 30 P5_APN P5_PDN P5_PFN P5_PWRGDN P5_AIN P5_PIN P5_PEP P5_RSTN P7_APN P7_PDN P7_PFN P7_PWRGDN P7_AIN P7_PIN P7_PEP P7_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 30 OUT 8 24 30 37 31 37 31 37 2.7K 2.7K 2.7K 32 1 R1617 0 IOEXPINTN P0 4 P1 5 A0 P2 6 V+ R98 21 R99 2 A1 P3 7 R100 3 A2 P4 8 P5 9 P6 10 P7 11 P8 13 32 33 37 13 16 33 30 30 37 28 13 12 11 10 9 8 6 31 37 28 13 12 11 10 9 8 6 31 IN BI MSMBCLK MSMBDAT 0 0 R103 22 SCL P9 14 R104 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 37 32 32 33 37 13 16 33 VSS INT_N 10.0K MAX7311AUG C191 12 21 4 P1 C189 12 R86 P0 V+ U27 +3V3 0.1UF 24 13 37 31 R130 R118 10.0K U25 MAX7311AUG 13 37 31 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD +3V3 28 30 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 28 30 ADDR: 0X2C +3V3 2.7K 0 2.7K IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT IOEXPANDER 6 ADDR: 0X28 B P10_APN P10_PDN P10_PFN P10_PWRGDN P10_AIN P10_PIN P10_PEP P10_RSTN P14_APN P14_PDN P14_PFN P14_PWRGDN P14_AIN P14_PIN P14_PEP P14_RSTN VSS INT_N IOEXPANDER 4 D 10.0K U26 +3V3 C190 MAX7311AUG 0.1UF U24 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 10.0K PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD R129 R117 D 9 10 11 12 13 30 12 B P18_APN P18_PDN P18_PFN P18_PWRGDN P18_AIN P18_PIN P18_PEP P18_RSTN P22_APN P22_PDN P22_PFN P22_PWRGDN P22_AIN P22_PIN P22_PEP P22_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 30 OUT 8 30 37 31 37 31 37 32 32 33 37 13 16 33 30 30 37 31 37 31 37 32 32 33 37 13 16 33 VSS INT_N 1 0 R1619 IOEXPINTN 9 10 11 12 13 30 IOEXPANDER 5 IOEXPANDER 7 A A ADDR: 0X2A ADDR: 0X2E TITLE EB-LOGAN-19 IOEXPANDER 4-7 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:45 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 9 OF 41 1 8 7 6 5 4 3 2 +3V3 1 +3V3 R143 R141 D D 24 12 11 10 9 8 6 13 12 11 10 9 8 6 IN BI 2 R109 3 0 0 A0 A1 A2 P0 4 P1 5 P2 6 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 R113 22 SCL P9 14 R114 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 0.1UF C 12 P9_APN P9_PDN P9_PFN P9_PWRGDN P9_AIN P9_PIN P9_PEP P9_RSTN P11_APN P11_PDN P11_PFN P11_PWRGDN P11_AIN P11_PIN P11_PEP P11_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 24 30 30 37 31 37 31 0 2.7K 0 37 32 R119 21 R120 2 R121 3 1 0 R1620 IOEXPINTN OUT 33 37 13 16 30 37 31 37 31 37 28 28 13 13 12 12 11 11 10 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT 0 0 9 8 6 10 9 8 6 IN BI MSMBCLK MSMBDAT R110 21 R111 2 3 0 0 P4 8 P5 9 P6 10 P7 11 P8 13 A2 22 SCL P9 14 R126 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 32 32 33 37 13 16 33 8 9 10 11 12 13 30 12 IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 30 OUT 8 30 37 31 37 31 37 32 32 33 37 13 16 33 30 30 37 31 37 31 37 32 32 33 37 13 16 C 33 VSS INT_N 1 0 ADDR: 0X54 4 P1 5 A0 P2 6 A1 P3 7 A2 P4 8 P5 9 P6 10 P7 11 P8 13 22 SCL P9 14 R116 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 12 R1622 IOEXPINTN 9 10 11 12 13 30 R144 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 10.0K P0 V+ R115 0.1UF 7 U31 +3V3 MAX7311AUG P13_APN P13_PDN P13_PFN P13_PWRGDN P13_AIN P13_PIN P13_PEP P13_RSTN P15_APN P15_PDN P15_PFN P15_PWRGDN P15_AIN P15_PIN P15_PEP P15_RSTN IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 30 OUT 8 24 30 37 31 37 31 37 0 2.7K 0 32 1 0 R1621 IOEXPINTN 4 P1 5 A0 P2 6 R122 21 R123 2 A1 P3 7 R124 3 A2 P4 8 P5 9 P6 10 P7 11 P8 13 32 33 37 13 16 33 30 30 37 31 37 31 28 28 13 13 12 12 11 11 10 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT 0 0 R127 22 SCL P9 14 R128 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 37 32 32 33 37 13 16 33 VSS INT_N P0 V+ C195 10 11 P3 R125 0.1UF 11 12 A1 30 R142 12 13 6 IOEXPANDER 10 C193 13 28 P2 IOEXPANDER 8 U29 24 28 A0 P17_APN P17_PDN P17_PFN P17_PWRGDN P17_AIN P17_PIN P17_PEP P17_RSTN P19_APN P19_PDN P19_PFN P19_PWRGDN P19_AIN P19_PIN P19_PEP P19_RSTN ADDR: 0X50 MAX7311AUG R112 5 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 0 0 0 4 P1 33 +3V3 B P0 V+ 32 VSS INT_N 10.0K MAX7311AUG 10.0K 13 28 21 R108 C192 28 MSMBCLK MSMBDAT R107 V+ U30 +3V3 C194 MAX7311AUG 0.1UF U28 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 0 0 0 10.0K PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 9 10 11 12 13 30 12 P21_APN P21_PDN P21_PFN P21_PWRGDN P21_AIN P21_PIN P21_PEP P21_RSTN P23_APN P23_PDN P23_PFN P23_PWRGDN P23_AIN P23_PIN P23_PEP P23_RSTN 30 IN IN IN IN OUT OUT OUT OUT IN IN IN IN OUT OUT OUT OUT 30 OUT 8 30 37 31 37 31 37 32 32 33 37 13 16 30 37 31 37 31 37 33 32 32 33 37 13 16 33 VSS INT_N IOEXPANDER 9 B 1 0 R1623 IOEXPINTN 9 10 11 12 13 30 IOEXPANDER 11 A A ADDR: 0X56 ADDR: 0X52 TITLE EB-LOGAN-19 IOEXPANDER 8-11 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2009 2010 4 IDT CHECKED BY Thu Jun 10 11:24:45 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 10 OF 41 1 8 7 6 5 4 3 +3V3 2 1 +3V3 R147 R145 D 10.0K 24 13 12 12 11 11 10 10 9 9 8 8 6 6 IN BI R1149 2 R1150 3 0 0 A0 A1 A2 R1154 22 SCL R1155 23 SDA C645 28 13 21 0.1UF C 12 P0 4 P1 5 P2 6 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 P9 14 P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 MAX7311AUG P0_MRLN P1_MRLN P2_MRLN P3_MRLN P4_MRLN P5_MRLN P6_MRLN P7_MRLN P8_MRLN P10_MRLN P12_MRLN P14_MRLN P16_MRLN P18_MRLN P20_MRLN P22_MRLN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN 24 P0 4 P1 5 A0 P2 6 A1 P3 7 P4 8 34 P5 9 34 P6 10 34 P7 11 P8 13 P9 14 34 0 2.7K 2.7K 34 34 34 R1160 21 R1161 2 R1162 3 1 0 R1624 IOEXPINTN OUT A2 34 34 28 13 12 11 10 9 8 6 IN BI MSMBCLK MSMBDAT 0 0 R1166 22 SCL R1167 23 SDA P10 15 34 P11 16 34 P12 17 P13 18 P14 19 P15 20 34 28 13 12 11 10 9 8 6 34 34 34 VSS INT_N V+ 34 8 9 10 11 12 13 30 12 INT_N 12 11 10 9 8 8 6 6 IN BI MSMBCLK MSMBDAT R1152 2 3 0 0 R1156 22 R1157 23 5 A0 P2 6 A1 P3 7 A2 SCL SDA 0.1UF 12 P4 8 P5 9 P6 10 P7 11 P8 13 P9 14 P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 MAX7311AUG P9_MRLN P11_MRLN P13_MRLN P15_MRLN P17_MRLN P19_MRLN P21_MRLN P23_MRLN IN IN IN IN IN IN IN IN 24 34 5 A0 P2 6 21 R1164 2 A1 P3 7 R1165 3 A2 P4 8 P5 9 34 P6 10 34 P7 11 P8 13 P9 14 P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 34 34 34 28 28 13 13 12 12 11 11 10 10 9 9 8 8 6 6 IN BI MSMBCLK MSMBDAT 0 0 R1168 22 R1169 23 SCL SDA 1 0 R1625 IOEXPINTN OUT 8 9 10 11 12 13 30 12 34 34 34 34 35 35 35 35 35 35 C 35 35 R1626 0 IOEXPINTN 9 10 11 12 13 30 B P1_ILOCKST P3_ILOCKST P5_ILOCKST P7_ILOCKST P10_ILOCKST P14_ILOCKST P18_ILOCKST P22_ILOCKST P1_ILOCKP P3_ILOCKP P5_ILOCKP P7_ILOCKP P10_ILOCKP P14_ILOCKP P18_ILOCKP P22_ILOCKP IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT 34 OUT 8 34 34 34 34 34 34 34 35 35 35 35 35 35 35 35 VSS INT_N 1 R1627 0 IOEXPINTN 9 10 11 12 13 30 IOEXPANDER 15 IOEXPANDER 13 A 4 P1 R1163 0 2.7K 2.7K 34 VSS INT_N P0 V+ 34 C648 13 9 21 4 P1 C646 28 10 R1151 P0 V+ U97 +3V3 0.1UF 24 11 34 R148 R146 MAX7311AUG 12 1 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 10.0K U90 +3V3 13 8 34 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 28 OUT 34 ADDR: 0X5C +3V3 R1153 34 IOEXPANDER 14 ADDR: 0X58 0 0 2.7K IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT VSS IOEXPANDER 12 B P0_ILOCKST P2_ILOCKST P4_ILOCKST P6_ILOCKST P8_ILOCKST P12_ILOCKST P16_ILOCKST P20_ILOCKST P0_ILOCKP P2_ILOCKP P4_ILOCKP P6_ILOCKP P8_ILOCKP P12_ILOCKP P16_ILOCKP P20_ILOCKP 10.0K 28 MSMBCLK MSMBDAT R1148 V+ U96 +3V3 C647 MAX7311AUG 0.1UF U89 +3V3 10.0K PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 0 0 2.7K D A ADDR: 0X5E ADDR: 0X5A TITLE EB-LOGAN-19 IOEXPANDER 12-15 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:45 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 11 OF 41 1 8 7 6 5 4 3 +3V3 2 1 +3V3 R149 D D 24 28 13 12 12 11 11 10 10 9 9 8 8 6 6 IN BI 21 R1125 2 R1126 3 0 0 A0 A1 A2 R1130 22 SCL R1131 23 SDA C641 28 13 MSMBCLK MSMBDAT R1124 V+ 0.1UF C 12 P0 4 P1 5 P2 6 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 P9 14 P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 U87 MAX7311AUG P9_ILOCKST P11_ILOCKST P13_ILOCKST P15_ILOCKST P17_ILOCKST P19_ILOCKST P21_ILOCKST P23_ILOCKST P9_ILOCKP P11_ILOCKP P13_ILOCKP P15_ILOCKP P17_ILOCKP P19_ILOCKP P21_ILOCKP P23_ILOCKP IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT 24 34 0 0 0 34 34 34 R1136 21 R1137 2 R1138 3 1 0 R1628 IOEXPINTN OUT 34 P7 11 P8 13 P9 14 35 28 35 13 12 11 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT 0 0 R1142 22 SCL R1143 23 SDA P10 15 35 P11 16 35 P12 17 P13 18 P14 19 P15 20 28 35 13 12 11 10 35 35 35 8 9 10 11 13 30 12 11 10 9 8 6 IN BI MSMBCLK MSMBDAT R1127 21 R1128 2 R1129 3 0 0 INT_N 36 36 36 36 36 36 36 36 36 36 36 36 C 36 36 1 ADDR: 0XA4 U88 +3V3 R1132 22 R1133 23 P0 4 P1 5 A0 P2 6 A1 P3 7 V+ A2 SCL SDA 0.1UF 12 P4 8 P5 9 P6 10 P7 11 P8 13 P9 14 P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 P0_LINKUPN P1_LINKUPN P2_LINKUPN P3_LINKUPN P4_LINKUPN P5_LINKUPN P6_LINKUPN P7_LINKUPN P8_LINKUPN P9_LINKUPN P10_LINKUPN P11_LINKUPN P12_LINKUPN P13_LINKUPN P14_LINKUPN P15_LINKUPN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 24 36 P0 4 P1 5 A0 P2 6 V+ 36 R1139 21 R1140 2 A1 P3 7 R1141 3 A2 P4 8 P5 9 36 P6 10 36 P7 11 P8 13 P9 14 P10 15 36 P11 16 36 P12 17 P13 18 P14 19 P15 20 2.7K 0 0 36 36 36 36 36 28 36 28 36 13 13 12 12 11 11 10 10 9 9 8 8 6 6 IN BI MSMBCLK MSMBDAT 0 0 R1144 22 R1145 23 36 36 36 VSS INT_N B MAX7311AUG SCL SDA 1 12 P16_LINKUPN P17_LINKUPN P18_LINKUPN P19_LINKUPN P20_LINKUPN P21_LINKUPN P22_LINKUPN P23_LINKUPN P16_ACTIVEN P17_ACTIVEN P18_ACTIVEN P19_ACTIVEN P20_ACTIVEN P21_ACTIVEN P22_ACTIVEN P23_ACTIVEN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 VSS INT_N 1 IOEXPANDER 19 ADDR: 0XA6 IOEXPANDER 17 A 36 VSS C644 12 6 36 IOEXPANDER 18 0.1UF 13 8 P4 8 10 U86 C642 28 9 7 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 24 10 P3 P6 MAX7311AUG 11 A1 P0_ACTIVEN P1_ACTIVEN P2_ACTIVEN P3_ACTIVEN P4_ACTIVEN P5_ACTIVEN P6_ACTIVEN P7_ACTIVEN P8_ACTIVEN P9_ACTIVEN P10_ACTIVEN P11_ACTIVEN P12_ACTIVEN P13_ACTIVEN P14_ACTIVEN P15_ACTIVEN +3V3 +3V3 12 6 P5 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 13 P2 34 +3V3 28 A0 A2 ADDR: 0XB0 2.7K 0 0 5 34 IOEXPANDER 16 B 4 P1 9 VSS INT_N P0 V+ 34 C643 MAX7311AUG 0.1UF U85 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 0 0 0 10.0K PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD ADDR: 0XA2 TITLE A EB-LOGAN-19 IOEXPANDER 16-19 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:46 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 12 OF 41 1 8 7 6 5 4 3 2 1 +3V3 R150 D U83 MAX7311AUG 24 0 0 0 28 28 13 13 12 12 11 11 10 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT R131 21 R132 2 R133 3 0 0 P0 4 P1 5 A0 P2 6 A1 P3 7 P4 8 P5 9 P6 10 P7 11 P8 13 V+ A2 R137 22 SCL P9 14 R138 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 12 P0_RSTN P2_RSTN P4_RSTN P6_RSTN P8_RSTN P12_RSTN P16_RSTN P20_RSTN PART0_PERSTN PART1_PERSTN PART2_PERSTN PART3_PERSTN PART4_PERSTN PART5_PERSTN PART6_PERSTN PART7_PERSTN OUT OUT OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN IN IN 8 16 33 8 16 33 8 16 33 8 16 33 8 16 33 8 16 33 8 16 33 8 16 33 35 38 35 38 35 38 35 38 35 38 35 38 35 38 35 38 C VSS INT_N 0.1UF C196 C D 10.0K PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD 1 0 R1633 IOEXPINTN OUT 8 9 10 11 12 30 IOEXPANDER 20 ADDR: 0XA8 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD U84 +3V3 B B MAX7311AUG 24 2.7K 0 0 28 13 13 12 12 11 11 10 10 9 8 9 8 6 6 IN BI MSMBCLK MSMBDAT 4 P1 5 A0 P2 6 R134 21 R135 2 A1 P3 7 R136 3 A2 P4 8 P5 9 P6 10 P7 11 P8 13 0 0 R139 22 SCL P9 14 R140 23 SDA P10 15 P11 16 P12 17 P13 18 P14 19 P15 20 0.1UF C197 28 P0 V+ 12 P1_RSTN P3_RSTN P5_RSTN P7_RSTN P9_RSTN P10_RSTN P11_RSTN P13_RSTN P14_RSTN P15_RSTN P17_RSTN P18_RSTN P19_RSTN P21_RSTN P22_RSTN P23_RSTN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 9 16 33 9 16 33 9 16 33 9 16 33 10 9 10 10 9 16 16 16 16 16 10 16 10 16 9 16 33 33 33 33 33 33 33 33 10 16 33 10 16 33 9 10 16 16 33 33 VSS INT_N 1 IOEXPANDER 21 A A ADDR: 0XAA TITLE EB-LOGAN-19 IOEXPANDER 20-21 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:46 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 13 OF 41 1 6 5 3 2 +3V3_PS S8_3V R256 0.047UF D S8_12V W16 8 7 Q11 D D D D NMOSFET W15 C263 4 3 15 R252 R245 R244 R243 R242 R241 R240 R239 R238 0.013 R237 2 1 C261 0.015UF R248 6 10 5 4 3 S S S G 2 Q9 1 NMOSFET D R254 S S S G R250 10 D D D D 5 51 R246 0.008 LTC4242CUHF 10K 10K 10K 10K 10K 10K 10K 10K 33 C 1 +12V3_PS 8 +3V3_PS 4 7 7 6 8 C 28 12VOUT1 29 12VGATE1 30 12VSENSE1 31 12VIN1 3VIN1 5 3VSENSE1 4 3VGATE1 3 3VOUT1 2 S8_3VAUX W17 37 37 31 31 33 IN OUT 8 OUT 8 OUT 8 OUT 8 IN P8_PFN P8_PWRGDN P12_PFN P12_PWRGDN P12_PEP AUXIN1 1 AUXON1 38 ON1 R227 35 R228 34 R229 32 AUXPGOODN1 R230 33 R231 17 R232 18 AUXFAULTN2 R233 20 R234 R235 R236 AUXOUT1 27 FAULTN1 FON1 37 AUXFAULTN1 ENN1 36 PGOODN1 GND1 26 FAULTN2 GND2 39 AUXPGOODN2 ENN2 16 19 PGOODN2 FON2 15 14 ON2 13 AUXON2 AUXOUT2 25 8 10K 10K B C260 37 31 8 8 6 R226 R224 37 33 31 VCC R225 R223 37 37 100 100 100 100 100 100 100 100 100 100 100 100 P8_PEP 7 AUXIN2 21 12VIN2 22 12VSENSE2 23 12VGATE2 24 12VOUT2 S12_3VAUX 3VOUT2 12 3VGATE2 11 3VSENSE2 10 3VIN2 W18 B 9 1.0UF U47 S12_3V W19 0.013 C264 0.047UF W20 A 8 7 6 NMOSFET R257 S12_12V 4 3 2 15 D D D D Q12 R249 5 10 0.015UF 51 4 3 S S S G 2 Q10 NMOSFET 1 A R255 S S S G 1 C262 R251 8 7 10 D D D D 6 R247 5 0.008 R253 TITLE EB-LOGAN-19 HOT PLUG CONTROL PORTS 8-12 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:46 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 14 OF 41 1 6 5 3 2 +3V3_PS S16_3V R291 0.047UF D S16_12V W22 8 7 Q15 D D D D NMOSFET W21 C268 4 3 15 R287 R280 R279 R278 R277 R276 R275 R274 R273 0.013 R272 2 1 C266 0.015UF R283 6 10 5 4 3 S S S G 2 Q13 1 NMOSFET D R289 S S S G R285 10 D D D D 5 51 R281 0.008 LTC4242CUHF 10K 10K 10K 10K 10K 10K 10K 10K 33 C 1 +12V3_PS 8 +3V3_PS 4 7 7 6 8 C 28 12VOUT1 29 12VGATE1 30 12VSENSE1 31 12VIN1 3VIN1 5 3VSENSE1 4 3VGATE1 3 3VOUT1 2 S16_3VAUX W23 37 37 31 31 33 IN OUT 8 OUT 8 OUT 8 OUT 8 IN P16_PFN P16_PWRGDN P20_PFN P20_PWRGDN P20_PEP AUXIN1 1 AUXON1 38 ON1 R262 35 R263 34 R264 32 AUXPGOODN1 R265 33 R266 17 R267 18 AUXFAULTN2 R268 20 R269 R270 R271 AUXOUT1 27 FAULTN1 FON1 37 AUXFAULTN1 ENN1 36 PGOODN1 GND1 26 FAULTN2 GND2 39 AUXPGOODN2 ENN2 16 19 PGOODN2 FON2 15 14 ON2 13 AUXON2 AUXOUT2 25 8 10K 10K B C265 37 31 8 8 6 R261 R259 37 33 31 VCC R260 R258 37 37 100 100 100 100 100 100 100 100 100 100 100 100 P16_PEP 7 AUXIN2 21 12VIN2 22 12VSENSE2 23 12VGATE2 24 12VOUT2 S20_3VAUX 3VOUT2 12 3VGATE2 11 3VSENSE2 10 3VIN2 W24 B 9 1.0UF U48 S20_3V W25 0.013 C269 0.047UF W26 A 8 7 6 NMOSFET R292 S20_12V 4 3 2 15 D D D D Q16 R284 5 10 0.015UF 51 4 3 S S S G 2 Q14 NMOSFET 1 A R290 S S S G 1 C267 R286 8 7 10 D D D D 6 R282 5 0.008 R288 TITLE EB-LOGAN-19 HOT PLUG CONTROL PORTS 16-20 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:47 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 15 OF 41 1 8 7 6 5 +3V3 33 13 10 P23_RSTN IN 1 OE_N 2 A 3 GND 5 33 4 10 P15_RSTN IN R1 10K Y 13 SLOT_RSTN23 OUT 37 38 39 1 OE_N 2 A 3 GND 13 9 P22_RSTN IN 1 OE_N 2 A 3 5 33 GND Y 4 13 9 P14_RSTN IN R2 10K SLOT_RSTN22 OUT 37 38 39 OE_N 2 A 3 10 P21_RSTN IN 1 OE_N 2 A 3 5 33 Y 4 13 10 P13_RSTN IN R3 10K GND C 33 13 8 IN OE_N 2 A 3 GND SLOT_RSTN21 OUT 37 38 39 2 A 3 10 P19_RSTN IN 1 A 3 GND 5 33 4 8 IN R4 10K Y 13 P12_RSTN 9 P18_RSTN IN 1 OE_N 2 A 3 SLOT_RSTN20 OUT 37 39 OE_N A 3 GND 13 10 P17_RSTN IN OE_N 2 A 3 GND VCC 5 33 Y 4 13 10 P11_RSTN IN R11 10K SLOT_RSTN19 OUT 37 38 39 1 A 3 GND 8 P16_RSTN IN 1 2 A 3 GND 13 8 P6_RSTN IN 5 Y 4 33 13 9 P10_RSTN IN SLOT_RSTN14 R12 SLOT_RSTN18 5 VCC 4 OUT 37 38 39 A 3 OUT 37 38 OE_N 2 A 3 39 33 13 9 P5_RSTN 33 4 10 P9_RSTN IN R13 10K Y 13 IN R23 SLOT_RSTN13 5 VCC SLOT_RSTN17 OUT 37 38 39 2 A 3 GND OUT 37 38 2 A 3 39 33 4 13 8 P4_RSTN 33 4 8 P8_RSTN IN R14 10K Y 13 SLOT_RSTN16 OUT 37 U11 39 1 IN R25 SLOT_RSTN12 2 A 3 GND SLOT_RSTN6 4 OUT 37 38 39 VCC 5 GND Y 1K 1K 1K 1K R1285 1K 1K 1K 1K R1289 1K 1K 1K 1K R1293 1K 1K 1K 1K R1297 1K 1K 1K 1K R1301 1K 1K 1K 1K R1305 R1286 R1287 R1288 SLOT_WAKEN0 SLOT_WAKEN1 SLOT_WAKEN2 SLOT_WAKEN3 OUT OUT OUT OUT SLOT_RSTN5 4 R1290 R1291 R1292 R1294 R1295 R1296 SLOT_WAKEN4 SLOT_WAKEN5 SLOT_WAKEN6 SLOT_WAKEN7 SLOT_WAKEN8 SLOT_WAKEN9 SLOT_WAKEN10 SLOT_WAKEN11 R44 OUT 37 38 39 OUT 37 39 OE_N 2 A 3 GND VCC 5 R1280 10K Y SLOT_RSTN4 4 OUT 37 38 R1298 R1299 R1300 SLOT_WAKEN12 SLOT_WAKEN13 SLOT_WAKEN14 SLOT_WAKEN15 37 37 37 37 OUT OUT OUT OUT 37 OUT OUT OUT OUT 3 OUT OUT OUT OUT 3 OUT OUT OUT OUT 4 OUT OUT OUT OUT 4 37 37 37 37 37 37 37 37 37 37 5 VCC 33 4 13 9 P3_RSTN IN R26 SLOT_RSTN11 OUT 37 38 39 1 OE_N 2 A 3 GND VCC 5 37 4 VCC 5 Y 4 VCC 5 R1303 R1304 C 37 37 37 R1306 R1307 R1308 SLOT_WAKEN20 SLOT_WAKEN21 SLOT_WAKEN22 SLOT_WAKEN23 37 37 37 37 37 R1281 10K Y R1302 SLOT_WAKEN16 SLOT_WAKEN17 SLOT_WAKEN18 SLOT_WAKEN19 39 SN74LVC1G125 SLOT_RSTN3 OUT 37 38 39 OUT 37 38 39 U112 SN74LVC1G125 VCC 5 Y 4 33 13 8 P2_RSTN IN R33 SLOT_RSTN10 OUT 37 38 1 OE_N 2 A 3 39 R1282 10K GND SLOT_RSTN2 U113 B SN74LVC1G125 5 VCC 33 4 Y 13 9 P1_RSTN IN R34 10K OE_N 39 R37 10K 1 SLOT_RSTN9 OUT 37 38 39 1 OE_N 2 A 3 GND R1283 10K Y 4 VCC 5 SLOT_RSTN1 OUT 37 38 39 OUT 37 38 39 U114 SN74LVC1G125 5 Y OE_N U106 VCC 38 U111 GND OE_N 37 U110 10K 1 OUT 5 10K 1 SN74LVC1G125 5 VCC GND U105 VCC SLOT_RSTN7 4 SN74LVC1G125 Y 2 Y D R36 U109 10K OE_N 5 SN74LVC1G125 Y 1 VCC 10K 1 SN74LVC1G125 VCC 10K OE_N GND U104 SN74LVC1G125 13 33 10K OE_N 2 U10 33 3 U103 GND 1 A SN74LVC1G125 SN74LVC1G125 33 4 Y 2 U9 B 39 R22 10K 1 SN74LVC1G125 13 38 2 U102 U8 33 37 OE_N SN74LVC1G125 VCC OE_N 2 5 VCC GND U7 13 OUT 1 SN74LVC1G125 Y OE_N SN74LVC1G125 33 SLOT_RSTN15 10K 1 U6 1 P7_RSTN IN U101 SN74LVC1G125 P20_RSTN 9 SN74LVC1G125 VCC +3V3 U108 GND U5 13 4 Y 13 R15 10K 1 SN74LVC1G125 33 33 SN74LVC1G125 VCC 1 SN74LVC1G125 5 VCC U100 SN74LVC1G125 2 +3V3 SN74LVC1G125 VCC U4 33 3 +3V3 SN74LVC1G125 D 4 SN74LVC1G125 5 VCC 33 4 8 P0_RSTN IN R35 10K Y 13 SLOT_RSTN8 OUT 37 39 OE_N 2 A 3 GND R1284 10K Y SLOT_RSTN0 4 C661 C662 C663 C664 C665 C666 C667 C668 C669 C670 C671 C672 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF U115 0.1UF U107 1 A A TITLE EB-LOGAN-19 SLOT RESETS AND WAKE PULL-UPS SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:47 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 16 OF 41 1 D XTAL_IN 2 XTAL_OUT 31 VDD 4 VDD 14 VDD 24 VDD 29 VDDA 28 ICS_FS IN 21 33.2 R301 Q0 5 33.2 R302 FSEL1 nQ0 6 Q1 7 OE_REFOUT nQ1 8 30 REF_SEL 22 FSEL0 23 20 REF_OUT ICS_SSM IN C280 C281 0.1UF 1.0UF C278 0.1UF C279 C277 0.1UF YEL TP2 Q2 10 26 IREF nQ2 11 25 SSM Q3 12 27 BYPASS nQ3 13 3 29 400MA REF_IN C 29 FB1 10UF C276 0.1UF ICS841484 1 C275 120OHM 0805 0.1UF R296 DNP 5% 0.1UF 10UF R294 DNP 1 1 C271 1 R306 2 2 22PF 2 +3V3 C270 X1 3 C274 D 22PF 4 10 0603 C273 R299 DNP 5 16V R297 DNP 6 R295 7 DNP 8 MR_nOE 33.2 R303 33.2 R304 33.2 R307 33.2 R308 33.2 33.2 C CGCLKP CGCLKN OUT OUT 17 678005005 CG_SATA_CLKP CG_SATA_CLKN CG_SMA_CLKP CG_SMA_CLKN R309 R305 33.2 17 R310 GND NC 19 GND NC 16 32 GND NC 17 33 PGND NC 18 1% CONNSMA NC NC NC NC 5 1 2 2 3 3 4 4 5 5 6 6 7 7 4 1 2 U49 475 R293 J119 15 9 1 MTG1 MTG1 MTG2 MTG2 J121 3 221789-0 J120 CONNSMA R317 R315 49.9 R318 49.9 49.9 R316 49.9 49.9 3 221789-0 R314 678005005 1 3 3 5 1 2 R312 4 B 2 49.9 4 R313 R311 49.9 J7 CONNSMA 5 1 49.9 J5 CONNSMA 4 221789-0 10K DNP B R300 R298 5 2 221789-0 A 1 1 2 2 3 3 4 4 5 5 6 6 7 7 MTG1 MTG1 MTG2 MTG2 SATAIN_CLKP SATAIN_CLKN SATAIN_RSTN OUT OUT 17 OUT 28 17 A J8 HDR_2x5 18 OUT 17 IN 17 IN MAIN_CLKP SMAIN_CLKP CGCLKP SATAIN_CLKP 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 J6 VERT-SM 10 MAIN_CLKN SMAIN_CLKN CGCLKN SATAIN_CLKN OUT 18 IN 17 IN 17 TITLE EB-LOGAN-19 2.00MM CLOCK SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:48 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 17 OF 41 1 8 7 6 5 4 3 2 1 D +3V3 D R333 2.2 C288 C289 C290 C291 C292 0.1UF 0.1UF 1.0UF 0.1UF C287 0.1UF 0.1UF C286 1% 0.1UF 500MA C285 C283 0.1UF FB2 10UF C282 1.0UF 600OHM 0805 R328 R322 R326 R321 R324 R320 +3V3 U50 ICS9DB803 OE2# 7 OE3# 43 OE4# 35 OE5# 44 27 26 28 40 22 23 24 1 R329 R327 R323 10 18 OE_INV=1 OE6# DIF_3 DIF_3# 20 BS12CLKP_R 21 BS12CLKN_R DIF_4 DIF_4# 30 BS16CLKP_R 29 BS16CLKN_R 33.2 33.2 R340 33.2 33.2 R342 33.2 33.2 R344 33.2 33.2 R346 33.2 33.2 R348 3 21 4 4 5 5 OUT OUT 21 6 6 21 7 DIF_5 DIF_5# 34 BS20CLKP_R 33 BS20CLKN_R DIF_6 DIF_6# 38 SATACLKP_R 37 SATACLKN_R DIF_7 DIF_7# 42 SMAOUT_CLKP_R 41 SMAOUT_CLKN_R BS08CLKP BS08CLKN 7 OUT OUT 21 MTG1 R339 MTG1 21 MTG2 MTG2 OUT OUT 21 OUT OUT 21 OUT OUT 21 BS12CLKP BS12CLKN R341 BS16CLKP BS16CLKN R343 BS20CLKP BS20CLKN R345 J124 21 21 21 J123 OE7# DIFF_STOP PD HIGH_BW# OE_INV BYPASS#/PLL SCLK SDATA SRC_DIV# GND GND GND CONNSMA SATAOUT_CLKP SATAOUT_CLKN R347 5 SMAOUT_CLKP SMAOUT_CLKN R349 LOCK 45 IREF GNDA GND GND 46 YEL TP5 47 32 25 B 4 1 2 DNP 10.0K DNP 10.0K R325 3 BS08CLKN_R R338 2 3 R365 B 15 36 SILKSCREEN LABEL: SWITCH S11 POS DESCRIPTION ------------------1 P8_CLK_EN 2 P12_CLK_EN 3 P16_CLK_EN 4 P20_CLK_EN ------------------- 17 33.2 33.2 R364 S11 BS08CLKP_R 2 OE1# R363 S4B 5 DIF_2 DIF_2# 16 R337 1 21 BGCLK1P BGCLK1N R362 S4A 6 BGCLK1N_R R336 R361 S3B P8_CLK_EN P12_CLK_EN P16_CLK_EN P20_CLK_EN 13 33.2 33.2 R360 S2B S3A 7 BGCLK1P_R R359 S2A 8 12 R358 4 S1B DIF_1 DIF_1# 1 OUT OUT BGCLK0P BGCLK0N R335 R357 3 S1A R334 33.2 33.2 R356 2 BGCLK0N_R R355 1 BGCLK0P_R 9 R353 R354 SM_SW4 OE0# 8 R351 14 DIF_0 DIF_0# R352 6 SRC_IN SRC_IN# 48 R350 5 C 678005005 31 3 221789-0 J122 CONNSMA 5 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 49.9 4 11 1% MAIN_CLKP MAIN_CLKN 39 VDD VDD VDDA VDD VDD VDD R332 17 IN IN 10.0K 10.0K 10.0K DNP 10.0K DNP 17 19 4 1 475 2 C 2 3 221789-0 A A TITLE EB-LOGAN-19 CLOCK BUFFER SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:48 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 18 OF 41 1 8 7 6 5 4 3 2 1 P08CLK - DUT PORT 8 CLK LP8CLK - LOCAL CLOCK GEN. PORT 8 CLK P8SHXXCLK - TO SLOT CLK HEADERS +3V3 +3V3 +3V3 D 45 nQA3 44 1 C147 C146 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF DNP DNP J62 C145 OUT C144 19 C143 YEL TP129 39 C142 6 C141 5 P8_SATARSTN 6 C140 5 MTG2 C139 MTG1 MTG2 3 R632 R629 R627 R625 R623 R621 R619 R617 R615 R613 R611 R609 R607 R605 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C156 6 21 21 21 21 21 21 QB1 21 nQB1 20 QB2 38 nQB2 39 QB3 40 nQB3 41 VCC VCC 12 VCC 18 VCC NC 19 VCC VEE 6 25 VCC VEE 13 30 VCC VEE 24 36 VCC VEE 31 42 VCC VEE 37 43 VCC VEE 48 10 P8SATA_CLK1P P8SATA_CLK1N P8SATA_CLK2P P8SATA_CLK2N P8SATA_CLK3P P8SATA_CLK3N P8SMA_CLKP P8SMA_CLKN C157 C158 C159 C160 C161 C162 C163 19 OUT OUT OUT OUT OUT OUT OUT OUT 19 19 19 19 C 19 19 19 R634 OEB3 R647 22 R631 OEB2 32 23 R628 33 QB0 nQB0 R626 OEB1 R624 OEB0 34 6 OUT OUT OUT OUT OUT OUT OUT OUT 11 DIV_SELB R622 35 +3V3 MTG1 nCLK0 R620 U17 5 R618 P8_OEB0 P8_OEB1 P8_OEB2 P8_OEB3 14 CLK0 R616 IN IN 4 C155 R614 LP8_CLKP LP8_CLKN C154 R612 40 C153 R610 18 CLK_SEL C152 R608 17 7 C151 R606 GND QA3 P8ECLK_SEL CLK1 C150 R604 nCLK nQA2 46 9 P08CLKP P08CLKN P8SH12_CLKP P8SH12_CLKN P8SH16_CLKP P8SH16_CLKN P8SH20_CLKP P8SH20_CLKN C149 R602 CLK 13 QA2 47 C148 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 R502 40 12 17 nCLK1 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF R585 nQ nQA1 8 R584 Q 16 PLACE R502 CLOSE TO U18 100 NC QA1 R568 20 OEA3 R567 NC 29 R566 3 16 15 R550 NC NC nQA0 R549 3 15 OEA2 R548 NC NC 14 28 R532 2 P8JA_FSEL0 QA0 DIV_SELA R531 BW_SEL 9 OEA1 R530 6 F_SEL0 2 OEA0 27 R514 PLL_SEL 7 R513 1 F_SEL1 26 R512 MR P8_OEA0 P8_OEA1 P8_OEA2 P8_OEA3 R511 5 P8ECLK_ENABLE C138 7 R652 R648 4 7 3 P8_SATACLKN 11 R653 4 R645 0 0 R650 C OE VDD DNP DNP 678005005 2 P8_SATACLKP 19 R505 P8JA_PLL_SEL P8JA_BW_SEL 2 VDDO ICS853S1208I 10 4 1 VDDA 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 C137 10UF 8 DNP DNP C136 0.1UF C135 0.1UF ICS874001I-02 +3V3 1 R603 C136 CLOSE TO VDDA 5% R586 R501 R504 R503 D +3V3 10 0603 U18 B 19 678005005 19 19 39 19 P8SATA_CLK1P P8SATA_CLK1N IN IN P8_SATARSTN IN 678005005 1 1 2 2 19 3 3 19 4 4 5 5 6 7 1 2 2 19 3 3 19 4 4 5 5 6 6 7 7 39 19 IN IN IN P8SATA_CLK2P P8SATA_CLK2N P8_SATARSTN 1 2 2 3 3 4 4 5 5 6 6 6 7 7 7 39 19 IN IN IN P8SATA_CLK3P P8SATA_CLK3N P8_SATARSTN P8SMA_CLKP P8SMA_CLKN IN IN B J72 J74 CONNSMA 4 MTG1 MTG1 MTG1 MTG1 MTG1 MTG2 MTG2 MTG2 MTG2 MTG2 J57 19 CONNSMA MTG2 J56 OFF OFF OFF OFF ON 1 MTG1 DEFAULT DIPSW SETTING S19:1 S19:3 S19:4 S19:5 S19:6 678005005 1 3 5 5 1 1 2 2 221789-0 J70 4 3 221789-0 (SATACLK) (PLL) (2.2MHZ) (U15 OUT ON) (100MHZ) R498 U18 OUTPUTS OFF (ENABLE) ON (DISABLE) R500 R499 R497 R496 +3V3 A A 4.7K 4.7K 4.7K 4.7K 4.7K S20 S19 SM_SW6 1 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 SM_SW8 1 P8ECLK_SEL 2 11 10 9 8 7 3 P8JA_PLL_SEL P8JA_BW_SEL P8ECLK_ENABLE P8JA_FSEL0 4 5 6 7 8 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B S7A S7B S8A S8B 16 P8_OEA0 15 P8_OEA1 14 P8_OEA2 13 P8_OEA3 TITLE EB-LOGAN-19 12 P8_OEB0 11 P8_OEB1 CLOCK SELECTOR DUT PCLK 8 10 P8_OEB2 9 P8_OEB3 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:28:22 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 19 OF 41 1 8 7 6 5 4 3 2 1 P16CLK - DUT PORT 16 CLK LP16CLK - LOCAL CLOCK GEN. PORT 16 CLK P16SHXXCLK - TO SLOT CLK HEADERS +3V3 D +3V3 +3V3 OEB2 32 OEB3 R636 1 +3V3 C113 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF DNP DNP J64 C112 OUT C110 20 C89 39 3 C108 YEL TP131 C105 6 C102 5 P16_SATARSTN 6 C100 5 MTG2 C99 MTG1 MTG2 C95 MTG1 R470 R468 R466 R464 R462 R460 R458 R456 R454 R452 R450 R448 R446 R444 R442 R440 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 470 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF C127 6 OUT OUT OUT OUT OUT OUT OUT OUT 20 6 21 21 21 21 21 21 23 22 QB1 21 nQB1 20 QB2 38 nQB2 39 QB3 40 nQB3 41 VCC VCC 12 VCC 18 VCC NC 19 VCC VEE 6 25 VCC VEE 13 30 VCC VEE 24 36 VCC VEE 31 42 VCC VEE 37 43 VCC VEE 48 10 P16SATA_CLK1P P16SATA_CLK1N P16SATA_CLK2P P16SATA_CLK2N P16SATA_CLK3P P16SATA_CLK3N P16SMA_CLKP P16SMA_CLKN C128 C129 C130 C131 C132 C133 C134 20 20 20 C 20 20 20 20 R471 33 QB0 nQB0 R469 OEB1 R467 OEB0 34 OUT OUT OUT OUT OUT OUT OUT OUT 11 DIV_SELB R465 U15 35 C126 R463 nCLK0 44 R461 5 nQA3 R459 CLK0 C125 R457 4 45 R455 LP16_CLKP LP16_CLKN QA3 C124 R453 CLK_SEL 46 R451 7 QA2 nQA2 R449 P16ECLK_SEL P16_OEB0 P16_OEB1 P16_OEB2 P16_OEB3 14 CLK1 C123 R447 GND 9 47 C122 R445 nCLK nCLK1 C121 R443 CLK 13 IN IN 8 P16CLKP P16CLKN P16SH8_CLKP P16SH8_CLKN P16SH12_CLKP P16SH12_CLKN P16SH20_CLKP P16SH20_CLKN C120 R441 41 41 12 nQA1 17 C117 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 18 16 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF R439 nQ QA1 R438 17 OEA3 R437 R367 100 Q 29 PLACE R367 CLOSE TO U16 NC NC 15 R436 20 nQA0 R435 NC OEA2 R434 R640 R638 3 16 R643 7 3 P16_SATACLKN R639 4 7 2 R635 0 0 NC 14 28 R431 NC 15 QA0 DIV_SELA R430 2 NC P16JA_FSEL0 OEA1 R429 BW_SEL 9 OEA0 27 R428 6 F_SEL0 2 26 R411 PLL_SEL 7 P16_OEA0 P16_OEA1 P16_OEA2 P16_OEA3 R410 1 F_SEL1 P16ECLK_ENABLE R407 MR DNP DNP 678005005 1 11 R406 5 4 4 OE VDD 3 C 19 ICS853S1208I 10 P16JA_PLL_SEL P16JA_BW_SEL 2 P16_SATACLKP VDDO R405 VDDA R404 8 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 C88 ICS874001I-02 DNP DNP C85 10UF 5% +3V3 1 R369 C85 CLOSE TO VDDA R366 0.1UF 0.1UF C84 10 0603 R368 D +3V3 U16 20 678005005 B 20 20 39 20 P16SATA_CLK1P P16SATA_CLK1N IN IN P16_SATARSTN IN 678005005 1 1 2 2 20 3 3 20 4 4 5 5 6 7 678005005 1 1 2 2 3 3 4 4 5 5 6 6 6 7 7 7 1 1 2 2 20 3 3 20 4 4 5 5 6 6 7 7 39 20 IN IN IN P16SATA_CLK2P P16SATA_CLK2N P16_SATARSTN 39 20 IN IN IN P16SATA_CLK3P P16SATA_CLK3N P16_SATARSTN P16SMA_CLKP P16SMA_CLKN IN IN B J54 4 MTG1 MTG1 MTG1 MTG1 MTG1 MTG2 MTG2 MTG2 MTG2 MTG2 MTG2 3 CONNSMA 5 5 1 1 2 2 221789-0 J53 J42 J55 CONNSMA MTG1 J41 20 4 3 221789-0 DEFAULT DIPSW SETTING S17:1 S17:3 S17:4 S17:5 S17:6 OFF OFF OFF OFF ON (SATACLK) (PLL) (2.2MHZ) (U15 OUT ON) (100MHZ) U16 OUTPUTS OFF (ENABLE) ON (DISABLE) R331 R330 R152 A R319 R151 +3V3 A S18 SM_SW6 1 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 4.7K 4.7K 4.7K 4.7K 4.7K SM_SW8 S17 1 2 P16ECLK_SEL 3 11 10 9 8 7 4 P16JA_PLL_SEL P16JA_BW_SEL P16ECLK_ENABLE P16JA_FSEL0 5 6 7 8 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B S7A S7B S8A S8B 16 15 14 13 12 11 10 9 P16_OEA0 P16_OEA1 P16_OEA2 P16_OEA3 P16_OEB0 P16_OEB1 P16_OEB2 P16_OEB3 TITLE EB-LOGAN-19 CLOCK SELECTOR DUT PCLK 16 SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:28:19 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 20 OF 41 1 8 7 6 5 4 3 2 1 SXXCLK - SLOT CLK BSXXLCK - BUFFER SLOT CLK LSXXCLK - LOCAL CLOCK GEN. SLOT CLK SHXXCLK - SLOT HDR.CLK D D 678005005 1 2 2 3 3 40 HDR_2x6 40 3 18 20 21 IN OUT IN IN IN LS8_CLKP S8_CLKP BS08CLKP P16SH8_CLKP 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 S8_SATACLKP 11 11 12 12 J31 VERT-SM LS8_CLKN S8_CLKN BS08CLKN P16SH8_CLKN S8_SATACLKN 678005005 1 S8_SATACLKP S8_SATACLKN IN OUT IN IN 4 4 3 5 5 18 6 6 20 7 7 IN 21 MTG1 MTG1 MTG2 MTG2 2.00MM NO-SHROUD OUT OUT 21 OUT 39 21 HDR_2x6 19 S8_SATA_RSTN S8_SATA_WAKE 18 TP93 P8SH16_CLKP S16_CLKP BS16CLKP LS16_CLKP IN OUT IN IN 4 DNP 41 21 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 11 12 11 S16_SATACLKP IN 1 10 12 J33 VERT-SM P8SH16_CLKN S16_CLKN BS16CLKN LS16_CLKN 1 1 2 2 3 3 S16_SATACLKP S16_SATACLKN IN OUT IN IN 19 4 4 4 5 5 18 6 6 41 7 7 IN 21 MTG1 MTG1 MTG2 MTG2 S16_SATACLKN 2.00MM NO-SHROUD J35 S16_SATA_RSTN S16_SATA_WAKE 21 OUT OUT 21 OUT 39 DNP TP95 J37 C C 678005005 HDR_2x6 19 3 18 20 21 IN OUT IN IN IN P8SH12_CLKP S12_CLKP BS12CLKP P16SH12_CLKP 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 11 S12_SATACLKP VERT-SM 11 12 J32 P8SH12_CLKN S12_CLKN BS12CLKN P16SH12_CLKN 10 12 S12_SATACLKN 678005005 1 1 2 2 3 3 IN OUT IN IN 19 4 4 3 5 5 18 6 6 20 7 7 IN 21 2.00MM NO-SHROUD S12_SATACLKP S12_SATACLKN OUT OUT 21 21 19 4 S12_SATA_RSTN S12_SATA_WAKE OUT 39 18 DNP TP94 MTG1 MTG1 MTG2 MTG2 1 1 2 2 3 3 4 4 5 5 6 6 7 7 HDR_2x6 20 21 P8SH20_CLKP S20_CLKP BS20CLKP P16SH20_CLKP IN OUT IN IN 1 1 3 3 5 6 6 7 7 8 8 9 11 S20_SATACLKP IN 4 4 5 9 10 10 11 VERT-SM 12 12 J34 P8SH20_CLKN S20_CLKN BS20CLKN P16SH20_CLKN 2 2 S20_SATACLKN IN OUT IN IN 19 IN 21 4 18 20 2.00MM NO-SHROUD J36 S20_SATACLKP S20_SATACLKN S20_SATA_RSTN S20_SATA_WAKE OUT OUT 21 OUT 39 21 DNP TP96 MTG1 MTG1 MTG2 MTG2 J38 B B 678005005 J66 J67 CONNSMA CONNSMA 5 4 4 5 1 1 2 3 3 221789-0 678005005 1 1 2 2 3 3 4 4 5 5 6 6 7 7 G0_SATACLKP G0_SATACLKN OUT OUT J20 21 J17 21 CONNSMA CONNSMA 5 1 2 221789-0 MTG1 MTG2 MTG2 5 1 2 MTG1 4 4 3 3 221789-0 18 A 21 OUT IN IN HDR_2x5 GCLK0P BGCLK0P G0_SATACLKP 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 VERT-SM J18 10 GCLK0N BGCLK0N G0_SATACLKN 1 2 2 3 3 4 4 5 5 6 6 7 7 G1_SATACLKP G1_SATACLKN OUT OUT 21 21 2 221789-0 J21 6 1 MTG1 MTG1 MTG2 MTG2 J22 OUT 6 6 IN 18 18 IN 21 21 GCLK1P OUT BGCLK1P IN G1_SATACLKP IN HDR_2x5 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 VERT-SM 2.00MM NO-SHROUD J19 GCLK1N OUT BGCLK1N G1_SATACLKN 10 6 IN 18 IN 21 A 2.00MM NO-SHROUD TITLE EB-LOGAN-19 CLOCK SELECTOR SLOTS 8-20, GCLK SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:49 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 21 OF 41 1 7 6 5 4 3 2 1 3 8 MINIMUM POWER SUPPLY LOADS C R506 W27 1K 0603 MMBT3904 1 U98 5% B 2 E D D +12V3_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS SPDT_TGL A ON S1 +12V3_PS 1% 1% R1121 1% R1117 1% R1113 R1109 1% 1% R1105 1% R1101 1% R1097 R1093 1% 1% R1089 1% R1085 1% R1081 R1077 1% 1% R1074 1% R1071 1% R1068 R1065 1% 1% R1060 1% R1056 1% R1052 715 715 715 715 715 715 715 715 715 715 715 715 715 715 715 715 715 715 715 715 1% R1123 124 1% 1% R1118 R1122 124 124 1% 1% R1114 124 R1110 124 1% 1% R1106 124 R1102 +5V0_PS 124 1% 1% R1094 R1098 124 124 1% R1090 124 1% R1086 +5V0_PS 124 1% 1% R1078 R1082 124 124 1% 1% R1062 53.6 53.6 R1061 +5V0_PS 1% 1% R1057 53.6 1% R1053 53.6 1% R1049 53.6 53.6 R1045 +3V3_PS 1% 1% R1033 25V +3V3_PS 53.6 47UF 22UF C321 RIGHT ANGLED R1041 24 C320 25V 23 J69 C317 C316 22 47UF 22UF 10UF C315 12 C 21 53.6 11 20 R1037 10 19 53.6 9 18 R508 C 17 150 8 16 DS2 7 15 GRN 6 14 R507 5 13 +3.3V_4 -12V_1 GND_4 PS-ON GND_5 GND_6 GND_7 -5V +5V_3 +5V_4 +5V_5 GND_8 330 4 +3.3V_1 +3.3V_2 GND_1 +5V_1 GND_2 +5V_2 GND_3 PWROK +5VAB +12V3_1 +12V3_2 +3.3V_3 DS1 2 GRN 1 3 715 0039291247 715 +3V3_PS 715 +3V3_PS R1048 +5V0_PS 1% 5 1% MTG1 MTG2 1% OFF +5V0_PS 37 R1044 OUT 1% PS_ENABLEN 4 R1040 2 1% B R1032 +12V3_PS R1036 COM 3 715 1 +3V3 B B +12.0V -> +3.3V VR1 Track 1 SYNC YEL 9 TURBOTRANS YEL 11 VO_SEN- 7 +3V3_PS C324 C326 C328 C330 C332 C334 C337 C340 C342 C344 C346 C348 C350 C352 C354 C356 C358 C360 C362 C364 C367 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF GRN 47UF 47UF 47UF 3 PTH08T240WAD C322 4 GND1 47UF GND2 10V Vo_Adj 150 Inhibit DS4 1% R509 8 5 1.21K 0603 25V C336 C339 22UF 22UF 25V TP29 Vout 220UF TP28 6 R57 VO_SEN+ C369 10 Vin C366 2 A A WHT TP32 WHT TP31 WHT TP30 WHT TP27 WHT TP26 WHT TP25 WHT TP24 WHT TP23 WHT TP22 WHT TP18 TP21 TP17 WHT TP16 TP20 GND TEST POINTS SCATTER AROUND BOARD TITLE EB-LOGAN-19 POWER CONNECTORS, MIN LOAD RESISTORS SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:50 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 22 OF 41 1 8 7 6 5 4 3 2 1 +12V3_PS +3V3 VDD_IO, 3.3V D D CONN BANANA VIN1 VOUT1 J1 A2 VIN2 VOUT2 J2 A3 VIN3 VOUT3 J3 A4 VIN4 VOUT4 J4 A5 VIN5 VOUT5 J5 A6 VIN6 VOUT6 J6 CONN BANANA B1 VIN7 VOUT7 J7 BLK B2 VIN8 VOUT8 J8 J79 B3 VIN9 VOUT9 J9 B4 VIN10 L5 VOUT27 L6 VOUT28 L7 VOUT29 L8 VOUT30 L9 VOUT31 L10 VOUT32 L11 VOUT33 M1 VOUT34 M2 VOUT35 M3 VOUT36 M4 VOUT37 M5 VOUT38 M6 VOUT39 M7 VOUT40 M8 C383 S9 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 PS_IO_MARG0 11 PS_IO_MARG1 10 PS_IO_CTRL3 9 PS_IO_CTRL2 8 PS_IO_CTRL1 7 PS_IO_CTRL0 487K 487K R517 487K R519 R518 8% 4% MARGINING CONTROL 1.96M 1.96M 1.96M MARG0 VOUT41 M9 D12 MARG1 VOUT42 M10 VOUT43 M11 H12 SM_SW6 1 C12 A12 DNP B MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN R520 R521 R522 A 2% 1% TRACK/SS MPGM SGND VFB F12 VOSNSP J12 VOSNSN M12 D1 GND1 D2 GND2 D3 GND3 D4 GND4 D5 GND5 D6 GND6 E1 GND7 E2 GND8 E3 GND9 E4 GND10 E5 GND11 GND26 G4 E6 GND12 GND27 G5 E7 GND13 GND28 G6 F1 GND14 GND29 G7 F2 GND15 GND30 G8 F3 GND16 GND31 G9 F4 GND17 GND32 H1 F5 GND18 GND33 H2 F6 GND19 GND34 H3 F7 GND20 GND35 H4 F8 GND21 GND36 H5 F9 GND22 GND37 H6 G1 GND23 GND38 H7 G2 GND24 GND39 H8 G3 GND25 GND40 H9 FSET B R526 0 0 0 0 R527 R528 R529 PLACE R526 & R527 CLOSE TO U57, NOISE-FREE ROUTING PLACE R528 & R529 CLOSE TO U1, NOISE-FREE ROUTING R525 A9 VOUT_LCL B12 191K L12 DIFFVOUT C385 K12 PLLIN 0.01UF TP38 R524 A8 DRVCC 51.1K W33 R1390 10K 10K R1389 E12 INTVCC A TITLE U56 EB-LOGAN-19 POWER REGULATOR - VDDIO SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 7 6 5 2010 4 IDT 2.0 Derek Huang Thu Jun 10 11:24:50 2010 3 REV. 18-692-001 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 8 C396 L4 VOUT26 COMP 1.0UF L3 VOUT25 A7 C395 VOUT24 A11 TP37 C 10UF L2 6.5A PLACE CLOSE TO U1 R58 VOUT23 FB5 150 L1 26NH DS101 VOUT22 PGOOD REG_2V5_VDDIO GRN VOUT21 K11 C394 K10 C392 K9 VOUT20 RUN 0.1UF K8 VOUT19 1.0UF VOUT18 C391 VIN18 1.0UF C6 +3V3_IO ROUTE AS POWER NET OR ISLAND C390 K7 C389 K6 VIN17 VOUT17 47UF VOUT16 47UF K5 VIN16 C5 C388 VOUT15 C387 VIN15 C4 47UF K4 C3 47UF VOUT14 C386 VIN14 16V K3 C2 100UF K2 VOUT13 C384 VOUT12 1 100PF VOUT11 VIN12 VIN13 1 R523 100K 100K VIN11 C1 G12 PLACE W33 CLOSE TO J112 J10 B6 A10 DNP VOUT10 K1 +3V3 DNP J78 A1 B5 C RED 18.2K R516 R515 C381 10UF 10UF C380 LTM4603 2 SHEET 23 OF 41 1 8 7 6 5 4 3 2 1 +12V3_PS VDD_CORE, 1.0V +3V3 +3V3 CONN BANANA D RED R70 330 GRN DS117 J10 VIN11 VOUT11 K1 B6 VIN12 VOUT12 K2 C1 VIN13 VOUT13 K3 C2 VIN14 VOUT14 K4 C3 VIN15 VOUT15 K5 C4 VIN16 VOUT16 K6 C5 VIN17 VOUT17 K7 C6 VIN18 VOUT18 K8 VOUT19 K9 VOUT20 K10 VOUT21 K11 VOUT22 L1 VOUT23 L2 VOUT24 L3 VOUT25 L4 VOUT26 L5 VOUT27 L6 VOUT28 L7 VOUT29 L8 VOUT30 L9 VOUT31 L10 VOUT32 L11 VOUT33 M1 VOUT34 M2 VOUT35 M3 VOUT36 M4 VOUT37 M5 VOUT38 M6 VOUT39 M7 VOUT40 M8 DRVCC PLLIN PLACE W34 CLOSE TO J114 L12 A9 1 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 PS_CORE_MARG0 11 PS_CORE_MARG1 10 PS_CORE_CTRL3 9 PS_CORE_CTRL2 8 PS_CORE_CTRL1 7 PS_CORE_CTRL0 487K 487K R535 487K R537 1.96M 1.96M 1.96M A MARG0 VOUT41 M9 MARG1 VOUT42 M10 VOUT43 M11 R536 8% 4% R538 R539 R540 MARGINING CONTROL 2% 1% 3 MPGM SGND VFB F12 VOSNSP J12 VOSNSN M12 D1 GND1 D2 GND2 D3 GND3 D4 GND4 D5 GND5 D6 GND6 E1 GND7 E2 GND8 E3 GND9 E4 GND10 E5 GND11 GND26 G4 E6 GND12 GND27 G5 E7 GND13 GND28 G6 F1 GND14 GND29 G7 F2 GND15 GND30 G8 F3 GND16 GND31 G9 F4 GND17 GND32 H1 F5 GND18 GND33 H2 F6 GND19 GND34 H3 F7 GND20 GND35 H4 F8 GND21 GND36 H5 F9 GND22 GND37 H6 G1 GND23 GND38 H7 G2 GND24 GND39 H8 G3 GND25 GND40 H9 FSET B12 B R544 0 0 R541 C400 S6 TRACK/SS D12 H12 SM_SW6 VOUT_LCL C12 A12 DNP B MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN DIFFVOUT 1% K12 0 0 R545 R546 R547 PLACE R544 & R545 CLOSE TO U57, NOISE-FREE ROUTING PLACE R546 & R547 CLOSE TO U1, NOISE-FREE ROUTING R543 DNP TP42 INTVCC A TITLE U59 EB-LOGAN-19 POWER REGULATOR - VDDCORE SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 7 6 5 2010 4 IDT 2.0 CHECKED BY Thu Jun 10 11:24:51 2010 3 REV. 18-692-001 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 8 C PLACE CLOSE TO U1 191K A8 COMP FB6 6.5A C402 W34 R1392 E12 10K 10K R1391 A7 26NH 0.01UF A11 DNP TP41 PGOOD REG_1V0_CORE R542 G12 RUN 316K A10 +1V0_CORE ROUTE AS POWER NET OR ISLAND C413 VOUT10 C412 VIN10 B5 10UF J9 B4 1.0UF J8 VOUT9 2 VOUT8 VIN9 C411 VIN8 B3 C409 B2 1 0.1UF J7 1.0UF VOUT7 C408 VIN7 1.0UF B1 J113 E C407 VOUT6 BLK B 1% R534 100K R533 100K VIN6 J6 C406 J5 47UF VOUT5 CONN BANANA MMBT3904 U3 47UF VIN5 A6 C 1 C405 J4 C404 VOUT4 47UF VIN4 47UF J3 A4 C403 VOUT3 16V VIN3 100UF J2 A3 C401 J1 VOUT2 100PF VOUT1 VIN2 127K C398 C397 10UF 10UF VIN1 A2 +3V3 C 1 A1 A5 D J114 LTM4603 2 SHEET 24 OF 41 1 8 7 6 5 4 3 2 1 +12V3_PS VDD_PEA, 1.0V +3V3 +3V3 CONN BANANA D RED R81 330 GRN DS133 VIN10 VOUT10 J10 B5 VIN11 VOUT11 K1 B6 VIN12 VOUT12 K2 C1 VIN13 VOUT13 K3 C2 VIN14 VOUT14 K4 C3 VIN15 VOUT15 K5 C4 VIN16 VOUT16 K6 C5 VIN17 VOUT17 K7 C6 VIN18 VOUT18 K8 VOUT19 K9 VOUT20 K10 VOUT21 K11 VOUT22 L1 VOUT23 L2 VOUT24 L3 VOUT25 L4 VOUT26 L5 VOUT27 L6 VOUT28 L7 VOUT29 L8 VOUT30 L9 VOUT31 L10 VOUT32 L11 VOUT33 M1 VOUT34 M2 VOUT35 M3 VOUT36 M4 VOUT37 M5 VOUT38 M6 VOUT39 M7 VOUT40 M8 C417 S7 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 PS_PEA_MARG0 11 PS_PEA_MARG1 10 PS_PEA_CTRL3 9 PS_PEA_CTRL2 8 PS_PEA_CTRL1 7 PS_PEA_CTRL0 487K 487K R553 487K R555 1.96M 1.96M 1.96M A MARG0 VOUT41 M9 D12 MARG1 VOUT42 M10 VOUT43 M11 H12 SM_SW6 1 C12 A12 DNP B MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN R554 8% 4% R556 R557 R558 MARGINING CONTROL 2% 1% TRACK/SS MPGM SGND VFB F12 VOSNSP J12 VOSNSN M12 D1 GND1 D2 GND2 D3 GND3 D4 GND4 D5 GND5 D6 GND6 E1 GND7 E2 GND8 E3 GND9 E4 GND10 E5 GND11 GND26 G4 E6 GND12 GND27 G5 E7 GND13 GND28 G6 F1 GND14 GND29 G7 F2 GND15 GND30 G8 F3 GND16 GND31 G9 F4 GND17 GND32 H1 F5 GND18 GND33 H2 F6 GND19 GND34 H3 F7 GND20 GND35 H4 F8 GND21 GND36 H5 F9 GND22 GND37 H6 G1 GND23 GND38 H7 G2 GND24 GND39 H8 G3 GND25 GND40 H9 FSET B12 B R562 0 0 1% A9 VOUT_LCL 0 0 R563 R564 R565 PLACE R562 & R563 CLOSE TO U60, NOISE-FREE ROUTING PLACE R564 & R565 CLOSE TO U1, NOISE-FREE ROUTING R561 L12 DIFFVOUT 191K K12 PLLIN A TITLE U62 EB-LOGAN-19 POWER REGULATOR - VDDPEA SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 7 6 5 2010 4 IDT 2.0 CHECKED BY Thu Jun 10 11:24:51 2010 3 REV. 18-692-001 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 8 C PLACE CLOSE TO U1 C419 PLACE W35 CLOSE TO J115 DRVCC FB7 0.01UF DNP TP46 INTVCC R560 A8 COMP R559 W35 R1394 E12 10K 10K R1393 A7 26NH 6.5A 316K A11 DNP TP45 PGOOD REG_1V0_PEA 1% G12 RUN +1V0_PEA ROUTE AS POWER NET OR ISLAND C430 J9 B4 C429 VOUT9 10UF VIN9 1.0UF J8 B3 3 J7 VOUT8 2 VOUT7 VIN8 C428 VIN7 B2 C426 B1 U12 E 0.1UF J6 1.0UF VOUT6 C425 VIN6 1.0UF A6 MMBT3904 B C424 J5 C423 VOUT5 47UF VIN5 47UF A5 C 1 C422 J4 C421 VOUT4 47UF VIN4 47UF J3 A4 C420 VOUT3 16V VIN3 100UF J2 A3 C418 J1 VOUT2 100PF VOUT1 VIN2 127K 100K R551 100K R552 C415 C414 10UF 10UF VIN1 A2 A10 C 1 A1 +3V3 D J115 LTM4603 2 SHEET 25 OF 41 1 8 7 6 5 4 3 2 1 +12V3_PS VDD_PEHA, 2.5V +3V3 +3V3 CONN BANANA D RED R82 330 GRN DS134 VIN10 VOUT10 J10 B5 VIN11 VOUT11 K1 B6 VIN12 VOUT12 K2 C1 VIN13 VOUT13 K3 C2 VIN14 VOUT14 K4 C3 VIN15 VOUT15 K5 C4 VIN16 VOUT16 K6 C5 VIN17 VOUT17 K7 C6 VIN18 VOUT18 K8 VOUT19 K9 VOUT20 K10 VOUT21 K11 VOUT22 L1 VOUT23 L2 VOUT24 L3 VOUT25 L4 VOUT26 L5 VOUT27 L6 VOUT28 L7 VOUT29 L8 VOUT30 L9 VOUT31 L10 VOUT32 L11 VOUT33 M1 VOUT34 M2 VOUT35 M3 VOUT36 M4 VOUT37 M5 VOUT38 M6 VOUT39 M7 VOUT40 M8 L12 A9 C434 S8 1 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 PS_PEHA_MARG0 11 PS_PEHA_MARG1 10 PS_PEHA_CTRL3 9 PS_PEHA_CTRL2 8 PS_PEHA_CTRL1 7 PS_PEHA_CTRL0 487K 487K R571 487K R573 1.96M 1.96M 1.96M A R572 8% 4% R574 R575 R576 MARGINING CONTROL 2% 1% TRACK/SS MARG0 VOUT41 M9 D12 MARG1 VOUT42 M10 VOUT43 M11 H12 SM_SW6 VOUT_LCL C12 A12 DNP B MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN DIFFVOUT MPGM SGND VFB F12 VOSNSP J12 VOSNSN M12 D1 GND1 D2 GND2 D3 GND3 D4 GND4 D5 GND5 D6 GND6 E1 GND7 E2 GND8 E3 GND9 E4 GND10 E5 GND11 GND26 G4 E6 GND12 GND27 G5 E7 GND13 GND28 G6 F1 GND14 GND29 G7 F2 GND15 GND30 G8 F3 GND16 GND31 G9 F4 GND17 GND32 H1 F5 GND18 GND33 H2 F6 GND19 GND34 H3 F7 GND20 GND35 H4 F8 GND21 GND36 H5 F9 GND22 GND37 H6 G1 GND23 GND38 H7 G2 GND24 GND39 H8 G3 GND25 GND40 H9 FSET B R580 0 0 0 0 R581 R582 R583 PLACE R580 & R581 CLOSE TO U63, NOISE-FREE ROUTING PLACE R582 & R583 CLOSE TO U1, NOISE-FREE ROUTING R579 K12 PLLIN B12 DNP PLACE W36 CLOSE TO J116 DRVCC A TITLE U65 EB-LOGAN-19 POWER REGULATOR - VDDPEHA SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 7 6 5 2010 4 IDT 2.0 CHECKED BY Thu Jun 10 11:24:51 2010 3 REV. 18-692-001 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 8 C PLACE CLOSE TO U1 C436 DNP TP50 INTVCC FB8 0.01UF A8 COMP R578 W36 R1396 E12 10K 10K R1395 A7 26NH 6.5A 34.8K A11 DNP TP49 PGOOD REG_2V5_PEHA R577 G12 RUN +2V5_PEHA ROUTE AS POWER NET OR ISLAND C447 J9 B4 C446 VOUT9 10UF VIN9 1.0UF J8 B3 3 J7 VOUT8 2 VOUT7 VIN8 C445 VIN7 B2 C443 B1 U13 E 0.1UF J6 1.0UF VOUT6 C442 VIN6 1.0UF A6 MMBT3904 B C441 J5 C440 VOUT5 47UF VIN5 47UF A5 C 1 C439 J4 C438 VOUT4 47UF VIN4 47UF J3 A4 C437 VOUT3 16V VIN3 100UF J2 A3 C435 J1 VOUT2 100PF VOUT1 VIN2 42.2K 100K R569 100K R570 C432 C431 10UF 10UF VIN1 A2 A10 C 1 A1 +3V3 D J116 LTM4603 2 SHEET 26 OF 41 1 8 7 6 5 4 3 2 1 +12V3_PS VDD_PETA, 1.0V +3V3 +3V3 CONN BANANA D RED R93 330 GRN DS135 VIN10 VOUT10 J10 B5 VIN11 VOUT11 K1 B6 VIN12 VOUT12 K2 C1 VIN13 VOUT13 K3 C2 VIN14 VOUT14 K4 C3 VIN15 VOUT15 K5 C4 VIN16 VOUT16 K6 C5 VIN17 VOUT17 K7 C6 VIN18 VOUT18 K8 VOUT19 K9 VOUT20 K10 VOUT21 K11 VOUT22 L1 VOUT23 L2 VOUT24 L3 VOUT25 L4 VOUT26 L5 VOUT27 L6 VOUT28 L7 VOUT29 L8 VOUT30 L9 VOUT31 L10 VOUT32 L11 VOUT33 M1 VOUT34 M2 VOUT35 M3 VOUT36 M4 VOUT37 M5 VOUT38 M6 VOUT39 M7 VOUT40 M8 2 3 4 5 6 S1B S2A S2B S3A S3B S4A S4B S5A S5B S6A S6B 12 PS_PETA_MARG0 11 PS_PETA_MARG1 10 PS_PETA_CTRL3 9 PS_PETA_CTRL2 8 PS_PETA_CTRL1 7 PS_PETA_CTRL0 M9 VOUT42 M10 VOUT43 M11 MPGM D1 GND1 D2 GND2 D3 GND3 D4 GND4 D5 GND5 F12 VOSNSP J12 VOSNSN M12 D6 GND6 R589 E1 GND7 R590 E2 GND8 E3 GND9 E4 GND10 487K R591 E5 GND11 GND26 G4 E6 GND12 GND27 G5 E7 GND13 GND28 G6 F1 GND14 GND29 G7 F2 GND15 GND30 G8 F3 GND16 GND31 G9 F4 GND17 GND32 H1 F5 GND18 GND33 H2 F6 GND19 GND34 H3 F7 GND20 GND35 H4 F8 GND21 GND36 H5 F9 GND22 GND37 H6 G1 GND23 GND38 H7 G2 GND24 GND39 H8 G3 GND25 GND40 H9 1.96M 8% 4% R592 R593 2% R594 1% MARGINING CONTROL FSET B12 B R598 0 0 R595 SGND VFB 487K 487K 1.96M 1.96M A VOUT41 MARG1 C451 S10 S1A MARG0 D12 H12 SM_SW6 1 TRACK/SS C12 A12 DNP B MARG1 | MARG0 | MODE -----------------------------LOW | LOW | NO MARGIN -----------------------------LOW | HIGH | MARGIN UP -----------------------------HIGH | LOW | MARGIN DOWN -----------------------------HIGH | HIGH | NO MARGIN VOUT_LCL R597 A9 DIFFVOUT 0 0 R599 R600 R601 PLACE R598 & R599 CLOSE TO U66, NOISE-FREE ROUTING PLACE R600 & R601 CLOSE TO U1, NOISE-FREE ROUTING 191K L12 PLLIN A TITLE U68 EB-LOGAN-19 POWER REGULATOR - VDDPETA SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 7 6 5 2010 4 IDT 2.0 Derek Huang Thu Jun 10 11:24:52 2010 3 REV. 18-692-001 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 8 C PLACE CLOSE TO U1 C453 K12 PLACE W37 CLOSE TO J117 DRVCC FB9 0.01UF DNP TP54 INTVCC 1% A8 COMP 1% W37 R1398 E12 10K 10K R1397 A7 26NH 6.5A R596 A11 DNP TP53 PGOOD REG_1V0_PETA 316K G12 RUN +1V0_PETA ROUTE AS POWER NET OR ISLAND C464 J9 B4 C463 VOUT9 10UF VIN9 1.0UF J8 B3 3 J7 VOUT8 2 VOUT7 VIN8 C462 VIN7 B2 0.1UF B1 U14 E C460 J6 1.0UF VOUT6 C459 VIN6 C458 A6 MMBT3904 B 47UF J5 1.0UF VOUT5 C457 VIN5 47UF A5 C 1 C456 J4 C455 VOUT4 47UF VIN4 47UF J3 A4 C454 VOUT3 16V VIN3 100UF J2 A3 C452 J1 VOUT2 100PF VOUT1 VIN2 127K 100K R587 100K R588 C449 C448 10UF 10UF VIN1 A2 A10 C 1 A1 +3V3 D J117 LTM4603 2 SHEET 27 OF 41 1 8 7 6 5 4 3 2 1 +3V3 5% R641 +3V3 +3V3 +3V3 A 3 GND 5 Y 4 TLC7733D 2 7 1 C489 VCC RESET RESETN GND TP61 8 6 R644 1K 0603 5 MAIN_RSTN 5% 4 U73 0.1UF C487 RESET 0.1UF FUNDAMENTAL 0.1UF 3 RESINN SENSE CONTROL CT YEL 5% R646 5% +3V3 10K 0402 2 VCC 6 OUT 39 DS3 OE_N D RED 1 C491 SATAIN_RSTN IN R642 U72 SN74LVC1G125 1K 0603 17 TP60 D YEL 10.0K 0603 +3V3 SPDT_MOM A 3 NC COM C 1 MOMSW_RSTN C 2 B NO MTG1 MTG2 4 5 S3 +3V3 +3V3 11 10 9 8 6 5 3 2 1 SCL SDA VCC A2 A1 A0 WP GND 6 8 7 6 R662 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 4 VERT-TH 5% 12 6 5% 13 IN BI MSMBCLK MSMBDAT 1 DUT_JTAG_TRST_N DUT_JTAG_TDI DUT_JTAG_TDO DUT_JTAG_TMS DUT_JTAG_TCK R661 6 OUT OUT IN BI BI R659 8 6 0.1UF 9 6 C499 1% R658 10 DNP 0603 11 1K 0603 DNP DNP DNP 12 JTAG HDR_2x7 6 24LC512 13 B 1K 0603 +3V3 B 5% R660 R1335 R1334 R1333 SOCKETED (52-298-000) 5% +3V3 BOOT EEPROM J73 14 2.54MM SHROUD 1K 0603 1K 0603 U77 A0-2 INTERNALLY PULLED DOWN +3V3 5% R651 5% A R649 A 1K 0603 EB-LOGAN-19 RESET, SMBUS, EEPROM, JTAG SSMBCLK J71 1K 0603 TITLE OUT 6 SIZE SSMBDAT BI 6 B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:52 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 28 OF 41 1 8 7 6 5 4 3 2 1 R1357 R1354 R1348 R1345 R1351 (GREEN) ACTIVE HIGH - DIP STK2CFG D DIPSW8 B5 A6 B6 A7 B7 A8 B8 OFF ON 13 12 11 10 9 3 6 29 3 6 29 6 29 6 29 6 29 29 6 IN 29 6 3 IN 29 6 3 IN STK2CFG3 150 R797 GRN DS103 STK2CFG2 150 R798 GRN DS104 STK2CFG1 150 R799 GRN DS105 STK2CFG0 150 R800 GRN DS106 +3V3 DNP TP106 DNP TP4 DNP TP6 SW8 R1367 8 B4 A5 14 OUT OUT OUT OUT OUT DS102 R1366 7 A4 15 STK2CFG0 STK2CFG1 STK2CFG2 STK2CFG3 STK2CFG4 SPARE1 SPARE2 SPARE3 GRN R1365 6 B3 IN R796 R1364 5 B2 A3 6 150 R1363 4 A2 16 29 STK2CFG4 R1362 3 B1 IN R1361 2 A1 6 R1360 1 29 1K 1K 1K 1K 1K 1K 1K 1K STK2CFG R1342 D R1339 R1336 +3V3 1K 1K 1K 1K 1K 1K 1K 1K +3V3 R1358 R1355 R1352 R1349 R1346 R1343 R1340 R1337 C (GREEN) ACTIVE HIGH - DIP STK3CFG 1 2 DIPSW8 1 2 3 4 5 6 7 8 B1 A1 B2 A2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 OFF ON 16 15 14 13 12 11 10 9 29 6 29 6 IN 29 6 IN IN 1K 1K 1K 1K 1K 1K 1K 1K STK3CFG STK3CFG0 STK3CFG1 STK3CFG2 STK3CFG3 STK3CFG4 SPARE4 SPARE5 SPARE6 OUT OUT OUT OUT OUT 4 6 4 6 6 29 6 29 6 29 STK3CFG4 150 R812 GRN DS118 STK3CFG3 150 R813 GRN DS119 STK3CFG2 150 R814 GRN DS120 3 4 5 6 7 8 29 29 29 29 6 6 4 4 IN IN STK3CFG1 150 STK3CFG0 150 C DIPSW8 R815 R816 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 OFF ON 16 15 14 13 12 11 10 9 ICS_FS GCLKFSEL ICS_SSM RSTHALT SSMBADDR2 SSMBADDR1 CLKMODE1 CLKMODE0 DS121 GRN DS122 GRN 17 OUT OUT OUT OUT OUT OUT OUT OUT 6 29 29 17 29 6 29 6 29 6 29 6 29 6 29 SW10 DNP TP107 DNP TP7 DNP TP8 SW9 (GREEN) ACTIVE HIGH - DIP CLOCK +3V3 B 29 17 IN 6 IN 17 IN R1359 R1356 R1353 R1350 R1347 R1344 R1341 29 (GREEN) ACTIVE HIGH - DIP MODE 29 6 IN 29 6 IN 29 6 IN 1K 1K 1K 1K 1K 1K 1K 1K R1338 29 SM_SW4 1 2 3 4 S1A S1B S2A S2B S3A S3B S4A S4B 8 7 6 5 G1 G2 G3 SPARE7 OUT OUT OUT 6 29 6 29 6 29 DNP TP3 S4 29 6 IN 29 6 IN 29 6 IN SWMODE 29 6 IN G3 150 R819 YEL DS125 G2 150 R820 YEL DS126 G1 150 R821 YEL DS127 SWMODE3 150 R823 GRN DS129 SWMODE2 150 R824 GRN DS130 SWMODE1 150 R825 GRN DS131 150 R826 GRN DS132 SWMODE0 29 6 IN 29 6 IN 29 6 IN 29 6 IN 29 6 IN ICS_FS 150 R803 GRN DS109 GCLKFSEL 150 R804 GRN DS110 ICS_SSM 150 R805 GRN DS111 RSTHALT 150 R806 GRN DS112 SSMBADDR2 150 R807 GRN DS113 SSMBADDR1 150 R808 GRN DS114 CLKMODE1 150 R809 GRN DS115 CLKMODE0 150 R810 GRN DS116 B SM_SW4 A 1 2 3 4 S1A S1B S2A S2B S3A S3B S4A S4B 8 7 6 5 SWMODE0 SWMODE1 SWMODE2 SWMODE3 OUT OUT OUT OUT 6 29 6 29 6 29 6 29 A S5 TITLE EB-LOGAN-19 DIP SWITCHES SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:52 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 29 OF 41 1 4 TP88 5 3 2 1 +3V3 YEL TP87 YEL TP86 YEL TP85 YEL TP84 YEL TP83 YEL TP82 6 YEL YEL YEL TP81 7 TP80 8 (YELLOW) ACTIVE LOW - GPIO D 6 BI 6 BI 6 BI 6 BI 6 BI 6 6 6 IN OUT BI GPIO0 150 R1368 DS406 YEL GPIO1 150 R1369 DS407 YEL GPIO2 150 R1370 DS408 YEL GPIO3 150 R1371 DS409 YEL GPIO4 150 R1372 DS410 YEL GPIO5 150 R1373 DS411 YEL 150 R1375 DS413 YEL 150 R1376 DS414 YEL TP19 GPIO6 GPIO7 W1 6 BI GPIO8 IOEXPINTN IN 8 9 10 11 12 GPIO | ALT0 | ALT1 ----------------------------------0 | PART0PERSTN | P16LINKUPN ----------------------------------1 | PART1PERSTN | P16ACTIVEN ----------------------------------2 | PART2PERSTN | P4LINKUPN ----------------------------------3 | PART3PERSTN | P4ACTIVEN ----------------------------------4 | FAILOVER0 | P0LINKUPN ----------------------------------5 | GPEN | P0ACTIVEN ----------------------------------6 | FAILOVER1 | FAILOVER3 ----------------------------------7 | FAILOVER2 | P8LINKUPN ----------------------------------8 | IOEXPINTN | P8ACTIVEN | W1:1-2 | W1:2-3 D +3V3 13 (YELLOW) ACTIVE LOW - PRESENCE DETECT C 37 +3V3 10 37 37 (ORANGE) ACTIVE LOW - ATTENTION INPUT 37 8 37 10 IN P23_APN 1K R852 DS158 ORG IN P22_APN 1K R853 DS159 ORG PORT 23 IN P21_APN 1K R854 DS160 ORG IN P20_APN 1K R855 DS161 ORG 10 PORT 21 37 8 8 IN P19_APN 1K R856 DS162 ORG 10 PORT 10 37 9 B IN P18_APN 1K R857 DS163 ORG IN 8 IN P17_APN 1K R858 DS164 ORG PORT 17 P16_APN 1K R859 DS165 ORG PORT 16 37 8 37 10 IN P15_APN 1K R860 DS166 ORG IN P14_APN 1K R861 DS167 ORG 10 IN 8 IN 1K R862 DS168 ORG PORT 13 P12_APN 1K R863 DS169 ORG PORT 12 37 10 9 10 8 9 8 A IN IN IN IN IN IN 9 IN 8 IN 9 IN 8 9 8 IN IN IN P11_APN 1K P10_APN 1K P9_APN 1K P8_APN 1K P7_APN 1K P6_APN 1K R864 R865 R866 R867 R868 R869 DS170 DS171 DS172 DS173 DS174 DS175 ORG ORG ORG ORG ORG ORG 8 9 37 9 37 8 37 9 37 8 37 9 P4_APN 1K R871 DS177 ORG PORT 4 P3_APN 1K R872 DS178 ORG PORT 3 P2_APN 1K R873 DS179 ORG PORT 2 P1_APN 1K R874 DS180 ORG PORT 1 P0_APN 1K R875 DS181 ORG PORT 0 IN IN IN IN IN IN IN IN 37 8 37 9 IN 37 8 IN PORT 6 PORT 5 IN IN PORT 7 ORG IN 3 PORT 8 DS176 IN IN PORT 9 R870 IN 10 PORT 10 1K IN IN PORT 11 P5_APN IN 3 PORT 14 P13_APN IN IN PORT 15 37 IN 10 10 37 9 9 PORT 18 37 10 4 PORT 20 37 10 9 PORT 22 37 10 4 10 37 9 9 10 IN IN C P23_PDN 150 R876 DS182 YEL PORT 23 P22_PDN 150 R877 DS183 YEL PORT 22 P21_PDN 150 R878 DS184 YEL PORT 21 P20_PDN 150 R879 DS185 YEL PORT 20 P19_PDN 150 R880 DS186 YEL PORT 19 P18_PDN 150 R881 DS187 YEL PORT 18 P17_PDN 150 R882 DS188 YEL PORT 17 P16_PDN 150 R883 DS189 YEL PORT 16 P15_PDN 150 R884 DS190 YEL PORT 15 P14_PDN 150 R885 DS191 YEL PORT 14 P13_PDN 150 R886 DS192 YEL PORT 13 P12_PDN 150 R887 DS193 YEL PORT 12 P11_PDN 150 R888 DS194 YEL PORT 11 P10_PDN 150 R889 DS195 YEL PORT 10 P9_PDN 150 R890 DS196 YEL PORT 9 P8_PDN 150 R891 DS197 YEL PORT 8 P7_PDN 150 R892 DS198 YEL PORT 7 P6_PDN 150 R893 DS199 YEL PORT 6 P5_PDN 150 R894 DS200 YEL PORT 5 P4_PDN 150 R895 DS201 YEL PORT 4 P3_PDN 150 R896 DS202 YEL PORT 3 P2_PDN 150 R897 DS203 YEL PORT 2 P1_PDN 150 R898 DS204 YEL PORT 1 P0_PDN 150 R899 DS205 YEL PORT 0 TITLE B EB-LOGAN-19 FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 6 5 2010 4 IDT 2.0 Derek Huang Thu Jun 10 11:24:53 2010 3 REV. 18-692-001 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 7 A LED - PORT STATUS (1 OF 7) SIZE 8 B 2 SHEET 30 OF 41 1 8 7 6 5 4 3 2 1 D D +3V3 +3V3 (GREEN) ACTIVE LOW - POWER GOOD (RED) ACTIVE LOW - POWER FAULT C C 37 37 37 37 15 37 37 37 37 15 37 37 37 B 37 14 37 37 37 37 IN 9 IN 10 8 10 IN IN IN 9 IN 10 IN 8 10 9 IN IN IN 10 IN 8 IN 10 IN 9 10 IN IN 14 8 IN 37 9 IN 37 8 37 9 37 A 10 8 IN IN IN 37 9 IN 37 8 IN 37 9 37 8 IN IN P23_PFN 1K R663 DS5 RED PORT 23 P22_PFN 1K R664 DS6 RED PORT 22 P21_PFN 1K R665 DS7 RED PORT 21 P20_PFN 1K R666 DS8 RED PORT 20 P19_PFN 1K R667 DS9 RED PORT 10 P18_PFN 1K R668 DS10 RED PORT 18 P17_PFN 1K R669 DS11 RED PORT 17 P16_PFN 1K R670 DS12 RED PORT 16 P15_PFN 1K R671 DS13 RED PORT 15 P14_PFN 1K R672 DS14 RED PORT 14 P13_PFN 1K R673 DS15 RED PORT 13 P12_PFN 1K R674 DS16 RED PORT 12 P11_PFN 1K R675 DS17 RED PORT 11 P10_PFN 1K R676 DS18 RED PORT 10 P9_PFN 1K R677 DS19 RED PORT 9 P8_PFN 1K R678 DS20 RED PORT 8 P7_PFN 1K R679 DS21 RED PORT 7 P6_PFN 1K R680 DS22 RED PORT 6 37 8 P5_PFN 1K R681 DS23 RED PORT 5 37 9 P4_PFN 1K R682 DS24 RED PORT 4 P3_PFN 1K R683 DS25 RED PORT 3 37 9 IN P2_PFN 1K R684 DS26 RED PORT 2 37 8 IN P1_PFN 1K R685 DS27 RED PORT 1 37 9 P0_PFN 1K R686 DS28 RED PORT 0 37 8 37 37 37 37 15 37 37 37 37 15 37 37 37 37 14 37 37 37 37 10 IN 9 IN 10 8 10 IN IN IN 9 IN 10 IN 8 10 9 IN IN IN 10 IN 8 IN 10 IN 9 10 IN IN 14 8 IN 37 9 IN 37 8 IN IN IN IN IN P23_PWRGDN 150 R687 DS29 GRN PORT 23 P22_PWRGDN 150 R688 DS30 GRN PORT 22 P21_PWRGDN 150 R689 DS31 GRN PORT 21 P20_PWRGDN 150 R690 DS32 GRN PORT 20 P19_PWRGDN 150 R691 DS33 GRN PORT 10 P18_PWRGDN 150 R692 DS34 GRN PORT 18 P17_PWRGDN 150 R693 DS35 GRN PORT 17 P16_PWRGDN 150 R694 DS36 GRN PORT 16 P15_PWRGDN 150 R695 DS37 GRN PORT 15 P14_PWRGDN 150 R696 DS38 GRN PORT 14 P13_PWRGDN 150 R697 DS39 GRN PORT 13 P12_PWRGDN 150 R698 DS40 GRN PORT 12 P11_PWRGDN 150 R699 DS41 GRN PORT 11 P10_PWRGDN 150 R700 DS42 GRN PORT 10 P9_PWRGDN 150 R701 DS43 GRN PORT 9 P8_PWRGDN 150 R702 DS44 GRN PORT 8 P7_PWRGDN 150 R703 DS45 GRN PORT 7 P6_PWRGDN 150 R704 DS46 GRN PORT 6 P5_PWRGDN 150 R705 DS47 GRN PORT 5 P4_PWRGDN 150 R706 DS48 GRN PORT 4 P3_PWRGDN 150 R707 DS49 GRN PORT 3 P2_PWRGDN 150 R708 DS50 GRN PORT 2 P1_PWRGDN 150 R709 DS51 GRN PORT 1 P0_PWRGDN 150 R710 DS52 GRN PORT 0 TITLE B A EB-LOGAN-19 LED - PORT STATUS (2 OF 7) SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:53 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 31 OF 41 1 8 7 6 5 4 3 2 1 D D +3V3 +3V3 (ORANGE) ACTIVE LOW - ATTENTION OUTPUT (GREEN) ACTIVE LOW - POWER INDICATOR C C 10 IN 9 IN 10 8 10 9 10 8 10 9 10 B IN IN IN IN IN IN IN IN 8 IN 10 IN 9 10 8 9 8 9 8 9 8 9 A IN 8 IN IN IN IN IN IN IN IN IN IN IN P23_AIN 1K R900 DS206 ORG PORT 23 10 IN P22_AIN 1K R901 DS207 ORG PORT 22 9 IN P21_AIN 1K R902 DS208 ORG PORT 21 10 P20_AIN 1K R903 DS209 ORG PORT 20 8 P19_AIN 1K R904 DS210 ORG PORT 10 10 P18_AIN 1K R905 DS211 ORG PORT 18 9 P17_AIN 1K R906 DS212 ORG PORT 17 10 P16_AIN 1K R907 DS213 ORG PORT 16 8 P15_AIN 1K R908 DS214 ORG PORT 15 10 P14_AIN 1K R909 DS215 ORG P13_AIN 1K R910 DS216 ORG PORT 13 10 P12_AIN 1K R911 DS217 ORG PORT 12 8 IN P11_AIN 1K R912 DS218 ORG PORT 11 10 IN P10_AIN 1K R913 DS219 ORG PORT 10 9 P9_AIN 1K R914 DS220 ORG PORT 9 10 P8_AIN 1K R915 DS221 ORG PORT 8 8 P7_AIN 1K R916 DS222 ORG PORT 7 9 P6_AIN 1K R917 DS223 ORG PORT 6 8 P5_AIN 1K R918 DS224 ORG PORT 5 9 P4_AIN 1K R919 DS225 ORG PORT 4 8 P3_AIN 1K R920 DS226 ORG PORT 3 9 P2_AIN 1K R921 DS227 ORG PORT 2 8 P1_AIN 1K R922 DS228 ORG PORT 1 9 P0_AIN 1K R923 DS229 ORG PORT 0 8 PORT 14 9 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN P23_PIN 150 R924 DS230 GRN PORT 23 P22_PIN 150 R925 DS231 GRN PORT 22 P21_PIN 150 R926 DS232 GRN PORT 21 P20_PIN 150 R927 DS233 GRN PORT 20 P19_PIN 150 R928 DS234 GRN PORT 10 P18_PIN 150 R929 DS235 GRN PORT 18 P17_PIN 150 R930 DS236 GRN PORT 17 P16_PIN 150 R931 DS237 GRN PORT 16 P15_PIN 150 R932 DS238 GRN PORT 15 P14_PIN 150 R933 DS239 GRN PORT 14 P13_PIN 150 R934 DS240 GRN PORT 13 P12_PIN 150 R935 DS241 GRN PORT 12 P11_PIN 150 R936 DS242 GRN PORT 11 P10_PIN 150 R937 DS243 GRN PORT 10 P9_PIN 150 R938 DS244 GRN PORT 9 P8_PIN 150 R939 DS245 GRN PORT 8 P7_PIN 150 R940 DS246 GRN PORT 7 P6_PIN 150 R941 DS247 GRN PORT 6 P5_PIN 150 R942 DS248 GRN PORT 5 P4_PIN 150 R943 DS249 GRN PORT 4 P3_PIN 150 R944 DS250 GRN PORT 3 P2_PIN 150 R945 DS251 GRN PORT 2 P1_PIN 150 R946 DS252 GRN PORT 1 P0_PIN 150 R947 DS253 GRN PORT 0 TITLE B A EB-LOGAN-19 LED - PORT STATUS (3 OF 7) SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:53 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 32 OF 41 1 8 7 6 5 4 3 2 1 D D +3V3 (GREEN) ACTIVE HIGH - POWER ENABLE (RED) ACTIVE LOW - HP SLOT RST C C 37 37 37 37 15 37 37 37 37 15 37 37 37 B 37 14 37 37 37 37 IN 9 IN 10 8 10 IN IN IN 9 IN 10 IN 8 10 9 IN IN IN 10 IN 8 IN 10 IN 9 10 IN IN 14 8 IN 37 9 IN 37 8 37 9 37 A 10 8 IN IN IN 37 9 IN 37 8 IN 37 9 37 8 IN IN P23_PEP 150 R711 GRN DS53 PORT 23 P22_PEP 150 R712 GRN DS54 PORT 22 P21_PEP 150 R713 GRN DS55 PORT 21 P20_PEP 150 R714 GRN DS56 PORT 20 P19_PEP 150 R715 GRN DS57 PORT 10 P18_PEP 150 R716 GRN DS58 PORT 18 P17_PEP 150 R717 GRN DS59 PORT 17 P16_PEP 150 R718 GRN DS60 PORT 16 P15_PEP 150 R719 GRN DS61 PORT 15 P14_PEP 150 R720 GRN DS62 PORT 14 P13_PEP 150 R721 GRN DS63 PORT 13 P12_PEP 150 R722 GRN DS64 PORT 12 P11_PEP 150 R723 GRN DS65 PORT 11 P10_PEP 150 R724 GRN DS66 PORT 10 P9_PEP 150 R725 GRN DS67 PORT 9 P8_PEP 150 R726 GRN DS68 PORT 8 16 13 8 IN P7_PEP 150 R727 GRN DS69 PORT 7 16 13 9 IN P6_PEP 150 R728 GRN DS70 PORT 6 16 13 8 P5_PEP 150 R729 GRN DS71 PORT 5 16 13 9 P4_PEP 150 R730 GRN DS72 PORT 4 16 13 8 P3_PEP 150 R731 GRN DS73 PORT 3 16 13 9 IN P2_PEP 150 R732 GRN DS74 PORT 2 16 13 8 IN P1_PEP 150 R733 GRN DS75 PORT 1 16 13 9 P0_PEP 150 R734 GRN DS76 PORT 0 16 13 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 10 IN 9 IN 10 8 10 IN IN IN 9 IN 10 IN 8 10 9 IN IN IN 10 IN 8 IN 10 IN 9 10 IN IN IN IN IN IN IN P23_RSTN 1K R735 DS77 RED PORT 23 P22_RSTN 1K R736 DS78 RED PORT 22 P21_RSTN 1K R737 DS79 RED PORT 21 P20_RSTN 1K R738 DS80 RED PORT 20 P19_RSTN 1K R739 DS81 RED PORT 10 P18_RSTN 1K R740 DS82 RED PORT 18 P17_RSTN 1K R741 DS83 RED PORT 17 P16_RSTN 1K R742 DS84 RED PORT 16 P15_RSTN 1K R743 DS85 RED PORT 15 P14_RSTN 1K R744 DS86 RED PORT 14 P13_RSTN 1K R745 DS87 RED PORT 13 P12_RSTN 1K R746 DS88 RED PORT 12 P11_RSTN 1K R747 DS89 RED PORT 11 P10_RSTN 1K R748 DS90 RED PORT 10 P9_RSTN 1K R749 DS91 RED PORT 9 P8_RSTN 1K R750 DS92 RED PORT 8 P7_RSTN 1K R751 DS93 RED PORT 7 P6_RSTN 1K R752 DS94 RED PORT 6 P5_RSTN 1K R753 DS95 RED PORT 5 P4_RSTN 1K R754 DS96 RED PORT 4 P3_RSTN 1K R755 DS97 RED PORT 3 P2_RSTN 1K R756 DS98 RED PORT 2 P1_RSTN 1K R757 DS99 RED PORT 1 P0_RSTN 1K R758 DS100 RED PORT 0 TITLE B A EB-LOGAN-19 LED - PORT STATUS (4 OF 7) SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:54 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 33 OF 41 1 8 7 6 5 4 3 2 1 D D +3V3 (GREEN) ACTIVE HIGH - INTERLOCK INPUT (RED) ACTIVE LOW - MRL C C 12 IN 11 IN 12 11 12 11 12 11 12 11 12 B IN IN IN IN IN IN IN IN 11 IN 12 IN 11 12 11 11 11 11 11 11 11 11 A IN 11 IN IN IN IN IN IN IN IN IN IN IN P23_ILOCKST 150 R948 GRN DS254 PORT 23 11 IN P22_ILOCKST 150 R949 GRN DS255 PORT 22 11 IN P21_ILOCKST 150 R950 GRN DS256 PORT 21 11 P20_ILOCKST 150 R951 GRN DS257 PORT 20 11 P19_ILOCKST 150 R952 GRN DS258 PORT 10 11 P18_ILOCKST 150 R953 GRN DS259 PORT 18 11 P17_ILOCKST 150 R954 GRN DS260 PORT 17 11 P16_ILOCKST 150 R955 GRN DS261 PORT 16 11 P15_ILOCKST 150 R956 GRN DS262 PORT 15 11 P14_ILOCKST 150 R957 GRN DS263 PORT 14 11 P13_ILOCKST 150 R958 GRN DS264 PORT 13 11 P12_ILOCKST 150 R959 GRN DS265 PORT 12 11 IN P11_ILOCKST 150 R960 GRN DS266 PORT 11 11 IN P10_ILOCKST 150 R961 GRN DS267 PORT 10 11 P9_ILOCKST 150 R962 GRN DS268 PORT 9 11 P8_ILOCKST 150 R963 GRN DS269 PORT 8 11 P7_ILOCKST 150 R964 GRN DS270 PORT 7 11 P6_ILOCKST 150 R965 GRN DS271 PORT 6 11 P5_ILOCKST 150 R966 GRN DS272 PORT 5 11 P4_ILOCKST 150 R967 GRN DS273 PORT 4 11 P3_ILOCKST 150 R968 GRN DS274 PORT 3 11 P2_ILOCKST 150 R969 GRN DS275 PORT 2 11 P1_ILOCKST 150 R970 GRN DS276 PORT 1 11 P0_ILOCKST 150 R971 GRN DS277 PORT 0 11 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN P23_MRLN 1K R972 DS278 RED PORT 23 P22_MRLN 1K R973 DS279 RED PORT 22 P21_MRLN 1K R974 DS280 RED PORT 21 P20_MRLN 1K R975 DS281 RED PORT 20 P19_MRLN 1K R976 DS282 RED PORT 10 P18_MRLN 1K R977 DS283 RED PORT 18 P17_MRLN 1K R978 DS284 RED PORT 17 P16_MRLN 1K R979 DS285 RED PORT 16 P15_MRLN 1K R980 DS286 RED PORT 15 P14_MRLN 1K R981 DS287 RED PORT 14 P13_MRLN 1K R982 DS288 RED PORT 13 P12_MRLN 1K R983 DS289 RED PORT 12 P11_MRLN 1K R984 DS290 RED PORT 11 P10_MRLN 1K R985 DS291 RED PORT 10 P9_MRLN 1K R986 DS292 RED PORT 9 P8_MRLN 1K R987 DS293 RED PORT 8 P7_MRLN 1K R988 DS294 RED PORT 7 P6_MRLN 1K R989 DS295 RED PORT 6 P5_MRLN 1K R990 DS296 RED PORT 5 P4_MRLN 1K R991 DS297 RED PORT 4 P3_MRLN 1K R992 DS298 RED PORT 3 P2_MRLN 1K R993 DS299 RED PORT 2 P1_MRLN 1K R994 DS300 RED PORT 1 P0_MRLN 1K R995 DS301 RED PORT 0 TITLE B A EB-LOGAN-19 LED - PORT STATUS (5 OF 7) SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:54 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 34 OF 41 1 8 7 6 5 4 3 2 +3V3 +3V3 (RED) ACTIVE LOW - PARTITION FUND. RESET D 1 (RED) ACTIVE LOW - SLOT HEADER RESET D 38 13 IN 38 13 IN 38 13 IN 38 13 38 13 IN 38 13 IN 38 13 IN 38 13 IN IN PART7_PERSTN 1K R1020 DS326 RED PART 7 39 38 6 4 IN PART6_PERSTN 1K R1021 DS327 RED PART 6 39 38 6 4 IN PART5_PERSTN 1K R1022 DS328 RED PART 5 39 38 6 3 PART4_PERSTN 1K R1023 DS329 RED PART 4 PART3_PERSTN 1K R1024 DS330 RED PART 3 PART2_PERSTN 1K R1025 DS331 RED PART 2 PART1_PERSTN 1K R1026 DS332 RED PART 1 PART0_PERSTN 1K R1027 DS333 RED PART 0 39 38 6 3 IN IN SLOT_HDR_RSTN20 1K R1650 DS415 RED SLOT 20 SLOT_HDR_RSTN16 1K R1651 DS416 RED SLOT 16 SLOT_HDR_RSTN12 1K R1652 DS417 RED SLOT 12 SLOT_HDR_RSTN8 1K R1653 DS418 RED SLOT 8 (GREEN) ACTIVE HIGH - INTERLOCK OUTPUT C 12 11 IN 12 IN 11 12 11 IN IN IN 11 IN 11 IN IN 12 IN 11 IN 12 IN 11 12 11 IN IN IN 11 IN 11 IN 11 11 11 11 A IN 12 12 B IN IN IN IN IN 11 IN 11 IN C P23_ILOCKP 150 R996 GRN DS302 PORT 23 P22_ILOCKP 150 R997 GRN DS303 PORT 22 P21_ILOCKP 150 R998 GRN DS304 PORT 21 P20_ILOCKP 150 R999 GRN DS305 PORT 20 P19_ILOCKP 150 R1000 GRN DS306 PORT 10 P18_ILOCKP 150 R1001 GRN DS307 PORT 18 P17_ILOCKP 150 R1002 GRN DS308 PORT 17 P16_ILOCKP 150 R1003 GRN DS309 PORT 16 P15_ILOCKP 150 R1004 GRN DS310 PORT 15 P14_ILOCKP 150 R1005 GRN DS311 PORT 14 P13_ILOCKP 150 R1006 GRN DS312 PORT 13 P12_ILOCKP 150 R1007 GRN DS313 PORT 12 P11_ILOCKP 150 R1008 GRN DS314 PORT 11 P10_ILOCKP 150 R1009 GRN DS315 PORT 10 P9_ILOCKP 150 R1010 GRN DS316 PORT 9 P8_ILOCKP 150 R1011 GRN DS317 PORT 8 P7_ILOCKP 150 R1012 GRN DS318 PORT 7 P6_ILOCKP 150 R1013 GRN DS319 PORT 6 P5_ILOCKP 150 R1014 GRN DS320 PORT 5 P4_ILOCKP 150 R1015 GRN DS321 PORT 4 P3_ILOCKP 150 R1016 GRN DS322 PORT 3 P2_ILOCKP 150 R1017 GRN DS323 PORT 2 P1_ILOCKP 150 R1018 GRN DS324 PORT 1 P0_ILOCKP 150 R1019 GRN DS325 PORT 0 B A TITLE EB-LOGAN-19 LED - PORT STATUS (6 OF 7) SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT CHECKED BY Thu Jun 10 11:24:54 2010 3 2.0 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 35 OF 41 1 8 7 6 5 4 3 2 1 D D +3V3 +3V3 (GREEN) ACTIVE LOW - LINK UP (BLUE) ACTIVE LOW - LINK ACTIVITY C C 12 IN 12 IN 12 12 12 12 12 12 12 12 B IN IN IN IN IN IN IN 12 IN 12 IN 12 IN 12 12 12 12 12 12 12 12 12 12 A IN 12 IN IN IN IN IN IN IN IN IN IN IN P23_LINKUPN 150 R1172 DS334 GRN PORT 23 12 IN P22_LINKUPN 150 R1173 DS335 GRN PORT 22 12 IN P21_LINKUPN 150 R1174 DS336 GRN PORT 21 12 P20_LINKUPN 150 R1175 DS337 GRN PORT 20 12 P19_LINKUPN 150 R1176 DS338 GRN PORT 10 12 P18_LINKUPN 150 R1177 DS339 GRN PORT 18 12 P17_LINKUPN 150 R1178 DS340 GRN PORT 17 12 P16_LINKUPN 150 R1179 DS341 GRN PORT 16 12 P15_LINKUPN 150 R1180 DS342 GRN PORT 15 12 P14_LINKUPN 150 R1181 DS343 GRN PORT 14 12 P13_LINKUPN 150 R1182 DS344 GRN PORT 13 12 IN P12_LINKUPN 150 R1183 DS345 GRN PORT 12 12 IN P11_LINKUPN 150 R1184 DS346 GRN PORT 11 12 IN P10_LINKUPN 150 R1185 DS347 GRN PORT 10 12 P9_LINKUPN 150 R1186 DS348 GRN P8_LINKUPN 150 R1187 DS349 GRN PORT 8 12 P7_LINKUPN 150 R1188 DS350 GRN PORT 7 12 P6_LINKUPN 150 R1189 DS351 GRN PORT 6 12 P5_LINKUPN 150 R1190 DS352 GRN PORT 5 12 P4_LINKUPN 150 R1191 DS353 GRN PORT 4 12 P3_LINKUPN 150 R1192 DS354 GRN PORT 3 12 P2_LINKUPN 150 R1193 DS355 GRN PORT 2 12 P1_LINKUPN 150 R1194 DS356 GRN PORT 1 12 P0_LINKUPN 150 R1195 DS357 GRN PORT 0 12 PORT 9 12 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN P23_ACTIVEN 549R R1196 DS358 BLUE PORT 23 P22_ACTIVEN 549R R1197 DS359 BLUE PORT 22 P21_ACTIVEN 549R R1198 DS360 BLUE PORT 21 P20_ACTIVEN 549R R1199 DS361 BLUE PORT 20 P19_ACTIVEN 549R R1200 DS362 BLUE PORT 10 P18_ACTIVEN 549R R1201 DS363 BLUE PORT 18 P17_ACTIVEN 549R R1202 DS364 BLUE PORT 17 P16_ACTIVEN 549R R1203 DS365 BLUE PORT 16 P15_ACTIVEN 549R R1204 DS366 BLUE PORT 15 P14_ACTIVEN 549R R1205 DS367 BLUE PORT 14 P13_ACTIVEN 549R R1206 DS368 BLUE PORT 13 P12_ACTIVEN 549R R1207 DS369 BLUE PORT 12 P11_ACTIVEN 549R R1208 DS370 BLUE PORT 11 P10_ACTIVEN 549R R1209 DS371 BLUE PORT 10 P9_ACTIVEN 549R R1210 DS372 BLUE PORT 9 P8_ACTIVEN 549R R1211 DS373 BLUE PORT 8 P7_ACTIVEN 549R R1212 DS374 BLUE PORT 7 P6_ACTIVEN 549R R1213 DS375 BLUE PORT 6 P5_ACTIVEN 549R R1214 DS376 BLUE PORT 5 P4_ACTIVEN 549R R1215 DS377 BLUE PORT 4 P3_ACTIVEN 549R R1216 DS378 BLUE PORT 3 P2_ACTIVEN 549R R1217 DS379 BLUE PORT 2 P1_ACTIVEN 549R R1218 DS380 BLUE PORT 1 P0_ACTIVEN 549R R1219 DS381 BLUE PORT 0 TITLE B A EB-LOGAN-19 LED - PORT STATUS (7 OF 7) SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:55 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 36 OF 41 1 8 7 6 5 4 HDR_2x30 D SLOT_RESETN CARD_PRESENTN WAKEN POWERGOOD PWR_FLTN PWR_ENABLE CLOCK_ENABLEN C PS_ENABLEN CABLE SENSE 1 2 2 3 3 4 4 100 R1220 100 R1221 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 100 17 17 18 18 19 19 20 20 100 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 100 31 31 32 32 33 33 34 34 100 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 100 45 45 46 46 47 47 48 48 100 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 100 59 59 60 60 J43 R1222 R1223 R1224 R1225 R1226 R1227 R1228 SLOT_RSTN8 P8_PDN SLOT_WAKEN8 P8_PWRGDN P8_PFN P8_PEP P8_CLK_EN SLOT_RSTN9 P9_PDN SLOT_WAKEN9 P9_PWRGDN P9_PFN P9_PEP P9_CLK_EN SLOT_RSTN10 P10_PDN SLOT_WAKEN10 P10_PWRGDN P10_PFN P10_PEP P10_CLK_EN SLOT_RSTN11 P11_PDN SLOT_WAKEN11 P11_PWRGDN P11_PFN P11_PEP P11_CLK_EN PS_ENABLEN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN 16 3 8 1 1 2 2 30 3 3 4 4 SLOT_RESETN CARD_PRESENTN WAKEN POWERGOOD PWR_FLTN PWR_ENABLE CLOCK_ENABLEN PS_ENABLEN CABLE SENSE 6 31 7 7 8 8 14 31 9 9 10 10 8 14 33 11 11 12 12 13 13 14 14 15 15 16 16 100 17 17 18 18 19 19 20 20 100 39 16 10 38 39 30 16 10 31 21 21 22 22 10 31 23 23 24 24 33 25 25 26 26 27 27 28 28 29 29 30 30 100 31 31 32 32 10 39 16 9 38 39 30 33 33 34 34 100 9 31 35 35 36 36 9 31 37 37 38 38 9 33 39 39 40 40 41 41 42 42 43 43 44 44 100 45 45 46 46 47 47 48 48 100 16 39 16 10 38 39 30 16 10 31 49 49 50 50 10 31 51 51 52 52 10 33 53 53 54 54 39 22 37 55 55 56 56 57 57 58 58 100 59 59 60 60 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 12 12 100 100 13 13 14 14 15 15 16 16 100 17 17 18 18 19 19 20 20 100 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 100 31 31 32 32 33 33 34 34 100 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 100 45 45 46 46 47 47 48 48 100 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 100 59 59 60 60 VERT J44 J45 VERT SLOT_RSTN12 P12_PDN SLOT_WAKEN12 P12_PWRGDN P12_PFN P12_PEP P12_CLK_EN SLOT_RSTN13 P13_PDN SLOT_WAKEN13 P13_PWRGDN P13_PFN P13_PEP P13_CLK_EN SLOT_RSTN14 P14_PDN SLOT_WAKEN14 P14_PWRGDN P14_PFN P14_PEP P14_CLK_EN SLOT_RSTN15 P15_PDN SLOT_WAKEN15 P15_PWRGDN P15_PFN P15_PEP P15_CLK_EN PS_ENABLEN R1242 R1243 R1244 R1245 R1246 R1247 R1248 BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN 16 3 8 3 39 1 1 2 2 30 3 3 4 4 6 6 16 5 5 R1229 R1230 R1231 R1232 R1233 R1234 R1235 R1236 R1237 BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN 16 4 8 4 31 7 7 8 14 31 9 9 10 10 8 14 33 11 11 12 12 13 13 14 14 15 15 16 16 100 17 17 18 18 19 19 20 20 100 39 16 10 38 39 30 16 1 2 2 30 3 3 4 4 5 5 6 6 8 15 31 7 7 8 8 15 31 9 9 10 10 33 11 12 12 15 39 16 10 38 39 30 16 11 10 31 21 21 22 22 10 31 23 23 24 24 33 25 25 26 26 27 27 28 28 29 29 30 30 100 31 31 32 32 10 39 16 9 38 39 30 33 33 34 34 100 9 31 35 35 36 36 9 31 37 37 38 38 9 33 39 39 40 40 41 41 42 42 43 43 44 44 100 45 45 46 46 47 47 48 48 100 16 39 16 10 38 39 30 16 10 31 49 49 50 50 10 31 51 51 52 52 10 33 53 53 54 54 39 22 37 55 55 56 56 57 57 58 58 100 59 59 60 60 100 100 13 13 14 14 15 15 16 16 100 17 17 18 18 19 19 20 20 100 31 21 22 22 10 31 23 23 24 24 10 33 25 25 26 26 27 27 28 28 29 29 30 30 100 31 31 32 32 39 16 9 38 39 30 33 34 34 100 9 31 35 35 36 36 9 31 37 37 38 38 9 33 39 39 40 40 16 39 16 10 38 39 30 16 33 41 41 42 42 43 43 44 44 100 45 45 46 46 47 47 48 48 100 10 31 49 49 50 50 10 31 51 51 52 52 33 53 53 54 54 55 55 56 56 57 57 58 58 100 59 59 60 60 10 39 22 37 0.050X0.1 SHROUD VERT PORTS 20,21,22,23 J46 J47 VERT 21 10 8 R1262 R1263 R1264 R1265 R1266 R1267 R1268 SLOT_RSTN4 P4_PDN SLOT_WAKEN4 P4_PWRGDN P4_PFN P4_PEP P4_CLK_EN SLOT_RSTN5 P5_PDN SLOT_WAKEN5 P5_PWRGDN P5_PFN P5_PEP P5_CLK_EN SLOT_RSTN6 P6_PDN SLOT_WAKEN6 P6_PWRGDN P6_PFN P6_PEP P6_CLK_EN SLOT_RSTN7 P7_PDN SLOT_WAKEN7 P7_PWRGDN P7_PFN P7_PEP P7_CLK_EN PS_ENABLEN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN 16 8 38 39 30 16 8 31 8 31 8 33 D 39 16 9 38 39 38 39 38 39 30 16 9 31 9 31 9 33 39 16 8 30 16 8 31 8 31 8 33 39 16 9 30 16 9 31 9 31 9 33 C 39 22 37 0.050X0.1 SHROUD PORTS 4,5,6,7 HDR_2x30 1 8 8 R1261 14 0.050X0.1 SHROUD 39 16 R1260 8 PORTS 12,13,14,15 SLOT_RSTN20 P20_PDN SLOT_WAKEN20 P20_PWRGDN P20_PFN P20_PEP P20_CLK_EN SLOT_RSTN21 P21_PDN SLOT_WAKEN21 P21_PWRGDN P21_PFN P21_PEP P21_CLK_EN SLOT_RSTN22 P22_PDN SLOT_WAKEN22 P22_PWRGDN P22_PFN P22_PEP P22_CLK_EN SLOT_RSTN23 P23_PDN SLOT_WAKEN23 P23_PWRGDN P23_PFN P23_PEP P23_CLK_EN PS_ENABLEN 100 100 8 HDR_2x30 1 A R1241 14 HDR_2x30 B 100 8 0.050X0.1 SHROUD 1 11 R1240 8 16 5 100 6 3 5 1 HDR_2x30 39 PORTS 8,9,10,11 11 2 HDR_2x30 1 VERT 3 R1249 R1250 R1251 R1252 R1253 R1254 R1255 R1256 R1257 SLOT_RSTN16 P16_PDN SLOT_WAKEN16 P16_PWRGDN P16_PFN P16_PEP P16_CLK_EN SLOT_RSTN17 P17_PDN SLOT_WAKEN17 P17_PWRGDN P17_PFN P17_PEP P17_CLK_EN SLOT_RSTN18 P18_PDN SLOT_WAKEN18 P18_PWRGDN P18_PFN P18_PEP P18_CLK_EN SLOT_RSTN19 P19_PDN SLOT_WAKEN19 P19_PWRGDN P19_PFN P19_PEP P19_CLK_EN PS_ENABLEN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN 16 39 4 8 4 16 8 8 30 8 15 1 2 2 3 3 4 4 5 5 6 6 8 7 7 8 31 9 9 10 10 33 11 12 12 15 15 1 31 11 100 R1269 100 R1270 13 13 14 14 15 15 16 16 100 17 17 18 18 16 19 19 20 20 100 10 21 39 16 38 10 30 39 21 22 22 10 31 23 23 24 24 10 33 25 25 26 26 27 27 28 28 29 29 30 30 100 31 31 32 32 31 39 16 9 38 39 30 33 34 34 100 35 35 36 36 9 31 37 37 38 38 9 33 39 39 40 40 16 9 31 39 16 38 10 30 39 16 10 10 10 41 41 42 42 43 43 44 44 100 45 45 46 46 47 47 48 48 100 49 49 50 50 31 51 51 52 52 33 53 53 54 54 55 55 56 56 57 57 58 58 100 59 59 60 60 31 39 22 33 37 VERT 0.050X0.1 SHROUD PORTS 16,17,18,19 J48 R1271 R1272 R1273 R1274 R1275 R1276 R1277 SLOT_RSTN0 P0_PDN SLOT_WAKEN0 P0_PWRGDN P0_PFN P0_PEP P0_CLK_EN SLOT_RSTN1 P1_PDN SLOT_WAKEN1 P1_PWRGDN P1_PFN P1_PEP P1_CLK_EN SLOT_RSTN2 P2_PDN SLOT_WAKEN2 P2_PWRGDN P2_PFN P2_PEP P2_CLK_EN SLOT_RSTN3 P3_PDN SLOT_WAKEN3 P3_PWRGDN P3_PFN P3_PEP P3_CLK_EN PS_ENABLEN 16 BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN BI OUT BI OUT OUT IN IN IN 8 38 39 38 39 30 16 8 31 8 31 8 33 39 16 9 B 30 16 9 31 9 31 9 33 39 16 8 38 39 38 39 30 16 8 31 8 31 8 33 39 16 9 30 16 9 31 9 31 9 33 39 22 37 0.050X0.1 SHROUD A PORTS 0,1,2,3 TITLE EB-LOGAN-19 SIDEBAND CONNECTORS SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:55 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 37 OF 41 1 6 5 4 3 HDR_2x10 HDR_2x10 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 J80 VERT_SM SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN1 SLOT_RSTN3 IN IN IN IN IN IN IN IN IN IN 2.0MM NO-SHROUD PART4_PERSTN 1 1 2 2 39 3 3 4 4 16 37 38 39 16 37 38 35 13 OUT 16 37 38 39 5 5 6 6 16 37 38 39 7 7 8 8 9 10 10 3 6 35 38 39 9 3 6 35 38 39 11 11 12 12 4 6 35 38 39 13 13 14 14 39 15 15 16 16 16 37 39 17 17 18 18 16 37 39 19 19 20 20 4 6 35 38 TP110 YEL YEL TP136 PART1_PERSTN C 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 18 18 20 20 19 17 19 J81 VERT_SM SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN5 SLOT_RSTN7 IN IN IN IN IN IN IN IN IN IN 2.0MM NO-SHROUD 1 2 2 39 3 3 4 4 37 38 39 16 37 38 16 16 PART5_PERSTN 1 16 35 13 OUT 37 38 39 5 5 6 6 37 38 39 7 7 8 8 9 9 10 10 11 11 12 12 39 13 13 14 14 39 15 15 16 16 18 18 20 20 3 6 35 38 39 3 6 35 38 39 4 6 35 38 4 6 35 38 16 37 39 17 16 37 39 19 TP137 YEL TP138 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 J82 VERT_SM 20 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN9 SLOT_RSTN10 IN IN IN IN IN IN IN IN IN IN 2.0MM NO-SHROUD PART3_PERSTN PART6_PERSTN 1 2 2 39 3 3 4 4 37 38 39 16 37 38 35 13 OUT 16 37 38 39 5 5 6 6 16 37 38 39 7 7 8 8 3 6 35 38 39 9 9 10 10 3 6 35 38 39 11 11 12 12 4 6 35 38 39 13 13 14 14 4 6 35 38 39 15 15 16 16 18 16 37 39 17 17 18 16 37 39 19 19 20 TP139 TP140 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 38 39 3 6 35 38 39 4 6 35 38 39 4 6 38 39 35 16 37 39 16 37 39 16 37 38 39 16 37 38 39 16 16 37 38 39 37 38 39 3 6 35 38 39 3 6 35 38 39 4 6 35 38 39 4 6 35 38 39 16 37 39 16 37 39 C YEL J86 20 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN19 SLOT_RSTN21 IN IN IN IN IN IN IN IN IN IN 2.0MM NO-SHROUD 16 37 38 39 16 37 38 39 16 37 38 39 16 37 38 39 3 6 35 38 39 3 6 35 38 39 4 6 35 38 39 4 6 35 38 39 16 37 39 16 37 39 B YEL TP147 YEL TP148 HDR_2x10 1 J83 2.0MM NO-SHROUD 1 16 YEL VERT_SM 39 39 35 TP146 YEL TP112 OUT 38 38 6 YEL VERT_SM YEL 13 37 37 3 TP145 HDR_2x10 35 J85 IN IN IN IN IN IN IN IN IN IN TP116 B 16 16 D HDR_2x10 1 9 19 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN17 SLOT_RSTN18 YEL PART2_PERSTN 17 VERT_SM TP111 OUT 39 39 TP144 YEL YEL 13 38 38 YEL HDR_2x10 35 37 37 HDR_2x10 1 17 16 16 YEL TP115 OUT 2.0MM NO-SHROUD YEL 13 IN IN IN IN IN IN IN IN IN IN TP143 HDR_2x10 35 J84 VERT_SM YEL TP135 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN14 SLOT_RSTN15 TP114 OUT PART0_PERSTN YEL 13 1 YEL YEL D 35 2 TP113 7 TP109 8 20 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN11 SLOT_RSTN13 2.0MM NO-SHROUD IN IN IN IN IN IN IN IN IN IN 1 2 2 39 3 3 4 4 38 39 5 5 6 6 38 39 8 37 38 39 16 37 38 16 37 37 16 3 6 35 PART7_PERSTN 1 16 38 35 13 OUT 7 7 8 39 9 9 10 10 3 6 35 38 39 11 11 12 12 4 6 35 38 39 13 13 14 14 4 6 35 38 39 15 15 16 16 18 18 16 37 39 17 17 16 37 39 19 19 VERT_SM YEL A 20 J87 20 SLOT_RSTN0 SLOT_RSTN2 SLOT_RSTN4 SLOT_RSTN6 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 SLOT_RSTN22 SLOT_RSTN23 IN IN IN IN IN IN IN IN IN IN 2.0MM NO-SHROUD 16 37 38 39 16 37 38 39 16 37 38 39 37 38 39 16 3 6 35 38 39 3 6 35 38 39 4 6 35 38 39 4 6 35 38 39 16 37 39 16 37 39 YEL TP141 A TP149 YEL YEL TP142 TP150 TITLE EB-LOGAN-19 PARTITION RESET SELECT HEADERS SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:56 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 38 OF 41 1 8 7 5 4 3 2 1 DNP JUMPERS WHEN IOEXPANDER IS ENABLED YEL D TP121 YEL TP133 NOTE: 6 HDR_2x12 6 MAIN_RSTN IN 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 J133 VERT SLOT_RSTN0 SLOT_RSTN1 SLOT_RSTN2 SLOT_RSTN3 SLOT_RSTN4 SLOT_RSTN5 SLOT_RSTN6 SLOT_RSTN7 SLOT_RSTN8 SLOT_RSTN9 SLOT_RSTN10 SLOT_RSTN11 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 37 38 37 38 16 37 38 16 37 38 1 1 2 2 16 37 38 3 3 4 4 16 37 38 5 5 6 6 16 37 38 7 7 8 8 16 37 38 9 9 10 10 12 12 HDR_2x6 39 38 35 6 3 BI SLOT_HDR_RSTN8 16 37 39 11 16 37 38 VERT-TH 16 37 38 16 37 38 16 37 39 16 37 38 16 37 38 16 37 38 1 1 2 2 3 3 4 4 5 5 6 6 8 7 7 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 24 23 VERT 11 J129 MAIN_RSTN SLOT_RSTN8 P16_SATARSTN SLOT_HDR_RSTN12 SLOT_HDR_RSTN20 S8_SATA_RSTN OUT OUT OUT OUT OUT OUT 6 28 16 39 37 39 20 3 6 35 38 39 4 6 35 38 39 21 2.54MM NO-SHROUD 2.54MM NO HDR_2x12 C D 16 16 YEL 28 TP122 39 J134 24 SLOT_RSTN12 SLOT_RSTN13 SLOT_RSTN14 SLOT_RSTN15 SLOT_RSTN16 SLOT_RSTN17 SLOT_RSTN18 SLOT_RSTN19 SLOT_RSTN20 SLOT_RSTN21 SLOT_RSTN22 SLOT_RSTN23 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT HDR_2x6 39 38 35 6 3 BI SLOT_HDR_RSTN12 1 1 2 2 3 4 4 6 6 8 16 37 39 3 16 37 38 5 5 16 37 38 7 7 8 16 37 38 9 9 10 10 12 12 16 37 39 11 16 37 38 VERT-TH 16 37 38 16 37 38 11 J130 MAIN_RSTN SLOT_RSTN12 SLOT_HDR_RSTN8 SLOT_HDR_RSTN16 SLOT_HDR_RSTN20 S12_SATA_RSTN OUT OUT OUT OUT OUT OUT 6 28 16 3 C 39 37 6 39 35 38 39 4 6 35 38 39 4 6 35 38 39 21 2.54MM NO-SHROUD 2.54MM NO R487 R485 R483 R481 R479 R477 R475 R473 YEL TP123 +3V3 HDR_2x6 SM_SW8 1 2 3 4 5 6 S1A S1B S2A S2B S3A S3B S4A S4B S5A S5B S6B S6A 7 S7B S7A 8 S8B 6 4 BI SLOT_HDR_RSTN16 P0_CLK_EN P1_CLK_EN P2_CLK_EN P3_CLK_EN P4_CLK_EN P5_CLK_EN P6_CLK_EN P7_CLK_EN 16 15 14 13 12 11 10 9 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 12 12 11 OUT OUT OUT OUT OUT OUT OUT OUT MAIN_RSTN SLOT_RSTN16 P8_SATARSTN SLOT_HDR_RSTN12 SLOT_HDR_RSTN20 S16_SATA_RSTN 37 J131 VERT-TH 37 OUT OUT OUT OUT OUT OUT 6 28 16 39 37 39 19 3 6 35 38 39 4 6 35 38 39 B 21 2.54MM NO-SHROUD 37 37 37 37 37 37 YEL S8A 35 TP124 S13 B 38 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 39 +3V3 +3V3 HDR_2x6 38 35 6 4 BI SLOT_HDR_RSTN20 R495 R494 R493 R492 R491 R490 R489 R488 R486 R484 R482 R480 R478 R476 R474 R472 39 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 11 SM_SW8 1 2 3 4 5 6 7 8 S1A S1B S2A S2B S3A S4A S3B S4B S5A S5B S6A S6B S7A S8A S7B S8B 16 15 14 13 12 11 10 9 S15 SM_SW8 P8_CLK_EN P9_CLK_EN P10_CLK_EN P11_CLK_EN P12_CLK_EN P13_CLK_EN P14_CLK_EN P15_CLK_EN OUT OUT OUT OUT OUT OUT OUT OUT 37 1 37 2 37 3 37 4 37 5 37 6 37 7 37 8 S1A S1B S2A S2B S3A S4A S3B S4B S5A S5B S6A S6B S7A S8A S7B S8B 11 12 12 J132 16 15 14 13 12 11 10 9 P16_CLK_EN P17_CLK_EN P18_CLK_EN P19_CLK_EN P20_CLK_EN P21_CLK_EN P22_CLK_EN P23_CLK_EN OUT OUT OUT OUT OUT OUT OUT OUT 39 37 39 3 6 35 3 6 35 38 39 4 6 35 38 38 39 39 21 37 37 37 37 37 37 TITLE 37 EB-LOGAN-19 37 SLOT RESET SELECT HEADERS FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 5 2010 4 IDT 2.0 CHECKED BY Thu Jun 10 11:24:56 2010 3 REV. 18-692-001 Derek Huang Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) 6 28 A B 7 6 16 2.54MM NO-SHROUD SIZE 8 OUT OUT OUT OUT OUT OUT 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K S14 A 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K VERT-TH 10 MAIN_RSTN SLOT_RSTN20 SLOT_HDR_RSTN8 SLOT_HDR_RSTN12 SLOT_HDR_RSTN16 S20_SATA_RSTN 2 SHEET 39 OF 41 1 8 7 6 5 4 D 3 2 1 R1464 FB12 1 C695 C696 C697 C698 C699 C700 C701 C702 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 1.0UF R1461 1 400MA 0.1UF C694 16V 10UF C692 22PF D 5% 120OHM 0805 DNP DNP R1462 +3V3 R1471 10 0603 DNP 2 2 X4 C693 22PF ICS841484 1 XTAL_IN 2 XTAL_OUT VDD 4 VDD 14 VDD 24 VDD 29 VDDA 28 C 40 P8_ICS_FSEL0 IN 31 REF_IN 30 REF_SEL 22 FSEL0 23 FSEL1 20 26 25 P8_ICS_SSM IN 27 9 B 33.2 R1466 Q0 5 33.2 R1467 nQ0 6 Q1 7 33.2 R1468 nQ1 8 Q2 10 nQ2 11 MR_nOE IREF Q3 12 nQ3 13 SSM BYPASS YEL TP99 GND NC 15 19 GND NC 16 32 GND NC 17 33 PGND NC 18 LP8_CLKP 33.2 R1469 33.2 R1470 OUT OUT OUT OUT LP8_CLKN LS8_CLKP 33.2 33.2 R1472 R1473 R1474 33.2 R1475 19 678005005 21 1 1 2 2 LSATA8_CLKN 3 3 LSMA8_CLKP 4 4 LSMA8_CLKN 5 5 6 6 7 7 LS8_CLKN LSATA8_CLKP 33.2 19 21 NC NC NC NC MTG1 MTG1 MTG2 MTG2 J94 U118 475 R1460 40 3 P8_ICS_MR IN 1% 40 21 REF_OUT OE_REFOUT C B J95 R1465 R1482 R1480 R1478 5 R1476 R1463 CONNSMA 4 1 3 221789-0 49.9 49.9 +3V3 49.9 49.9 10K DNP 2 J96 R1483 R1481 R1479 5 4 1 R1430 49.9 49.9 3 221789-0 4.7K 4.7K 4.7K 49.9 2 49.9 R1427 R1424 R1477 CONNSMA A A SW1 SM_SW4 1 2 3 4 S1A S1B S2A S2B S3A S3B S4A S4B 8 P8_ICS_FSEL0 7 P8_ICS_MR 6 P8_ICS_SSM OUT OUT OUT 5 40 TITLE EB-LOGAN-19 40 40 PORT 8 CLOCK GENERATOR SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:56 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 40 OF 41 1 8 7 6 5 4 3 2 1 +3V3 R1512 FB14 C718 C719 C720 C721 C722 C723 C724 0.1UF 0.1UF 0.1UF 0.1UF 10UF 0.1UF 1.0UF 16V C716 C717 10UF 1 R1509 1 400MA 0.1UF DNP D 5% 120OHM 0805 C714 22PF R1519 10 0603 DNP R1510 D DNP 2 2 X6 C715 22PF ICS841484 1 2 C P16_ICS_FSEL0 IN 30 REF_SEL 22 FSEL0 23 FSEL1 P16_ICS_SSM IN R1508 VDDA 28 C 21 33.2 R1514 Q0 5 33.2 R1515 nQ0 6 33.2 R1516 REF_OUT Q1 7 nQ1 8 Q2 10 nQ2 11 25 SSM Q3 12 BYPASS 9 nQ3 YEL TP101 IREF MR_nOE 33.2 33.2 13 15 GND NC 19 GND NC 16 32 GND NC 17 33 PGND NC 18 LP16_CLKP 33.2 R1520 33.2 R1521 33.2 R1522 33.2 R1523 OUT OUT OUT OUT LP16_CLKN LS16_CLKP LS16_CLKN R1517 678005005 21 21 1 1 2 2 LSATA16_CLKN 3 3 LSMA16_CLKP 4 4 LSMA16_CLKN 5 5 6 6 7 7 LSATA16_CLKP R1518 20 20 NC NC NC NC MTG1 MTG1 MTG2 MTG2 J100 U120 475 B 29 26 27 1% 41 24 VDD OE_REFOUT 3 P16_ICS_MR IN 14 VDD REF_IN 20 41 4 VDD XTAL_OUT 31 41 VDD XTAL_IN B R1513 R1530 R1528 R1526 R1524 5 4 1 49.9 49.9 49.9 +3V3 49.9 2 10K DNP 3 221789-0 R1531 R1529 R1525 J102 R1527 R1511 J101 CONNSMA CONNSMA 5 4 49.9 49.9 49.9 49.9 R1431 R1428 2 3 221789-0 4.7K 4.7K 4.7K R1425 1 A A SW2 SM_SW4 1 2 3 4 S1A S1B S2A S2B S3A S3B S4A S4B 8 P16_ICS_FSEL0 7 P16_ICS_MR 6 P16_ICS_SSM OUT OUT OUT 5 41 41 41 TITLE EB-LOGAN-19 PORT 16 CLOCK GENERATOR SIZE B FAB P/N DRAWING NO. SCH-PESEB-002 AUTHOR CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. 8 7 6 5 2010 4 IDT Derek Huang Thu Jun 10 11:24:56 2010 3 2.0 CHECKED BY Tony Tran 6024 SILVER CREEK VALLEY ROAD. SAN JOSE, CA 95138 COPYRIGHT (C) REV. 18-692-001 2 SHEET 41 OF 41 1 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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