48-Lane 12-Port PCIe® Gen2
System Interconnect Switch
89HPES48H12G2
Data Sheet
®
Device Overview
The 89HPES48H12G2 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES48H12G2 is a 48-lane, 12port system interconnect switch optimized for PCI Express Gen2 packet
switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include servers,
storage, communications, embedded systems, and multi-host or intelligent I/O based systems with inter-domain communication.
Features
High Performance Non-Blocking Switch Architecture
– 48-lane 12-port PCIe switch
• Six x8 ports switch ports each of which can bifurcate to two
x4 ports (total of twelve x4 ports)
– Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Gen1 operation
– Delivers up to 48 GBps (384 Gbps) of switching capacity
– Supports 128 Bytes to 2 KB maximum payload size
– Low latency cut-through architecture
– Supports one virtual channel and eight traffic classes
Standards and Compatibility
– PCI Express Base Specification 2.0 compliant
– Implements the following optional PCI Express features
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Power Budgeting Enhanced Capability
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting ECN
• Multicast ECN
• VGA and ISA enable
• L0s and L1 ASPM
• ARI ECN
Port Configurability
– x4 and x8 ports
• Ability to merge adjacent x4 ports to create a x8 port
– Automatic per port link width negotiation
(x8 → x4 → x2 → x1)
– Crosslink support
– Automatic lane reversal
– Autonomous and software managed link width and speed
control
– Per lane SerDes configuration
• De-emphasis
• Receive equalization
• Drive strength
Switch Partitioning
– IDT proprietary feature that creates logically independent
switches in the device
– Supports up to 12 fully independent switch partitions
– Configurable downstream port device numbering
– Supports dynamic reconfiguration of switch partitions
• Dynamic port reconfiguration — downstream, upstream
• Dynamic migration of ports between partitions
• Movable upstream port within and between switch partitions
Initialization / Configuration
– Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
– Common switch configurations are supported with pin strapping (no external components)
– Supports in-system Serial EEPROM initialization/programming
Quality of Service (QoS)
– Port arbitration
• Round robin
– Request metering
• IDT proprietary feature that balances bandwidth among
switch ports for maximum system throughput
– High performance switch core architecture
• Combined Input Output Queued (CIOQ) switch architecture
with large buffers
Multicast
– Compliant to the PCI-SIG multicast ECN
– Supports arbitrary multicasting of Posted transactions
– Supports 64 multicast groups
– Multicast overlay mechanism support
– ECRC regeneration support
Clocking
– Supports 100 MHz and 125 MHz reference clock frequencies
– Flexible clocking modes
• Common clock
• Non-common clock
• Local port clock with SSC and port reference clock input
Hot-Plug and Hot Swap
– Hot-plug controller on all ports
• Hot-plug supported on all downstream switch ports
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2011 Integrated Device Technology, Inc.
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
– All ports support hot-plug using low-cost external I2C I/O
expanders
– Configurable presence detect supports card and cable applications
– GPE output pin for hot-plug event notification
• Enables SCI/SMI generation for legacy operating system
support
– Hot swap capable I/O
Power Management
Product Description
– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)
• Supports L0, L0s, L1, L2/L3 Ready and L3 link states
• Configurable L0s and L1 entry timers allow performance/
power-savings tuning
– Supports PCI Express Power Budgeting Capability
– SerDes power savings
• Supports low swing / half-swing SerDes operation
• SerDes optionally turned-off in D3hot
• SerDes associated with unused ports are turned-off
• SerDes associated with unused lanes are placed in a low
power state
9 General Purpose I/O
Reliability, Availability and Serviceability (RAS)
The PES48H12G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link
and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES48H12G2 can operate either as a store and
forward or cut-through switch. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity for servers, storage,
and embedded processors with limited connectivity.
Utilizing standard PCI Express Gen2 interconnect, the
PES48H12G2 provides the most efficient system interconnect switching
solution for applications requiring high throughput, low latency, and
simple board layout with a minimum number of board layers. It provides
48 GBps (384 Gbps) of aggregated, full-duplex switching capacity
through 48 integrated serial lanes, using proven and robust IDT technology. Each lane is capable of 5 GT/s of bandwidth in both directions
and is fully compliant with PCI Express Base specification 2.0.
The PES48H12G2 is a partitionable PCIe switch. This means that in
addition to operating as a standard PCI express switch, the
PES48H12G2 ports may be partitioned into groups that logically
operate as completely independent PCIe switches. Figure 2 illustrates a
three partition PES48H12G2 configuration.
–
–
–
–
–
–
ECRC support
AER on all ports
SECDED ECC protection on all internal RAMs
End-to-end data path parity protection
Checksum Serial EEPROM content protected
Autonomous link reliability (preserves system operation in the
presence of faulty links)
– Ability to generate an interrupt (INTx or MSI) on link up/down
transitions
Test and Debug
– On-chip link activity and status outputs available for Port 0
(upstream port)
– Per port link activity and status outputs available using
external I2C I/O expander for all other ports
– SerDes test modes
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
Power Supplies
– Requires only two power supply voltages (1.0 V and 2.5 V)
Note that a 3.3V is preferred for VDDI/O
– No power sequencing requirements
Packaged in a 27mm x 27mm 676-ball Flip Chip BGA with
1mm ball spacing
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November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Block Diagram
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
SerDes
SerDes
SerDes
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
Port
Arbitration
Route Table
12-Port Switch Core
Scheduler
Frame Buffer
DL/Transaction Layer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
SerDes
x8/x4/x2/x1
x8/x4/x2/x1
x8/x4/x2/x1
48 PCI Express Lanes
Up to 6 x8 ports or 12 x4 Ports
Figure 1 Internal Block Diagram
P2P
Bridge
Partition 1
Upstream Port
Partition 2
Upstream Port
Partition 3
Upstream Port
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 1 – Virtual PCI Bus
Partition 2 – Virtual PCI Bus
Partition 3 – Virtual PCI Bus
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
P2P
Bridge
Partition 2
Downstream Ports
Partition 1
Downstream Ports
P2P
Bridge
Partition 3
Downstream Ports
Figure 2 Example of Usage of Switch Partitioning
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IDT 89HPES48H12G2 Data Sheet
SMBus Interface
The PES48H12G2 contains an SMBus master interface. This master interface allows the default configuration register values of the PES48H12G2
to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug
I/O expander. Two pins make up the SMBus master interface: an SMBus clock pin and an SMBus data pin. Four pins make up the SMBus slave interface: an SMBus clock pin and an SMBus data pin plus two address pins, SSMBADDR[2,1].
As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.
Switch
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
Hot-Plug
I/O
Expander
Figure 3 Split SMBus Interface Configuration
The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the
SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two
independent buses; thus, multi-master arbitration is not required.
Hot-Plug Interface
The PES48H12G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
PES48H12G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES48H12G2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES48H12G2. In response to an I/O expander interrupt, the PES48H12G2 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES48H12G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables list the functions of the pins provided on the PES48H12G2. Some of the functions listed may be multiplexed onto the same
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
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IDT 89HPES48H12G2 Data Sheet
Signal
Type
Name/Description
PE00RP[3:0]
PE00RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
PE00TP[3:0]
PE00TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0.
PE01RP[3:0]
PE01RN[3:0]
I
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PE01TP[3:0]
PE01TN[3:0]
O
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PE02RP[3:0]
PE02RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE02TP[3:0]
PE02TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2.
PE03RP[3:0]
PE03RN[3:0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PE03TP[3:0]
PE03TN[3:0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PE04RP[3:0]
PE04RN[3:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE04TP[3:0]
PE04TN[3:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4.
PE05RP[3:0]
PE05RN[3:0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PE05TP[3:0]
PE05TN[3:0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PE06RP[3:0]
PE06RN[3:0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive
pairs for port 6.
PE06TP[3:0]
PE06TN[3:0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pairs for port 6.
PE07RP[3:0]
PE07RN[3:0]
I
PCI Express Port 7 Serial Data Receive. Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
port 6 receive pairs for lanes 4 through 7.
PE07TP[3:0]
PE07TN[3:0]
O
PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for port 7. When port 6 is merged with port 7, these signals
become port 6 transmit pairs for lanes 4 through 7.
PE08RP[3:0]
PE08RN[3:0]
I
PCI Express Port 8 Serial Data Receive. Differential PCI Express receive
pairs for port 8.
PE08TP[3:0]
PE08TN[3:0]
O
PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for port 8.
Table 1 PCI Express Interface Pins (Part 1 of 2)
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IDT 89HPES48H12G2 Data Sheet
Signal
Type
Name/Description
PE09RP[3:0]
PE09RN[3:0]
I
PCI Express Port 9 Serial Data Receive. Differential PCI Express receive
pairs for port 9. When port 8 is merged with port 9, these signals become
port 8 receive pairs for lanes 4 through 7.
PE09TP[3:0]
PE09TN[3:0]
O
PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for port 9. When port 8 is merged with port 9, these signals
become port 8 transmit pairs for lanes 4 through 7.
PE12RP[3:0]
PE12RN[3:0]
I
PCI Express Port 12 Serial Data Receive. Differential PCI Express
receive pairs for port 12.
PE12TP[3:0]
PE12TN[3:0]
O
PCI Express Port 12 Serial Data Transmit. Differential PCI Express
transmit pairs for port 12.
PE13RP[3:0]
PE13RN[3:0]
I
PCI Express Port 13 Serial Data Receive. Differential PCI Express
receive pairs for port 13. When port 12 is merged with port 13, these signals become port 12 receive pairs for lanes 4 through 7.
PE13TP[3:0]
PE13TN[3:0]
O
PCI Express Port 13 Serial Data Transmit. Differential PCI Express
transmit pairs for port 13. When port 12 is merged with port 13, these signals become port 12 transmit pairs for lanes 4 through 7.
Table 1 PCI Express Interface Pins (Part 2 of 2)
Signal
Type
Name/Description
GCLKN[1:0]
GCLKP[1:0]
I
Global Reference Clock. Differential reference clock input pair. This clock
is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic. The frequency of the differential reference
clock is determined by the GCLKFSEL signal.
P[2,0]CLKN
P[2,0]CLKP
I
Port Reference Clock. Differential reference clock pair associated with
ports 0 and 2.1
Table 2 Reference Clock Pins
1.
Unused port clock pins should be connected to Vss on the board.
Signal
Type
Name/Description
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[2,1]
I
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Table 3 SMBus Interface Pins
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IDT 89HPES48H12G2 Data Sheet
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PART0PERSTN
Alternate function pin type: Input/Output
Alternate function: Assertion of this signal initiated a partition fundamental
reset in the corresponding partition.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PART1PERSTN
Alternate function pin type: Input/Output
Alternate function: Assertion of this signal initiated a partition fundamental
reset in the corresponding partition.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PART2PERSTN
Alternate function pin type: Input/Output
Alternate function: Assertion of this signal initiated a partition fundamental
reset in the corresponding partition.
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PART3PERSTN
Alternate function pin type: Input/Output
Alternate function: Assertion of this signal initiated a partition fundamental
reset in the corresponding partition.
GPIO[4]
I
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function — Reserved
2nd Alternate function pin name: P0LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 0 Link Up Status output.
GPIO[5]
O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: GPEN
1st Alternate function pin type: Output
1st Alternate function: Hot-plug general purpose even output.
2nd Alternate function pin name: P0ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 0 Link Active Status Output.
GPIO[6]
I
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[8]
I
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN
Alternate function pin type: Input
Alternate function: IO expander interrupt.
Table 4 General Purpose I/O Pins
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IDT 89HPES48H12G2 Data Sheet
Signal
Type
CLKMODE[2:0]
Name/Description
Clock Mode. These signals determine the port clocking mode used by
ports of the device.
GCLKFSEL
I
Global Clock Frequency Select. These signals select the frequency of
the GCLKP and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
P01MERGEN
I
Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 0 is merged with port 1 to form a single
x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7
of port 0. When this pin is high, port 0 and port 1 are not merged, and each
operates as a single x4 port.
P23MERGEN
I
Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 2 is merged with port 3 to form a single
x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7
of port 2. When this pin is high, port 2 and port 3 are not merged, and each
operates as a single x4 port.
P45MERGEN
I
Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 4 is merged with port 5 to form a single
x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7
of port 4. When this pin is high, port 4 and port 5 are not merged, and each
operates as a single x4 port.
P67MERGEN
I
Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 6 is merged with port 7 to form a single
x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7
of port 6. When this pin is high, port 6 and port 7 are not merged, and each
operates as a single x4 port.
P89MERGEN
I
Port 8 and 9 Merge. P89MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 8 is merged with port 9 to form a single
x8 port. The Serdes lanes associated with port 9 become lanes 4 through 7
of port 8. When this pin is high, port 8 and port 9 are not merged, and each
operates as a single x4 port.
P1213MERGEN
I
Port 12 and 13 Merge. P1213MERGEN is an active low signal. It is pulled
low internally. When this pin is low, port 12 is merged with port 13 to form a
single x8 port. The Serdes lanes associated with port 13 become lanes 4
through 7 of port 12. When this pin is high, port 12 and port 13 are not
merged, and each operates as a single x4 port.
Table 5 System Pins (Part 1 of 2)
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IDT 89HPES48H12G2 Data Sheet
Signal
Type
Name/Description
PERSTN
I
Global Reset. Assertion of this signal resets all logic inside PES48H12G2.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES48H12G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the PES48H12G2
switch operating mode. Note: These pins should be static and not change
following the negation of PERSTN.
0x0 - Single partition
0x1 - Single partition with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 disabled)
0x9 - Single partition with port 2 selected as the upstream port (port 0 disabled)
0xA - Single partition with Serial EEPROM initialization and port 0 selected
as the upstream port (port 2 disabled)
0xB - Single partition with Serial EEPROM initialization and port 2 selected
as the upstream port (port 0 disabled)
0xC - Multi-partition
0xD - Multi-partition with Serial EEPROM initialization
0xE - Reserved
0xF - Reserved
Table 5 System Pins (Part 2 of 2)
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IDT 89HPES48H12G2 Data Sheet
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
REFRES[13,12,9:0]
I/O
External Reference Resistors. Provides a reference for the SerDes bias
currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be
connected from these pins to ground.
REFRESPLL
I/O
PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground.
VDDCORE
I
Core VDD. Power supply for core logic (1.0V).
VDDI/O
I
I/O VDD. LVTTL I/O buffer power supply (2.5V or preferred 3.3V).
VDDPEA
I
PCI Express Analog Power. Serdes analog power supply (1.0V).
VDDPEHA
I
PCI Express Analog High Power. Serdes analog power supply (2.5V).
VDDPETA
I
PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
VSS
I
Ground.
Table 7 Power, Ground, and SerDes Resistor Pins
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IDT 89HPES48H12G2 Data Sheet
Pin Characteristics
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to
appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any
of these pins left floating can cause a slight increase in power consumption. Finally, unused Serdes (Rx and Tx) pins should be left floating.
Function
PCI Express Interface
Pin Name
Type
Buffer
PE00RN[3:0]
I
PE00RP[3:0]
I
PCIe
Differential2
PE00TN[3:0]
O
PE00TP[3:0]
O
PE01RN[3:0]
I
PE01RP[3:0]
I
PE01TN[3:0]
O
PE01TP[3:0]
O
PE02RN[3:0]
I
PE02RP[3:0]
I
PE02TN[3:0]
O
PE02TP[3:0]
O
PE03RN[3:0]
I
PE03RP[3:0]
I
PE03TN[3:0]
O
PE03TP[3:0]
O
PE04RN[3:0]
I
PE04RP[3:0]
I
PE04TN[3:0]
O
PE04TP[3:0]
O
PE05RN[3:0]
I
PE05RP[3:0]
I
PE05TN[3:0]
O
PE05TP[3:0]
O
PE06RN[3:0]
I
PE06RP[3:0]
I
PE06TN[3:0]
O
PE06TP[3:0]
O
PE07RN[3:0]
I
PE07RP[3:0]
I
PE07TN[3:0]
O
PE07TP[3:0]
O
PE08RN[3:0]
I
PE08RP[3:0]
I
PE08TN[3:0]
O
I/O
Type
Internal
Resistor1
Notes
Serial Link
Table 8 Pin Characteristics (Part 1 of 3)
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IDT 89HPES48H12G2 Data Sheet
Function
PCI Express Interface
(Cont.)
SMBus
Pin Name
I/O
Type
Internal
Resistor1
Notes
Type
Buffer
PE08TP[3:0]
O
Serial Link
PE09RN[3:0]
I
PCIe
Differential
PE09RP[3:0]
I
HCSL
Diff. Clock
Input
LVTTL
STI3
pull-up on board
pull-up on board
PE09TN[3:0]
O
PE09TP[3:0]
O
PE12RN[3:0]
I
PE12RP[3:0]
I
PE12TN[3:0]
O
PE12TP[3:0]
O
PE13RN[3:0]
I
PE13RP[3:0]
I
PE13TN[3:0]
O
PE13TP[3:0]
O
GCLKN[1:0]
I
GCLKP[1:0]
I
P00CLKN,
P00CLKP
I
P02CLKN,
P02CLKP
I
MSMBCLK
I/O
MSMBDAT
I/O
STI
I
Input
I/O
STI
SSMBADDR[2:1]
SSMBCLK
Refer to Table 9
pull-up
pull-up on board
SSMBDAT
I/O
General Purpose I/O
GPIO[8:0]
I/O
LVTTL
STI,
High Drive
STI
pull-up
pull-up on board
System Pins
CLKMODE[1:0]
I
LVTTL
Input
pull-up
CLKMODE[2]
I
pull-down
GCLKFSEL
I
pull-down
P01MERGEN
I
pull-down
P23MERGEN
I
pull-down
P45MERGEN
I
pull-down
P67MERGEN
I
pull-down
P89MERGEN
I
pull-down
P1213MERGEN
I
pull-down
PERSTN
I
STI
RSTHALT
I
Input
SWMODE[3:0]
I
pull-down
pull-down
Table 8 Pin Characteristics (Part 2 of 3)
12 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Function
Type
Buffer
I/O
Type
Internal
Resistor1
JTAG_TCK
I
LVTTL
STI
pull-up
JTAG_TDI
I
STI
pull-up
JTAG_TDO
O
JTAG_TMS
I
STI
pull-up
JTAG_TRST_N
I
STI
pull-up
Pin Name
EJTAG / JTAG
SerDes Reference
Resistors
REFRES00
I/O
REFRES01
I/O
REFRES02
I/O
REFRES03
I/O
REFRES04
I/O
REFRES05
I/O
REFRES06
I/O
REFRES07
I/O
REFRES08
I/O
REFRES09
I/O
REFRES12
I/O
REFRES13
I/O
REFRESPLL
I/O
Notes
Analog
Table 8 Pin Characteristics (Part 3 of 3)
1. Internal resistor values
under typical operating conditions are 92K Ω for pull-up and 91K Ω for pull-down.
2.
All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
Schmitt Trigger Input (STI).
13 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Logic Diagram — PES48H12G2
Global
Reference Clocks
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 1
GCLKFSEL
P00CLKN
PE00RP[3:0]
PE00RN[3:0]
PE00TP[3:0]
PE00TN3:[0]
PE01RP[3:0]
PE01RN[3:0]
P02CLKN
PE02RP[3:0]
PE02RN[3:0]
PE09TP[3:0]
PE09TN[3:0]
PE03RP[3:0]
PE03RN[3:0]
......
PCI Express
Switch
SerDes Input
Port 9
PCI Express
Switch
SerDes Input
Port 12
PCI Express
Switch
SerDes Input
Port 13
Master
SMBus Interface
Slave
SMBus Interface
PE09RP[3:0]
PE09RN[3:0]
PE12RP[3:0]
PE12RN[3:0]
PE13RP[3:0]
PE13RN[3:0]
9
PCI Express
Switch
SerDes Output
Port 12
PE13TP[3:0]
PE13TN[3:0]
PCI Express
Switch
SerDes Output
Port 13
GPIO[8:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
MSMBCLK
MSMBDAT
2
REFRES[13,12,9:0]
CLKMODE[2:0]
RSTHALT
PERSTN
SWMODE[3:0]
System
Pins
REFRESPLL
3
PCI Express
Switch
SerDes Output
Port 9
PE12TP[3:0]
PE12TN[3:0]
PES48H12G2
SSMBADDR[2,1]
SSMBCLK
SSMBDAT
PCI Express
Switch
SerDes Output
Port 0
......
PCI Express
Switch
SerDes Input
Port 2
PCI Express
Switch
SerDes Input
Port 3
GCLKN[1:0]
GCLKP[1:0]
General Purpose
I/O
JTAG Pins
SerDes
Reference
Resistors
VDDCORE
4
VDDI/O
P01MERGEN
P23MERGEN
P45MERGEN
P67MERGEN
P89MERGEN
P1213MERGEN
VDDPEA
VDDPEHA
Power/Ground
VSS
VDDPETA
Figure 4 PES48H12G2 Logic Diagram
14 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Condition
Min
Typical
Max
Unit
100
1251
MHz
RefclkFREQ
Input reference clock frequency range
TC-RISE
Rising edge rate
Differential
0.6
4
V/ns
TC-FALL
Falling edge rate
Differential
0.6
4
V/ns
VIH
Differential input high voltage
Differential
+150
VIL
Differential input low voltage
Differential
VCROSS
Absolute single-ended crossing point
voltage
Single-ended
VCROSS-DELTA
Variation of VCROSS over all rising clock
edges
Single-ended
VRB
Ring back voltage margin
Differential
-100
TSTABLE
Time before VRB is allowed
Differential
500
TPERIOD-AVG
Average clock period accuracy
-300
2800
ppm
TPERIOD-ABS
Absolute period, including spread-spectrum and jitter
9.847
10.203
ns
TCC-JITTER
Cycle to cycle jitter
150
ps
VMAX
Absolute maximum input voltage
+1.15
V
VMIN
Absolute minimum input voltage
-0.3
Duty Cycle
Duty cycle
40
Rise/Fall Matching
Single ended rising Refclk edge rate versus falling Refclk edge rate
ZC-DC
Clock source output DC impedance
mV
+250
-150
mV
+550
mV
+140
mV
+100
mV
ps
V
60
20
%
%
40
60
Ω
Table 9 Input Clock Requirements
1.
The input clock frequency will be either 100 or 125 MHz depending on signal GCLKFSEL.
AC Timing Characteristics
Parameter
Gen 1
Description
1
Gen 2
Min
Typ1
Max1
Min1
Typ1
Max1
399.88
400
400.12
199.94
200
200.06
Units
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
TX Rise/Fall Time: 20% - 80%
TTX- IDLE-MIN
Minimum time in idle
0.75
0.75
0.125
ps
UI
UI
0.125
0.15
UI
20
20
UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
15 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Parameter
Gen 1
Description
1
Min
1
Typ
Gen 2
1
Max
TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending
an Idle ordered set
TTX-IDLE-TO-DIFF-
1
Min
Typ1
Max1
Units
8
8
ns
8
8
ns
1.3
1.3
ns
Maximum time to transition from valid idle to diff data
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
TMIN-PULSED
Minimum Instantaneous Lone Pulse Width
NA
TTX-HF-DJ-DD
Transmitter Deterministic Jitter > 1.5MHz Bandwidth
NA
0.15
UI
TRF-MISMATCH
Rise/Fall Time Differential Mismatch
NA
0.1
UI
200.06
ps
0.9
UI
PCIe Receive
UI
Unit Interval
399.88
400
400.12
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
TRX-EYE-MEDIUM TO
Max time between jitter median & max deviation
0.3
TRX-SKEW
Lane to lane input skew
20
TRX-HF-RMS
1.5 — 100 MHz RMS jitter (common clock)
TRX-HF-DJ-DD
0.4
199.94
0.4
UI
UI
MAX JITTER
8
ns
NA
3.4
ps
Maximum tolerable DJ by the receiver (common clock)
NA
88
ps
TRX-LF-RMS
10 KHz to 1.5 MHz RMS jitter (common clock)
NA
4.2
ps
TRX-MIN-PULSE
Minimum receiver instantaneous eye width
NA
0.6
UI
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
1. Minimum, Typical, and
Maximum values meet the requirements under PCI Specification 2.0
Signal
Symbol
Reference
Min Max Unit
Edge
Timing
Diagram
Reference
GPIO
GPIO[8:0]1
Tpw2
None
50
—
ns
Table 11 GPIO AC Timing Characteristics
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2. The values
for this symbol were determined by calculation, not by testing.
16 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
50.0
—
ns
See Figure 5.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
Tsu_16b
JTAG_TCK rising
Thld_16b
JTAG_TDO
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 12 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
17 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes
2.25
2.5
2.75
V
3.125
3.3
3.465
V
PCI Express Analog Power
0.95
1.0
1.1
V
VDDPEHA
PCI Express Analog High Power
2.25
2.5
2.75
V
VDDPETA1
PCI Express Transmitter Analog Voltage
0.95
1.0
1.1
V
VSS
Common ground
0
0
0
V
1
VDDPEA
2
Table 13 PES48H12G2 Operating Voltages
1.
VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value.
2.
VDDPEHA should have no more than 50mVpeak-peak AC power supply noise superimposed on the 2.5V nominal DC value.
Power-Up/Power-Down Sequence
During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Industrial
-40°C to +85°C Ambient
Table 14 PES48H12G2 Operating Temperatures
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November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
PCIe Analog
Supply
PCIe Analog
High Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
mA
3360
5529
2313
2705
816
825
845
898
24
29
Watts
3.36
6.08
2.31
2.98
2.04
2.27
0.85
0.99
0.06
0.08
mA
3360
5529
1989
2327
816
825
439
467
24
29
Watts
3.36
6.08
1.99
2.56
2.04
2.27
0.44
0.51
0.06
0.08
Number of Active
Lanes per Port
8/8/8/8/8/8
(Full Swing)
8/8/8/8/8/8
(Half Swing)
PCIe
Transmitter
Supply
Core Supply
I/O Supply
Total
Typ
Power
Max
Power
8.62
12.40
7.89
11.50
Table 15 PES48H12G2 Power Consumption — 2.5V I/O
PCIe Analog
Supply
PCIe Analog
High Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
mA
3360
5529
2313
2705
816
825
845
898
30
35
Watts
3.36
6.08
2.31
2.98
2.04
2.27
0.85
0.99
0.10
0.12
mA
3360
5529
1989
2327
816
825
439
467
30
35
Watts
3.36
6.08
1.99
2.56
2.04
2.27
0.44
0.51
0.10
0.12
Number of Active
Lanes per Port
8/8/8/8/8/8
(Full Swing)
8/8/8/8/8/8
(Half Swing)
PCIe
Transmitter
Supply
Core Supply
I/O Supply
Total
Typ
Power
Max
Power
8.66
12.44
7.93
11.54
Table 16 PES48H12G2 Power Consumption — 3.3V I/O
Note 1: I/O supply of 3.3V is preferred.
Note 2: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in VDDPEA, VDDPEHA, and
VDDPETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turnedoff port is close to zero. For example, if 2 ports out of 12 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 2/12 multiplied by the power consumption indicated in the above table.
Note 3: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: VDDPEA, VDDPEHA, and
VDDPETA.
19 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
Thermal Considerations
This section describes thermal considerations for the PES48H12G2 (27mm2 FCBGA676 package). The data in Table 17 below contains information that is relevant to the thermal performance of the PES48H12G2 switch.
Symbol
Parameter
Value
Units
Conditions
TJ(max)
Junction Temperature
125
oC
Maximum
70
o
C
Maximum for commercial-rated products
85
oC
Maximum for industrial-rated products
14.6
oC/W
Zero air flow
7.8
o
C/W
1 m/S air flow
6.4
oC/W
2 m/S air flow
TA(max)
θJA(effective)
Ambient Temperature
Effective Thermal Resistance, Junction-to-Ambient
θJB
Thermal Resistance, Junction-to-Board
2.7
oC/W
θJC
Thermal Resistance, Junction-to-Case
0.15
oC/W
P
Power Dissipation of the Device
12.44
Watts
Maximum
Table 17 Thermal Specifications for PES48H12G2, 27x27 mm FCBGA676 Package
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value
specified in Table 17. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be
maintained below the value determined by the formula:
θJA = (TJ(max) - TA(max))/P
Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to
achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value
provided in Table 17), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the
circuit board (number of layers and size of the board). It is strongly recommended that users perform their own thermal analysis for their own
board and system design scenarios.
20 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Description
Gen1
Min1
Typ1
Gen2
Max1
Min1
Typ1
Unit
Conditions
Max1
PCIe Transmit
VTX-DIFFp-p
Differential peak-to-peak output
voltage
800
1200
800
1200
mV
VTX-DIFFp-p-LOW
Low-Drive Differential Peak to
Peak Output Voltage
400
1200
400
1200
mV
VTX-DE-RATIO-
De-emphasized differential output
voltage
-3
-4
-3.0
-3.5
-4.0
dB
-5.5
-6.0
-6.5
dB
3.6
V
3.5dB
6.0dB
De-emphasized differential output
voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode
output voltage
VTX-DE-RATIO-
NA
0
3.6
0
20
mV
VTX-CM-DC-active- Abs delta of DC common mode
voltage between L0 and idle
idle-delta
100
100
mV
Abs delta of DC common mode
voltage between D+ and D-
25
25
mV
delta
VTX-Idle-DiffP
Electrical idle diff peak output
20
20
mV
RLTX-DIFF
Transmitter Differential Return
loss
10
10
dB
0.05 - 1.25GHz
8
dB
1.25 - 2.5GHz
RLTX-CM
Transmitter Common Mode
Return loss
6
6
dB
ZTX-DIFF-DC
DC Differential TX impedance
80
120
Ω
VTX-CM-ACpp
Peak-Peak AC Common
100
mV
VTX-DC-CM
Transmit Driver DC Common
Mode Voltage
3.6
V
600
mV
VTX-CM-DC-line-
100
NA
0
3.6
VTX-RCV-DETECT The amount of voltage change
allowed during Receiver Detection
ITX-SHORT
Transmitter Short Circuit Current
Limit
120
0
600
0
90
90
mA
Table 18 DC Electrical Characteristics (Part 1 of 2)
21 of 44
November 28, 2011
IDT 89HPES48H12G2 Data Sheet
I/O Type
Serial Link
(cont.)
Parameter
Description
Gen1
Min1
Typ1
Gen2
Max1
Min1
1200
120
Typ1
Unit
Conditions
Max1
PCIe Receive
VRX-DIFFp-p
Differential input voltage (peak-topeak)
175
RLRX-DIFF
Receiver Differential Return Loss
10
1200
mV
10
dB
8
RLRX-CM
Receiver Common Mode Return
Loss
6
ZRX-DIFF-DC
Differential input impedance (DC)
80
100
ZRX--DC
DC common mode impedance
40
50
ZRX-COMM-DC
Powered down input common
mode impedance (DC)
200k
350k
ZRX-HIGH-IMP-DCPOS
DC input CM input impedance for
V>0 during reset or power down
ZRX-HIGH-IMP-DCNEG
DC input CM input impedance for
V
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