89HPES12T3G2ZBBCGI

89HPES12T3G2 Data Sheet 12-Lane 3-Port Gen2 PCI Express® Switch ® Device Overview Legacy Support – PCI compatible INTx emulation – Bus locking ◆ Highly Integrated Solution – Incorporates on-chip internal memory for packet buffering and queueing – Integrates twelve 5 Gbps embedded SerDes with 8b/10b encoder/decoder (no separate transceivers needed) • Receive equalization (RxEQ) ◆ Reliability, Availability, and Serviceability (RAS) Features – Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-end CRC (ECRC) – Supports ECRC and Advanced Error Reporting – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC motherboards – Supports Hot-Swap ◆ The 89HPES12T3G2 is a member of IDT’s PRECISE™ family of PCI Express® switching solutions. The PES12T3G2 is a 12-lane, 3-port Gen2 peripheral chip that performs PCI Express Base switching with a feature set optimized for high performance applications such as servers, storage, and communications/networking. It provides connectivity and switching functions between a PCI Express upstream port and two downstream ports and supports switching between downstream ports. Features High Performance PCI Express Switch – Twelve 5 Gbps Gen2 PCI Express lanes – Three switch ports • One x4 upstream port • Two x4 downstream ports – Low latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 2.0 compliant ◆ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion – Ability to load device configuration from serial EEPROM ◆ Block Diagram 3-Port Switch Core / 12 PCI Express Lanes Frame Buffer Port Arbitration Route Table Scheduler Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Logical Layer Phy Logical Layer Phy Logical Layer SerDes SerDes SerDes (Port 0) (Port 2) (Port 4) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 30 August 10, 2011 DSC 6930 IDT 89HPES12T3G2 Data Sheet Power Management – Utilizes advanced low-power design techniques to achieve low typical power consumption – Support PCI Express Power Management Interface specification (PCI-PM 1.2) – Supports PCI Express Active State Power Management (ASPM) link state – Supports PCI Express Power Budgeting Capability – Supports the optional PCI Express SerDes Transmit LowSwing Voltage Mode – Unused SerDes are disabled and can be powered-off. ◆ Testability and Debug Features – Built in Pseudo-Random Bit Stream (PRBS) generator – Numerous SerDes test modes – Ability to read and write any internal register via the SMBus – Ability to bypass link training and force any link into any mode – Provides statistics and performance counters ◆ Nine General Purpose Input/Output Pins – Each pin may be individually configured as an input or output – Each pin may be individually configured as an interrupt input – Some pins have selectable alternate functions ◆ Packaged in a 19mm x 19mm 324-ball BGA with 1mm ball spacing ◆ Product Description Utilizing standard PCI Express interconnect, the PES12T3G2 provides the most efficient fan-out solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides 12 GBps (96 Gbps) of aggregated, full-duplex switching capacity through 12 integrated serial lanes, using proven and robust IDT technology. Each lane provides 5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base Specification, Revision 2.0. The PES12T3G2 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 2.0. The PES12T3G2 can operate either as a store and forward or cut-through switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded processors with limited connectivity. Processor Processor Memory Memory Memory Memory North Bridge x4 PES12T3G2 x4 x4 x4 PCI Express Slot I/O 10GbE I/O 10GbE I/O SATA Figure 2 I/O Expansion Application SMBus Interface The PES12T3G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES12T3G2, allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of the PES12T3G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in Table 1. Bit Slave SMBus Address Master SMBus Address 1 SSMBADDR[1] MSMBADDR[1] 2 SSMBADDR[2] MSMBADDR[2] 3 SSMBADDR[3] MSMBADDR[3] 4 0 MSMBADDR[4] 5 SSMBADDR[5] 1 6 1 0 7 1 1 Table 1 Master and Slave SMBus Address Assignment 2 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 3(a), the master and slave SMBuses are tied together and the PES12T3G2 acts both as a SMBus master as well as a SMBus slave on this bus. This requires that the SMBus master or processor that has access to PES12T3G2 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES12T3G2 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES12T3G2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. PES12T3G2 Processor SMBus Master Serial EEPROM ... Other SMBus Devices PES12T3G2 SSMBCLK SSMBDAT SSMBCLK SSMBDAT MSMBCLK MSMBDAT MSMBCLK MSMBDAT Processor SMBus Master ... Other SMBus Devices Serial EEPROM (b) Split Configuration and Management Buses (a) Unified Configuration and Management Bus Figure 3 SMBus Interface Configuration Examples Hot-Plug Interface The PES12T3G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES12T3G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES12T3G2 generates an SMBus transaction to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES12T3G2. In response to an I/O expander interrupt, the PES12T3G2 generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES12T3G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. 3 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Pin Description The following tables list the functions of the pins provided on the PES12T3G2. Some of the functions listed may be multiplexed onto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Note: In the PES12T3G2, the two downstream ports are labeled port 2 and port 4. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port. PE2RP[3:0] PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[3:0] PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2. PE4RP[3:0] PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[3:0] PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4. PEREFCLKP[0] PEREFCLKN[0] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz This pin should be static and not change following the negation of PERSTN. Table 2 PCI Express Interface Pins Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus. SSMBADDR[5,3:1] I SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. Table 3 SMBus Interface Pins 4 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2. GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4. GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O expander interrupt 0 input. GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Table 4 General Purpose I/O Pins 5 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Signal Type Name/Description CCLKDS I Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices.This bit is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports. The value may be overridden by modifying the SCLK bit in each downstream port’s PCIELSTS register. CCLKUS I Common Clock Upstream. The assertion of this pin indicates that the upstream port is using the same clock source as the upstream device. This bit is used as the initial value of the Slot Clock Configuration bit in the Link Status Register for the upstream port. The value may be overridden by modifying the SCLK bit in the P0_PCIELSTS register. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside PES12T3G2 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, PES12T3G2 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[2:0] I Switch Mode. These configuration pins determine the PES12T3G2 switch operating mode. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0x7 Reserved These pins should be static and not change following the negation of PERSTN. Table 5 System Pins Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. Table 6 Test Pins (Part 1 of 2) 6 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Signal Type Name/Description JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins (Part 2 of 2) Signal Type Name/Description REFRES0 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES2 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. REFRES4 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4 SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resistor should be connected from this pin to ground. VDDCORE I Core VDD. Power supply for core logic. VDDI/O I I/O VDD. LVTTL I/O buffer power supply. VDDPEA I PCI Express Analog Power. Serdes analog power supply (1.0V). VDDPEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V). VDDPETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog power supply (1.0V). VSS I Ground. Table 7 Power, Ground, and SerDes Resistor Pins 7 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Pin Characteristics Note: Some input pads of the PES12T3G2 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function PCI Express Interface SMBus Pin Name I/O Type Internal Resistor1 Type Buffer PE0RN[3:0] I Serial Link PE0RP[3:0] I PCIe differential2 PE0TN[3:0] O PE0TP[3:0] O PE2RN[3:0] I PE2RP[3:0] I PE2TN[3:0] O PE2TP[3:0] O PE4RN[3:0] I PE4RP[3:0] I PE4TN[3:0] O PE4TP[3:0] O PEREFCLKN[0] I HCSL PEREFCLKP[0] I Diff. Clock Input REFCLKM I LVTTL Input pull-down MSMBADDR[4:1] I LVTTL Input pull-up 3 Notes Refer to Table 9 MSMBCLK I/O STI pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[11,7:0] I/O LVTTL STI, High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I Input pull-up MSMBSMODE I Input pull-down PERSTN I STI RSTHALT I Input pull-down SWMODE[2:0] I Input pull-down JTAG_TCK I STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up EJTAG / JTAG LVTTL pull-up Table 8 Pin Characteristics (Part 1 of 2) 8 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Function SerDes Reference Resistors Pin Name Type Buffer REFRES0 I/O Analog REFRES2 I/O REFRES4 I/O I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2) 1. Internal resistor values under typical operating conditions are 92K Ω for pull-up and 90K Ω for pull-down. 2. All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media. 3. Schmitt Trigger Input (STI). 9 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Logic Diagram — PES12T3G2 Reference Clocks Reference Clock Frequency Selection PEREFCLKP[0] PEREFCLKN[0] REFCLKM PCI Express Switch SerDes Input Port 2 PE2RP[0] PE2RN[0] PCI Express Switch SerDes Input Port 4 PE4RP[0] PE4RN[0] System Pins PE2TP[0] PE2TN[0] ... PE2TP[3] PE2TN[3] PE2RP[3] PE2RN[3] PE4TP[0] PE4TN[0] ... ... Slave SMBus Interface PE0TP[3] PE0TN[3] PE0RP[3] PE0RN[3] ... Master SMBus Interface PE0TP[0] PE0TN[0] ... PE0RP[0] PE0RN[0] ... PCI Express Switch SerDes Input Port 0 PE4RP[3] PE4RN[3] MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT MSMBSMODE CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0] PE4TP[3] PE4TN[3] PES12T3G2 9 4 GPIO[11,7:0] JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N 4 REFRES0 REFRES2 REFRES4 PCI Express Switch SerDes Output Port 0 PCI Express Switch SerDes Output Port 2 PCI Express Switch SerDes Output Port 4 General Purpose I/O JTAG Pins SerDes Reference Resistors VDDCORE 3 VDDI/O VDDPEA VDDPEHA Power/Ground VDDPETA VSS Figure 4 PES12T3G2 Logic Diagram 10 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 15. Parameter Description Condition Min Typical Max Unit 100 1251 MHz RefclkFREQ Input reference clock frequency range TC-RISE Rising edge rate Differential 0.6 4 V/ns TC-FALL Falling edge rate Differential 0.6 4 V/ns VIH Differential input high voltage Differential +150 VIL Differential input low voltage Differential VCROSS Absolute single-ended crossing point voltage Single-ended VCROSS-DELTA Variation of VCROSS over all rising clock edges Single-ended VRB Ring back voltage margin Differential -100 TSTABLE Time before VRB is allowed Differential 500 TPERIOD-AVG Average clock period accuracy -300 2800 ppm TPERIOD-ABS Absolute period, including spread-spectrum and jitter 9.847 10.203 ns TCC-JITTER Cycle to cycle jitter 150 ps VMAX Absolute maximum input voltage +1.15 V VMIN Absolute minimum input voltage -0.3 Duty Cycle Duty cycle 40 Rise/Fall Matching Single ended rising Refclk edge rate versus falling Refclk edge rate ZC-DC Clock source output DC impedance mV +250 -150 mV +550 mV +140 mV +100 mV ps V 60 % 20 % 40 Ω 60 Table 9 Input Clock Requirements 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. AC Timing Characteristics Parameter Gen 1 Description Gen 2 Min1 Typ1 Max1 Min1 Typ1 Max1 399.88 400 400.12 199.94 200 200.06 Units PCIe Transmit UI Unit Interval TTX-EYE Minimum Tx Eye Width TTX-EYE-MEDIAN-toMAX-JITTER Maximum time between the jitter median and maximum deviation from the median TTX-RISE, TTX-FALL TX Rise/Fall Time: 20% - 80% TTX- IDLE-MIN Minimum time in idle 0.75 0.75 0.125 ps UI UI 0.125 0.15 UI 20 20 UI Table 10 PCIe AC Timing Characteristics (Part 1 of 2) 11 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Parameter Gen 1 Description 1 Min 1 Typ Gen 2 1 Max 1 Min Typ1 Max1 Units TTX-IDLE-SET-TO-IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 8 8 ns TTX-IDLE-TO-DIFF- 8 8 ns 1.3 1.3 ns Maximum time to transition from valid idle to diff data DATA TTX-SKEW Transmitter data skew between any 2 lanes TMIN-PULSED Minimum Instantaneous Lone Pulse Width NA TTX-HF-DJ-DD Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI TRF-MISMATCH Rise/Fall Time Differential Mismatch NA 0.1 UI 200.06 ps 0.9 UI PCIe Receive UI Unit Interval 399.88 400 400.12 TRX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) TRX-EYE-MEDIUM TO Max time between jitter median & max deviation 0.3 TRX-SKEW Lane to lane input skew 20 TRX-HF-RMS 1.5 — 100 MHz RMS jitter (common clock) TRX-HF-DJ-DD 0.4 199.94 0.4 UI UI MAX JITTER 8 ns NA 3.4 ps Maximum tolerable DJ by the receiver (common clock) NA 88 ps TRX-LF-RMS 10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps TRX-MIN-PULSE Minimum receiver instantaneous eye width NA 0.6 UI Table 10 PCIe AC Timing Characteristics (Part 2 of 2) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 2.0 Signal Symbol Reference Min Max Unit Edge Timing Diagram Reference GPIO GPIO[11,7:0]1 Tpw2 None 50 — ns Table 11 GPIO AC Timing Characteristics 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. 2. The values for this symbol were determined by calculation, not by testing. 12 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference Tper_16a none 50.0 — ns See Figure 5. 10.0 25.0 ns 2.4 — ns 1.0 — ns — 20 ns — 20 ns 25.0 — ns JTAG JTAG_TCK Thigh_16a, Tlow_16a JTAG_TMS1, JTAG_TDI Tsu_16b JTAG_TCK rising Thld_16b JTAG_TDO Tdo_16c Tdz_16c JTAG_TRST_N JTAG_TCK falling 2 Tpw_16d2 none Table 12 JTAG AC Timing Characteristics 1. The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. 2. The values for this symbol were determined by calculation, not by testing. Tlow_16a Tper_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c Tdz_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure 5 JTAG AC Timing Waveform 13 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Recommended Operating Supply Voltages Symbol Parameter Minimum Typical Maximum Unit 0.9 1.0 1.1 V VDDCORE Internal logic supply VDDI/O I/O supply except for SerDes LVPECL/CML 3.135 3.3 3.465 V VDDPEA1 PCI Express Analog Power 0.95 1.0 1.1 V 2 PCI Express Analog High Power 2.25 2.5 2.75 V 1 VDDPETA PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V VSS Common ground 0 0 0 V VDDPEHA Table 13 PES12T3G2 Operating Voltages VDDPEA and VDDPETA should have no more than 25mVpeak-peak AC power supply noise superimposed on the 1.0V nominal DC value. 1. 2. V PEHA should have no more than 50mV DD peak-peak AC power supply noise superimposed on the 2.5V nominal DC value. Absolute Maximum Voltage Rating Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Transmitter Supply I/O Supply 1.5V 1.5V 4.6V 1.5V 4.6V Table 14 PES12T3G2 Absolute Maximum Voltage Rating Warning: For proper and reliable operation in adherence with this data sheet, the device should not exceed the recommended operating voltages in Table 13. The absolute maximum operating voltages in Table 14 are offered to provide guidelines for voltage excursions outside the recommended voltage ranges. Device functionality is not guaranteed at these conditions and sustained operation at these values or any exposure to voltages outside the maximum range may adversely affect device functionality and reliability. Power-Up/Power-Down Sequence During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDI/O at all times. There are no other power-up sequence requirements for the various operating supply voltages. The power-down sequence can occur in any order. Recommended Operating Temperature Grade Temperature Commercial 0°C to +70°C Ambient Industrial -40°C to +85°C Ambient Table 15 PES12T3G2 Operating Temperatures 14 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet Power Consumption Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Core Supply PCIe Analog Supply PCIe Analog High Supply PCIe Termination Supply Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 2.5V Max 2.75V Typ 1.0V Max 1.1V Typ 3.3V Max 3.465V mA 531 781 402 484 155 220 230 264 3 4 Watts 0.53 0.86 0.40 0.53 0.39 0.61 0.23 0.29 0.01 0.02 mA 440 550 320 352 110 132 120 130 3 4 Watts 0.44 0.61 0.32 0.39 0.28 0.36 0.12 0.14 .01 .02 Number of active Lanes per Port 4/4/4 (Full swing) 4/1/1 (Full swing) I/O Supply Total Typ Power Max Power 1.56 2.3 1.16 1.51 Table 16 PES12T3G2 Power Consumption Thermal Considerations This section describes thermal considerations for the PES12T3G2 (19mm2 CABGA324 package). The data in Table 17 below contains information that is relevant to the thermal performance of the PES12T3G2 switch. Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the TJ(max) value Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oC Maximum 70 oC Maximum 23.6 oC/W Zero air flow 16.8 oC/W 1 m/S air flow 15.4 oC/W 2 m/S air flow TA(max) θJA(effective) Ambient Temperature Effective Thermal Resistance, Junction-to-Ambient θJB Thermal Resistance, Junction-to-Board 14.5 oC/W θJC Thermal Resistance, Junction-to-Case 7.6 oC/W P Power Dissipation of the Device 2.3 Watts Maximum Table 17 Thermal Specifications for PES12T3G2, 19x19 mm CABGA324 Package specified in Table 17. Consequently, the effective junction to ambient thermal resistance (θJA) for the worst case scenario must be maintained below the value determined by the formula: θJA = (TJ(max) - TA(max))/P Given that the values of TJ(max), TA(max), and P are known, the value of desired θJA becomes a known entity to the system designer. How to achieve the desired θJA is left up to the board or system designer, but in general, it can be achieved by adding the effects of θJC (value provided in Table 17), thermal resistance of the chosen adhesive (θCS), that of the heat sink (θSA), amount of airflow, and properties of the circuit board (number of layers and size of the board). As a general guideline, this device will not need a heat sink if the board has 8 or more layers AND the board size is larger than 4"x12" AND airflow in excess of 0.5 m/s is available. It is strongly recommended that users perform their own thermal analysis for their own board and system design scenarios. 15 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet DC Electrical Characteristics Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Serial Link Parameter Description Gen1 Min1 Typ1 Gen2 Max1 Min1 Typ1 Unit Conditions Max1 PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 800 1200 mV VTX-DIFFp-p-LOW Low-Drive Differential Peak to Peak Output Voltage 400 1200 400 1200 mV VTX-DE-RATIO- De-emphasized differential output voltage -3 -4 -3.0 -3.5 -4.0 dB -5.5 -6.0 -6.5 dB 3.6 V 3.5dB 6.0dB De-emphasized differential output voltage VTX-DC-CM DC Common mode voltage VTX-CM-ACP RMS AC peak common mode output voltage VTX-DE-RATIO- NA 0 3.6 0 20 mV VTX-CM-DC-active- Abs delta of DC common mode voltage between L0 and idle idle-delta 100 100 mV Abs delta of DC common mode voltage between D+ and D- 25 25 mV delta VTX-Idle-DiffP Electrical idle diff peak output 20 20 mV RLTX-DIFF Transmitter Differential Return loss 10 10 dB 0.05 - 1.25GHz 8 dB 1.25 - 2.5GHz RLTX-CM Transmitter Common Mode Return loss 6 6 dB ZTX-DIFF-DC DC Differential TX impedance 80 120 Ω VTX-CM-ACpp Peak-Peak AC Common 100 mV VTX-DC-CM Transmit Driver DC Common Mode Voltage 3.6 V 600 mV VTX-CM-DC-line- 100 NA 0 3.6 VTX-RCV-DETECT The amount of voltage change allowed during Receiver Detection ITX-SHORT Transmitter Short Circuit Current Limit 120 0 600 0 90 90 mA Table 18 DC Electrical Characteristics (Part 1 of 2) 16 of 30 August 10, 2011 IDT 89HPES12T3G2 Data Sheet I/O Type Serial Link (cont.) Parameter Description Gen1 Min1 Typ1 Gen2 Max1 Min1 1200 120 Typ1 Unit Conditions Max1 PCIe Receive VRX-DIFFp-p Differential input voltage (peak-topeak) 175 RLRX-DIFF Receiver Differential Return Loss 10 1200 mV 10 dB 8 RLRX-CM Receiver Common Mode Return Loss 6 ZRX-DIFF-DC Differential input impedance (DC) 80 100 ZRX--DC DC common mode impedance 40 50 ZRX-COMM-DC Powered down input common mode impedance (DC) 200k 350k 1.25 - 2.5GHz 6 dB 120 Refer to return loss spec Ω 60 40 60 Ω 50k Ω ZRX-HIGH-IMP-DC- DC input CM input impedance for V>0 during reset or power down POS 50k 50k Ω ZRX-HIGH-IMP-DC- DC input CM input impedance for V