89HPES22H16
Data Sheet
22-Lane 16-Port
PCI Express® Switch
®
Device Overview
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin algorithms
– Automatic per port link width negotiation from x4 to x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Supports locked transactions, allowing use with legacy software
– Ability to load device configuration from serial EEPROM
– Ability to control device via SMBus
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-two 2.5 Gbps embedded full duplex SerDes,
8B/10B encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Redundant upstream port failover capability
– Supports optional PCI Express end-to-end CRC checking
◆
The 89HPES22H16 is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES22H16 is a 22-lane, 16-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high-performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and up to
fifteen downstream ports and supports switching between downstream
ports.
◆
Features
◆
High Performance PCI Express Switch
– Sixteen maximum switch ports
• Two x4 ports
• Fourteen x1 ports
– Twenty-two 2.5 Gbps embedded SerDes
• Supports pre-emphasis and receive equalization on per-port
basis
– Delivers 88 Gbps (11 GBps) of aggregate switching capacity
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– Supports two virtual channels and eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆
Block Diagram
x4/x2/x1
x4/x2/x1
SerDes
SerDes
DL/Transaction Layer
DL/Transaction Layer
Port
Arbitration
Route Table
16-Port Switch Core
Scheduler
Frame Buffer
DL/Transaction Layer
DL/Transaction Layer
SerDes
SerDes
x1
x1
. . . . . . .
DL/Transaction Layer
SerDes
x1
22 PCI Express Lanes
2 x4 ports and 14 x1 Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 36
© 2009 Integrated Device Technology, Inc.
October 21, 2009
IDT 89HPES22H16 Data Sheet
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports optional PCI Express Advanced Error Reporting
– Supports PCI Express Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC
motherboards
– Supports Hot-Swap
◆
Power Management
– Supports PCI Power Management Interface specification,
Revision 1.1 (PCI-PM)
• Supports powerdown modes at the link level (L0, L0s, L1,
L2/L3 Ready and L3) and at the device level (D0, D3hot)
– Unused SerDes disabled
◆
Testability and Debug Features
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
◆ Thirty-two General Purpose Input/Output pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES22H16 provides
the most efficient I/O connectivity for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides 88 Gbps of aggregated, full-duplex
switching capacity through 22 integrated serial lanes, using proven and
robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specification 1.1.
The PES22H16 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers. The PES22H16 can operate either as a store and
forward switch or a cut-through switch and is designed to switch memory
and I/O transactions. It supports eight Traffic Classes (TCs) and two
Virtual Channels (VCs) with sophisticated resource management to
enable efficient switching and I/O connectivity.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES22H16 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES22H16 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES22H16 may be configured to operate in a split configuration as
shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES22H16 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
SMBus Interface
The PES22H16 contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES22H16,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configuration register values of the PES22H16 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
2 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
PES22H16
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES22H16
SSMBCLK
SSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
MSMBCLK
MSMBDAT
Processor
SMBus
Master
...
Other
SMBus
Devices
Serial
EEPROM
(b) Split Configuration and Management Buses
(a) Unified Configuration and Management Bus
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES22H16 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the
device, the PES22H16 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following
reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES22H16 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES22H16. In response to an I/O expander interrupt, the PES22H16 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES22H16 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES22H16. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for
port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for
port 0. Port 0 is the upstream port.
PE1RP[0]
PE1RN[0]
I
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pair for
port 1.
PE1TP[0]
PE1TN[0]
O
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pair for
port 1.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for
port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2.
Table 2 PCI Express Interface Pins (Part 1 of 3)
3 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
PE3RP[0]
PE3RN[0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pair for
port 3.
PE3TP[0]
PE3TN[0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for
port 3.
PE4RP[0]
PE4RN[0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pair for
port 4.
PE4TP[0]
PE4TN[0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pair for
port 4.
PE5RP[0]
PE5RN[0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pair for
port 5.
PE5TP[0]
PE5TN[0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pair for
port 5.
PE6RP[0]
PE6RN[0]
I
PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pair for
port 6.
PE6TP[0]
PE6TN[0]
O
PCI Express Port 6 Serial Data Transmit. Differential PCI Express transmit pair for
port 6.
PE7RP[0]
PE7RN[0]
I
PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pair for
port 7.
PE7TP[0]
PE7TN[0]
O
PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pair for
port 7.
PE8RP[0]
PE8RN[0]
I
PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pair for
port 8.
PE8TP[0]
PE8TN[0]
O
PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pair for
port 8.
PE9RP[0]
PE9RN[0]
I
PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pair for
port 9.
PE9TP[[0]
PE9TN[0]
O
PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pair for
port 9.
PE10RP[0]
PE10RN[0]
I
PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pair for
port 10.
PE10TP[0]
PE10TN[0]
O
PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pair for
port 10.
PE11RP[0]
PE11RN[0]
I
PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pair for
port 11.
PE11TP[0]
PE11TN[0]
O
PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pair for
port 11.
PE12RP[0]
PE12RN[0]
I
PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pair for
port 12.
PE12TP[0]
PE12TN[0]
O
PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pair for
port 12.
PE13RP[0]
PE13RN[0]
I
PCI Express Port 13 Serial Data Receive. Differential PCI Express receive pair for
port 13.
PE13TP[0]
PE13TN[0]
O
PCI Express Port 13 Serial Data Transmit. Differential PCI Express transmit pair for
port 13. W
Table 2 PCI Express Interface Pins (Part 2 of 3)
4 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
PE14RP[0]
PE14RN[0]
I
PCI Express Port 14 Serial Data Receive. Differential PCI Express receive pair for
port 14.
PE14TP[0]
PE14TN[0]
O
PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pair for
port 14.
PE15RP[0]
PE15RN[0]
I
PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pair for
port 15.
PE15TP[0]
PE15TN[0]
O
PCI Express Port 15 Serial Data Transmit. Differential PCI Express transmit pair for
port 15.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the frequency of the
reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
PEREFCLKP[3:0]
PEREFCLKN[3:0]
I
PCI Express Reference Clock. Differential reference clock pair input. This clock is
used as the reference clock by on-chip PLLs to generate the clocks required for the
system logic and on-chip SerDes. The frequency of the differential reference clock is
determined by the REFCLKM signal.
Table 2 PCI Express Interface Pins (Part 3 of 3)
Signal
Type
Name/Description
MSMBADDR[4:1]
I
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[5,3:1]
I
Slave SMBus Address. These pins determine the SMBus address to which the slave
SMBus interface responds.
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the
slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.
Master SMBus Address. These pins determine the SMBus address of the serial
EEPROM from which configuration information is loaded.
Table 3 SMBus Interface Pins
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins (Part 1 of 4)
5 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[8]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[10]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
GPIO[11]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P6RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 6
GPIO[12]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P7RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 7
GPIO[13]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P8RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 8
Table 4 General Purpose I/O Pins (Part 2 of 4)
6 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
GPIO[14]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P9RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 9
GPIO[15]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P10RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 10
GPIO[16]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P11RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 11
GPIO[17]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P12RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 12
GPIO[18]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P13RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 13
GPIO[19]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P14RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 14
GPIO[20]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P15RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 15
GPIO[21]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 0
GPIO[22]1
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN1
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 1
GPIO[23]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 2
Table 4 General Purpose I/O Pins (Part 3 of 4)
7 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
GPIO[24]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN3
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 3
GPIO[25]1
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN4
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 4
GPIO[26]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN5
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 5
GPIO[27]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN6
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 6
GPIO[28]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN7
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 7
GPIO[29]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[30]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[31]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN10
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 10
Table 4 General Purpose I/O Pins (Part 4 of 4)
1. GPIO pins 22 and 25 are not available in the 23x23mm package.
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
Table 5 System Pins (Part 1 of 2)
8 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
Name/Description
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the PES22H16 and
initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES22H16 executes the reset procedure and remains in a reset state with the Master
and Slave SMBuses active. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the PES22H16 switch operating
mode. These pins should be static and not change following the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as the
upstream port)
0x9 - Normal switch mode with upstream port failover (port 2 selected as the
upstream port)
0xA - Normal switch mode with Serial EEPROM initialization and upstream port
failover (port 0 selected as the upstream port)
0xB - Normal switch mode with Serial EEPROM initialization and upstream port
failover (port 2 selected as the upstream port)
0xC through 0xF - Reserved
Table 5 System Pins (Part 2 of 2)
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDI/O
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital power of
the SerDes.
Table 7 Power and Ground Pins
9 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal
Type
VDDAPE
I
VSS
I
VTTPE
Name/Description
PCI Express Analog Power. PCI Express analog power used by the PLL and bias
generator.
Ground.
PCI Express Serial Data Transmit Termination Voltage. This pin allows the driver
termination voltage to be set, enabling the system designer to control the Common
Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit
differential pair.
Table 7 Power and Ground Pins
10 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Pin Characteristics
Note: Some input pads of the PES22H16 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
Pin Name
Type
Buffer
I/O
Type
PCI Express Interface
PE0RN[3:0]
I
CML
Serial Link
PE0RP[3:0]
I
PE0TN[3:0]
O
PE0TP[3:0]
O
PE1RN[0]
I
PE1RP[0]
I
PE1TN[0]
O
PE1TP[0]
O
PE2RN[3:0]
I
PE2RP[3:0]
I
PE2TN[3:0]
O
PE2TP[3:0]
O
PE3RN[0]
I
PE3RP[0]
I
PE3TN[0]
O
PE3TP[0]
O
PE4RN[0]
I
PE4RP[0]
I
PE4TN[0]
O
PE4TP[0]
O
PE5RN[0]
I
PE5RP[0]
I
PE5TN[0]
O
PE5TP[0]
O
PE6RN[0]
I
PE6RP[0]
I
PE6TN[0]
O
PE6TP[0]
O
PE7RN[0]
I
PE7RP[0]
I
PE7TN[0]
O
PE7TP[0]
O
PE8RN[0]
I
Internal
Resistor
Notes
Table 8 Pin Characteristics (Part 1 of 3)
11 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Function
Pin Name
Type
Buffer
I/O
Type
PCI Express Interface
(cont.)
PE8RP[0]
I
CML
Serial Link
PE8TN[0]
O
PE8TP[0]
O
PE9RN[0]
I
PE9RP[0]
I
PE9TN[0]
O
PE9TP[0]
O
PE10RN[0]
I
LVPECL/
CML
Diff. Clock
Input
LVTTL
Input
PE10RP[0]
I
PE10TN[0]
O
PE10TP[0]
O
PE11RN[0]
I
PE11RP[0]
I
PE11TN[0]
O
PE11TP[0]
O
PE12RN[0]
I
PE12RP[0]
I
PE12TN[0]
O
PE12TP[0]
O
PE13RN[0]
I
PE13RP[0]
I
PE13TN[0]
O
PE13TP[0]
O
PE14RN[0]
I
PE14RP[0]
I
PE14TN[0]
O
PE14TP[0]
O
PE15RN[0]
I
PE15RP[0]
I
PE15TN[0]
O
PE15TP[0]
O
PEREFCLKN[3:0]
I
PEREFCLKP[3:0]
I
REFCLKM
I
Internal
Resistor
Notes
Refer to Table 9
pull-down
Table 8 Pin Characteristics (Part 2 of 3)
12 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Pin Name
Type
Buffer
SMBus
MSMBADDR[4:1]
I
LVTTL
MSMBCLK
I/O
STI1
MSMBDAT
I/O
STI
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
SSMBDAT
I/O
I/O
LVTTL
System Pins
CCLKDS
I
LVTTL
pull-up
STI
pull-up
Input
pull-up
CCLKUS
I
pull-up
MSMBSMODE
I
pull-down
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-down
JTAG_TCK
I
LVTTL
STI
pull-up
STI
pull-up
JTAG_TDI
I
JTAG_TDO
O
JTAG_TMS
I
STI
pull-up
JTAG_TRST_N
I
STI
pull-up
Schmitt Trigger Input (STI).
Notes
STI
GPIO[31:0]
EJTAG / JTAG
Internal
Resistor
pull-up
General Purpose I/O
1.
I/O
Type
Function
External pull-down
Table 8 Pin Characteristics (Part 3 of 3)
13 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Logic Diagram — PES22H16
PCI Express
Switch
SerDes Input
Port 1
...
PE0RP[3]
PE0RN[3]
PE0TP[3]
PE0TN[3]
PE1RP[0]
PE1RN[0]
PE1TP[0]
PE1TN[0]
PE2TP[0]
PE2TN[0]
PE2RP[0]
PE2RN[0]
PE2RP[3]
PE2RN[3]
PE2TP[3]
PE2TN[3]
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PCI Express
Switch
SerDes Input
Port 15
Master
SMBus Interface
PES22H16
PE15TP[0]
PE15TN[0]
PE15RP[0]
PE15RN[0]
MSMBADDR[4:1]
MSMBCLK
MSMBDAT
4
4
32
System
Pins
MSMBSMODE
CCLKDS
CCLKUS
RSTHALT
PERSTN
SWMODE[3:0]
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 1
PCI Express
Switch
SerDes Output
Port 2
PCI Express
Switch
SerDes Output
Port 3
...
...
PCI Express
Switch
SerDes Input
Port 3
PE0TP[0]
PE0TN[0]
PE0RP[0]
PE0RN[0]
...
PCI Express
Switch
SerDes Input
Port 2
4
...
PCI Express
Switch
SerDes Input
Port 0
4
PEREFCLKP[3:0]
PEREFCLKN[3:0]
REFCLKM
...
Reference
Clock
SSMBADDR[5,3:1]
SSMBCLK
SSMBDAT
GPIO[31:0]
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
4
VDDCORE
VDDIO
VDDPE
VDDAPE
VSS
PCI Express
Switch
SerDes Output
Port 15
Slave
SMBus Interface
General Purpose
I/O
JTAG Pins
Power/Ground
VTTPE
Figure 4 PES22H16 Logic Diagram
Note: GPIO pins 22 and 25 are not available in the 23x23mm package.
14 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Min
Typical
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
PEREFCLK
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
RT
Termination Resistor
50
0.6
110
Ohms
Table 9 Input Clock Requirements
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4. AC coupling required.
AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
399.88
400
400.12
ps
0.7
.9
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
D+ / D- Tx output rise/fall time
50
TTX- IDLE-MIN
Minimum time in idle
50
TTX-IDLE-SET-TO-
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20
UI
IDLE
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
20
UI
500
1300
ps
400
400.12
ps
UI
0.15
90
UI
ps
UI
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
PCIe Receive
UI
Unit Interval
399.88
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
TRX-EYE-MEDIUM TO
Max time between jitter median & max deviation
0.3
UI
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
Lane to lane input skew
20
ns
0.4
UI
MAX JITTER
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 10 PCIe AC Timing Characteristics
15 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tpw_13b2
None
50
—
ns
See Figure 5.
GPIO
GPIO[31:0]1
Table 11 GPIO AC Timing Characteristics
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
EXTCLK
Tpw_13b
GPIO (asynchronous input)
Figure 5 GPIO AC Timing Waveform
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Referenc
e
Tper_16a
none
50.0
—
ns
See Figure 6.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
JTAG_TDO
Tsu_16b
JTAG_TCK rising
Thld_16b
Tdo_16c
JTAG_TCK falling
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
none
Table 12 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
16 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 6 JTAG AC Timing Waveform
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.0
3.3
3.6
V
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 13 PES22H16 Operating Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES22H16, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
17 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Industrial
-40°C to +85°C Ambient
Table 14 PES22H16 Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Core Supply
PCIe Digital
Supply
PCIe Analog
Supply
PCIe Termination Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.5V
Max
1.575V
Typ
3.3V
Max
3.6V
Typ
Power
Max
Power
mA
1900
2364
1400
1727
800
1000
535
762
5
5
—
—
Watts
1.9
2.6
1.4
1.9
0.8
1.1
0.8
1.2
0.018
0.02
4.92
6.82
Number of active
Lanes per Port
Two x4 and
fourteen x1
I/O Supply
Total
Table 15 PES22H16 Power Consumption
Thermal Considerations
This section describes thermal considerations for the PES22H16 (23mm2 FCBGA484 package). The data in Table 16 below contains information
that is relevant to the thermal performance of the PES22H16 switch.
Symbol
Parameter
Value
Units
Conditions
TJ(max)
Junction Temperature
125
oC
Maximum
TA(max)
Ambient Temperature
70
oC
Maximum for commercial-rated products
θJA(effective)
Effective Thermal Resistance, Junction-to-Ambient
13.4
o
C/W
Zero air flow
7.2
oC/W
1 m/S air flow
6.2
oC/W
2 m/S air flow
θJB
Thermal Resistance, Junction-to-Board
2.5
o
θJC
Thermal Resistance, Junction-to-Case
0.1
oC/W
P
Power Dissipation of the Device
6.82
Watts
C/W
Maximum
Table 16 Thermal Specifications for PES22H16, 23x23mm FCBGA484 Package
Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance
can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective
θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card.
18 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Min1
Description
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
Conditions
PCIe Transmit
VTX-DIFFp-p
VTX-DE-RATIO
Differential peak-to-peak output voltage
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
Abs delta of DC common mode voltage
between D+ and D-
25
mV
Electrical idle diff peak output
20
mV
Voltage change during receiver detection
600
mV
active-idle-delta
VTX-CM-DC-linedelta
VTX-Idle-DiffP
VTX-RCV-Detect
-0.1
1
RLTX-DIFF
Transmitter Differential Return loss
12
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
15
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
Differential input impedance (DC)
80
100
120
Ω
Single-ended input impedance
40
50
60
Ω
200k
350k
PCIe Receive
ZRX-DIFF-DC
ZRX-COMM-DC
ZRX-COMM-HIGH- Powered down input common mode
impedance (DC)
Z-DC
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 17 DC Electrical Characteristics (Part 1 of 2)
19 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDI/O
+ 0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDI/O
+ 0.5
V
—
CIN
—
—
8.5
pF
—
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Capacitance
Leakage
Table 17 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.0a.
20 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Package Pinout — 484-BGA Signal Pinout for PES22H16
The following table lists the pin numbers and signal names for the PES22H16 device.
Pin
Function
A1
VDDI/O
A2
GPIO_16
A3
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
B13
VSS
D3
GPIO_27
1
E15
VSS
B14
PE2TP03
D4
GPIO_23
1
E16
VDDPE
VSS
B15
PE2TP02
D5
GPIO_20
1
E17
VDDPE
A4
PE9TN00
B16
VSS
D6
VSS
E18
JTAG_TRST_N
A5
PE8TN00
B17
PE2TN01
D7
PE9RP00
E19
SSMBCLK
A6
VSS
B18
PE2TN00
D8
PE9RN00
E20
SSMBADDR_2
A7
PE3RP00
B19
MSMBADDR_3
D9
PE8RP00
E21
PE1TP00
A8
PE2RP03
B20
JTAG_TDO
D10
PE8RN00
E22
PE1TN00
A9
VSS
B21
PERSTN
D11
VSS
F1
PE10RP00
A10
PEREFCLKN1
B22
JTAG_TDI
D12
PE2RP02
F2
PE10RN00
A11
VSS
C1
VDDI/O
D13
PE2RN02
F3
VSS
A12
PE3TN00
C2
GPIO_21
1
D14
PE2RP01
F4
GPIO_30
A13
VSS
C3
GPIO_19
1
D15
PE2RN01
F5
VDDI/O
A14
PE2TN03
C4
VSS
D16
PE2RP00
F6
VDDI/O
A15
PE2TN02
C5
VSS
D17
PE2RN00
F7
VDDPE
A16
VSS
C6
VSS
D18
MSMBADDR_1
F8
VDDPE
A17
PE2TP01
C7
VSS
D19
VDDI/O
F9
VDDPE
A18
PE2TP00
C8
VSS
D20
CCLKDS
F10
VDDCORE
A19
MSMBSMODE
C9
VSS
D21
SSMBADDR_1
F11
VDDCORE
A20
MSMBDAT
C10
VSS
D22
SSMBADDR_3
F12
VDDCORE
A21
JTAG_TMS
C11
VSS
E1
VSS
F13
VDDCORE
A22
VSS
C12
VSS
E2
VSS
F14
VDDPE
B1
VSS
C13
VSS
E3
GPIO_31
1
F15
VDDPE
B2
GPIO_18
C14
VSS
E4
GPIO_28
1
F16
VDDI/O
B3
VSS
C15
VSS
E5
GPIO_26
1
F17
VDDI/O
B4
PE9TP00
C16
VSS
E6
GPIO_17
1
F18
SSMBADDR_5
B5
PE8TP00
C17
VSS
E7
VDDPE
F19
VSS
B6
VSS
C18
MSMBADDR_4
E8
VSS
F20
VSS
B7
PE3RN00
C19
MSMBADDR_2
E9
VTTPE
F21
PE0TN03
B8
PE2RN03
C20
MSMBCLK
E10
VTTPE
F22
PE0TP03
B9
VSS
C21
SSMBDAT
E11
VDDPEA
G1
PE11RP00
B10
PEREFCLKP1
C22
JTAG_TCK
E12
VDDPEA
G2
PE11RN00
B11
VSS
D1
GPIO_29
E13
VTTPE
G3
VSS
B12
PE3TP00
D2
GPIO_24
E14
VTTPE
G4
VSS
1
1
1
Alt
Table 18 PES22H16 Signal Pin-Out (Part 1 of 4)
21 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
G5
VDDI/O
H20
VSS
K13
VSS
M6
VSS
G6
VDDPE
H21
PE0TN02
K14
VDDCORE
M7
VSS
G7
VSS
H22
PE0TP02
K15
VDDCORE
M8
VDDCORE
G8
VDDCORE
J1
PE10TN00
K16
VSS
M9
VDDCORE
G9
VDDCORE
J2
PE10TP00
K17
VDDPE
M10
VSS
G10
VSS
J3
VSS
K18
VTTPE
M11
VDDCORE
G11
VDDCORE
J4
VSS
K19
PE0RP03
M12
VDDCORE
G12
VDDCORE
J5
VTTPE
K20
VSS
M13
VSS
G13
VSS
J6
VDDPE
K21
VSS
M14
VDDCORE
G14
VDDCORE
J7
VSS
K22
VSS
M15
VDDCORE
G15
VDDCORE
J8
VDDCORE
L1
VSS
M16
VSS
G16
VSS
J9
VDDCORE
L2
VSS
M17
VSS
G17
VDDI/O
J10
VSS
L3
VSS
M18
VDDPEA
G18
VSS
J11
VDDCORE
L4
VSS
M19
PE0RN02
G19
PE1RN00
J12
VDDCORE
L5
VDDPEA
M20
VSS
G20
VSS
J13
VSS
L6
VSS
M21
VSS
G21
VSS
J14
VDDCORE
L7
VSS
M22
VSS
G22
VSS
J15
VDDCORE
L8
VDDCORE
N1
VSS
H1
VSS
J16
VSS
L9
VDDCORE
N2
VSS
H2
VSS
J17
VDDPE
L10
VSS
N3
VSS
H3
VSS
J18
VTTPE
L11
VDDCORE
N4
VSS
H4
VSS
J19
PE0RN03
L12
VDDCORE
N5
VTTPE
H5
VDDPE
J20
VSS
L13
VSS
N6
VSS
H6
VDDPE
J21
PE0TP01
L14
VDDCORE
N7
VSS
H7
VSS
J22
PE0TN01
L15
VDDCORE
N8
VDDCORE
H8
VDDCORE
K1
PE11TN00
L16
VSS
N9
VDDCORE
H9
VDDCORE
K2
PE11TP00
L17
VSS
N10
VSS
H10
VSS
K3
VSS
L18
VDDPEA
N11
VDDCORE
H11
VDDCORE
K4
VSS
L19
PE0RP02
N12
VDDCORE
H12
VDDCORE
K5
VTTPE
L20
VSS
N13
VSS
H13
VSS
K6
VSS
L21
PE0TP00
N14
VDDCORE
H14
VDDCORE
K7
VSS
L22
PE0TN00
N15
VDDCORE
H15
VDDCORE
K8
VDDCORE
M1
PEREFCLKN2
N16
VSS
H16
VSS
K9
VDDCORE
M2
PEREFCLKP2
N17
VSS
H17
VDDPE
K10
VSS
M3
VSS
N18
VTTPE
H18
VDDPE
K11
VDDCORE
M4
VSS
N19
VSS
H19
PE1RP00
K12
VDDCORE
M5
VDDPEA
N20
VSS
Alt
Table 18 PES22H16 Signal Pin-Out (Part 2 of 4)
22 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
N21
PEREFCLKN0
R14
VDDCORE
U7
VDDPE
V22
PE15TP00
N22
PEREFCLKP0
R15
VDDCORE
U8
VDDPE
W1
VSS
P1
PE4TN00
R16
VSS
U9
VDDPE
W2
VSS
P2
PE4TP00
R17
VDDPE
U10
VDDCORE
W3
VSS
P3
VSS
R18
VSS
U11
VDDCORE
W4
REFCLKM
P4
VSS
R19
PE15RN00
U12
VDDCORE
W5
RSTHALT
P5
VTTPE
R20
VSS
U13
VDDCORE
W6
SWMODE_1
P6
VDDPE
R21
PE0RN01
U14
VDDPE
W7
VSS
P7
VSS
R22
PE0RP01
U15
VDDPE
W8
VSS
P8
VDDCORE
T1
VSS
U16
VDDI/O
W9
VSS
P9
VDDCORE
T2
VSS
U17
VDDI/O
W10
VSS
P10
VSS
T3
VSS
U18
VSS
W11
VDDPEA
P11
VDDCORE
T4
VSS
U19
PE14RN00
W12
VSS
P12
VDDCORE
T5
VSS
U20
VSS
W13
VSS
P13
VSS
T6
VDDPE
U21
VSS
W14
VSS
P14
VDDCORE
T7
VSS
U22
VSS
W15
VDDI/O
P15
VDDCORE
T8
VDDCORE
V1
PE5RP00
W16
GPIO_01
P16
VSS
T9
VDDCORE
V2
PE5RN00
W17
GPIO_03
P17
VDDPE
T10
VSS
V3
VSS
W18
GPIO_04
P18
VTTPE
T11
VDDCORE
V4
VSS
W19
GPIO_08
P19
PE15RP00
T12
VDDCORE
V5
VDDI/O
W20
VSS
P20
VSS
T13
VSS
V6
VDDI/O
W21
PE14TN00
P21
VSS
T14
VDDCORE
V7
VSS
W22
PE14TP00
P22
VSS
T15
VDDCORE
V8
VDDPE
Y1
VDDI/O
R1
PE5TN00
T16
VSS
V9
VTTPE
Y2
CCLKUS
R2
PE5TP00
T17
VDDPE
V10
VTTPE
Y3
VDDI/O
R3
VSS
T18
VDDPE
V11
VDDPEA
Y4
SWMODE_0
R4
VSS
T19
PE14RP00
V12
VTTPE
Y5
VSS
R5
VDDPE
T20
VSS
V13
VTTPE
Y6
VSS
R6
VDDPE
T21
PE0RN00
V14
VDDPE
Y7
VSS
R7
VSS
T22
PE0RP00
V15
VDDPE
Y8
VSS
R8
VDDCORE
U1
PE4RP00
V16
VDDI/O
Y9
VSS
R9
VDDCORE
U2
PE4RN00
V17
GPIO_06
1
Y10
VSS
R10
VSS
U3
VSS
V18
GPIO_11
1
Y11
VSS
R11
VDDCORE
U4
VSS
V19
VSS
Y12
VSS
R12
VDDCORE
U5
VSS
V20
VSS
Y13
VSS
R13
VSS
U6
VDDI/O
V21
PE15TN00
Y14
VSS
Alt
1
Table 18 PES22H16 Signal Pin-Out (Part 3 of 4)
23 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
1
AB10
VSS
AB11
PEREFCLKN3
Alt
Y15
VSS
AA6
PE7RN00
AA19
GPIO_05
Y16
VSS
AA7
VSS
AA20
VDDI/O
Y17
VSS
AA8
PE6TP00
AA21
GPIO_12
1
AB12
VSS
Y18
GPIO_00
AA9
PE7TP00
AA22
GPIO_14
1
AB13
PE12TN00
Y19
GPIO_07
1
AA10
VSS
AB1
VDDI/O
AB14
PE13TN00
Y20
GPIO_09
1
AA11
PEREFCLKP3
AB2
VSS
AB15
VSS
Y21
VSS
AA12
VSS
AB3
SWMODE_2
AB16
PE12RP00
Y22
VSS
AA13
PE12TP00
AB4
VSS
AB17
PE13RP00
AA1
VSS
AA14
PE13TP00
AB5
PE6RP00
AB18
VSS
AA2
VDDI/O
AA15
VSS
AB6
PE7RP00
AB19
GPIO_02
AA3
SWMODE_3
AA16
PE12RN00
AB7
VSS
AB20
GPIO_10
1
AA4
VSS
AA17
PE13RN00
AB8
PE6TN00
AB21
GPIO_13
1
AA5
PE6RN00
AA18
VSS
AB9
PE7TN00
AB22
GPIO_15
Table 18 PES22H16 Signal Pin-Out (Part 4 of 4)
Alternate Signal Functions
Pin
GPIO
Alternate
Pin
GPIO
Alternate
AA19
GPIO_05
GPEN
E6
GPIO_17
P12RSTN
V17
GPIO_06
P1RSTN
B2
GPIO_18
P13RSTN
Y19
GPIO_07
P2RSTN
C3
GPIO_19
P14RSTN
W19
GPIO_08
P3RSTN
D5
GPIO_20
P15RSTN
Y20
GPIO_09
P4RSTN
C2
GPIO_21
IOEXPINTN0
AB20
GPIO_10
P5RSTN
D4
GPIO_23
IOEXPINTN2
V18
GPIO_11
P6RSTN
D2
GPIO_24
IOEXPINTN3
AA21
GPIO_12
P7RSTN
E5
GPIO_26
IOEXPINTN5
AB21
GPIO_13
P8RSTN
D3
GPIO_27
IOEXPINTN6
AA22
GPIO_14
P9RSTN
E4
GPIO_28
IOEXPINTN7
AB22
GPIO_15
P10RSTN
E3
GPIO_31
IOEXPINTN10
A2
GPIO_16
P11RSTN
—
—
—
Table 19 PES22H16 Alternate Signal Functions
24 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Power Pins
VDDCore
VDDCore
VDDCore
VDDCore
VDDIO
VDDPE
VDDPE
VDDPEA
VTTPE
F10
J9
M8
P15
A1
E7
P6
E11
E9
F11
J11
M9
R8
C1
E16
P17
E12
E10
F12
J12
M11
R9
D19
E17
R5
L5
E13
F13
J14
M12
R11
F5
F7
R6
L18
E14
G8
J15
M14
R12
F6
F8
R17
M5
J5
G9
K8
M15
R14
F16
F9
T6
M18
J18
G11
K9
N8
R15
F17
F14
T17
V11
K5
G12
K11
N9
T8
G5
F15
T18
W11
K18
G14
K12
N11
T9
G17
G6
U7
N5
G15
K14
N12
T11
U6
H5
U8
N18
H8
K15
N14
T12
U16
H6
U9
P5
H9
L8
N15
T14
U17
H17
U14
P18
H11
L9
P8
T15
V5
H18
U15
V9
H12
L11
P9
U10
V6
J6
V8
V10
H14
L12
P11
U11
V16
J17
V14
V12
H15
L14
P12
U12
W15
K17
V15
V13
J8
L15
P14
U13
Y1
Y3
AA2
AA20
AB1
Table 20 PES22H16 Power Pins
25 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Ground Pins
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A3
C17
H16
L16
P4
U4
Y10
A6
D6
H20
L17
P7
U5
Y11
A9
D11
J3
L20
P10
U18
Y12
A11
E1
J4
M3
P13
U20
Y13
A13
E2
J7
M4
P16
U21
Y14
A16
E8
J10
M6
P20
U22
Y15
A22
E15
J13
M7
P21
V3
Y16
B1
F3
J16
M10
P22
V4
Y17
B3
F19
J20
M13
R3
V7
Y21
B6
F20
K3
M16
R4
V19
Y22
B9
G3
K4
M17
R7
V20
AA1
B11
G4
K6
M20
R10
W1
AA4
B13
G7
K7
M21
R13
W2
AA7
B16
G10
K10
M22
R16
W3
AA10
C4
G13
K13
N1
R18
W7
AA12
C5
G16
K16
N2
R20
W8
AA15
C6
G18
K20
N3
T1
W9
AA18
C7
G20
K21
N4
T2
W10
AB2
C8
G21
K22
N6
T3
W12
AB4
C9
G22
L1
N7
T4
W13
AB7
C10
H1
L2
N10
T5
W14
AB10
C11
H2
L3
N13
T7
W20
AB12
C12
H3
L4
N16
T10
Y5
AB15
C13
H4
L6
N17
T13
Y6
AB18
C14
H7
L7
N19
T16
Y7
C15
H10
L10
N20
T20
Y8
C16
H13
L13
P3
U3
Y9
Table 21 PES22H16 Ground Pins
26 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
CCLKDS
I
D20
System
CCLKUS
I
Y2
GPIO_00
I/O
Y18
GPIO_01
I/O
W16
GPIO_02
I/O
AB19
GPIO_03
I/O
W17
GPIO_04
I/O
W18
GPIO_05
I/O
AA19
GPIO_06
I/O
V17
GPIO_07
I/O
Y19
GPIO_08
I/O
W19
GPIO_09
I/O
Y20
GPIO_10
I/O
AB20
GPIO_11
I/O
V18
GPIO_12
I/O
AA21
GPIO_13
I/O
AB21
GPIO_14
I/O
AA22
GPIO_15
I/O
AB22
GPIO_16
I/O
A2
GPIO_17
I/O
E6
GPIO_18
I/O
B2
GPIO_19
I/O
C3
GPIO_20
I/O
D5
GPIO_21
I/O
C2
GPIO_23
I/O
D4
GPIO_24
I/O
D2
GPIO_26
I/O
E5
GPIO_27
I/O
D3
GPIO_28
I/O
E4
GPIO_29
I/O
D1
GPIO_30
I/O
F4
GPIO_31
I/O
E3
General Purpose Input/Output
Table 22 PES22H16 Alphabetical Signal List (Part 1 of 5)
27 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal Name
I/O Type
Location
Signal Category
JTAG_TCK
I
C22
JTAG
JTAG_TDI
I
B22
JTAG_TDO
O
B20
JTAG_TMS
I
A21
JTAG_TRST_N
I
E18
MSMBADDR_1
I
D18
MSMBADDR_2
I
C19
MSMBADDR_3
I
B19
MSMBADDR_4
I
C18
MSMBCLK
I/O
C20
MSMBDAT
I/O
A20
MSMBSMODE
I
A19
System
PE0RN00
I
T21
PCI Express
PE0RN01
I
R21
PE0RN02
I
M19
PE0RN03
I
J19
PE0RP00
I
T22
PE0RP01
I
R22
PE0RP02
I
L19
PE0RP03
I
K19
PE0TN00
O
L22
PE0TN01
O
J22
PE0TN02
O
H21
PE0TN03
O
F21
PE0TP00
O
L21
PE0TP01
O
J21
PE0TP02
O
H22
PE0TP03
O
F22
PE1RN00
I
G19
PE1RP00
I
H19
PE1TN00
O
E22
PE1TP00
O
E21
PE2RN00
I
D17
PE2RN01
I
D15
PE2RN02
I
D13
PE2RN03
I
B8
SMBus
Table 22 PES22H16 Alphabetical Signal List (Part 2 of 5)
28 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE2RP00
I
D16
PCI Express (Cont.)
PE2RP01
I
D14
PE2RP02
I
D12
PE2RP03
I
A8
PE2TN00
O
B18
PE2TN01
O
B17
PE2TN02
O
A15
PE2TN03
O
A14
PE2TP00
O
A18
PE2TP01
O
A17
PE2TP02
O
B15
PE2TP03
O
B14
PE3RN00
I
B7
PE3RP00
I
A7
PE3TN00
O
A12
PE3TP00
O
B12
PE4RN00
I
U2
PE4RP00
I
U1
PE4TN00
O
P1
PE4TP00
O
P2
PE5RN00
I
V2
PE5RP00
I
V1
PE5TN00
O
R1
PE5TP00
O
R2
PE6RN00
I
AA5
PE6RP00
I
AB5
PE6TN00
O
AB8
PE6TP00
O
AA8
PE7RN00
I
AA6
PE7RP00
I
AB6
PE7TN00
O
AB9
PE7TP00
O
AA9
PE8RN00
I
D10
PE8RP00
I
D9
PE8TN00
O
A5
PE8TP00
O
B5
Table 22 PES22H16 Alphabetical Signal List (Part 3 of 5)
29 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE9RN00
I
D8
PCI Express (Cont.)
PE9RP00
I
D7
PE9TN00
O
A4
PE9TP00
O
B4
PE10RN00
I
F2
PE10RP00
I
F1
PE10TN00
O
J1
PE10TP00
O
J2
PE11RN00
I
G2
PE11RP00
I
G1
PE11TN00
O
K1
PE11TP00
O
K2
PE12RN00
I
AA16
PE12RP00
I
AB16
PE12TN00
O
AB13
PE12TP00
O
AA13
PE13RN00
I
AA17
PE13RP00
I
AB17
PE13TN00
O
AB14
PE13TP00
O
AA14
PE14RN00
I
U19
PE14RP00
I
T19
PE14TN00
O
W21
PE14TP00
O
W22
PE15RN00
I
R19
PE15RP00
I
P19
PE15TN00
O
V21
PE15TP00
O
V22
PEREFCLKN0
I
N21
PEREFCLKN1
I
A10
PEREFCLKN2
I
M1
PEREFCLKN3
I
AB11
PEREFCLKP0
I
N22
PEREFCLKP1
I
B10
PEREFCLKP2
I
M2
PEREFCLKP3
I
AA11
Table 22 PES22H16 Alphabetical Signal List (Part 4 of 5)
30 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PERSTN
I
B21
System
REFCLKM
I
W4
PCI Express
RSTHALT
I
W5
System
SSMBADDR_1
I
D21
SMBus
SSMBADDR_2
I
E20
SSMBADDR_3
I
D22
SSMBADDR_5
I
F18
SSMBCLK
I/O
E19
SSMBDAT
I/O
C21
SWMODE_0
I
Y4
SWMODE_1
I
W6
SWMODE_2
I
AB3
SWMODE_3
I
AA3
System
VDDCORE, VDDPEA, VDDIO,
VDDPE, VTTPE
See Table 20 for a listing of power pins.
VSS
See Table 21 for a listing of ground pins.
Table 22 PES22H16 Alphabetical Signal List (Part 5 of 5)
31 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
PES22H16 Pinout — Top View
1
2
3
4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
A
A
B
B
C
C
D
D
X X
X X
E
E
F
F
G
G
H
H
J
X
X
J
K
X
X
K
L
L
M
M
N
X
X
N
P
X
X
P
R
R
T
T
U
U
X X
X X
V
V
W
W
Y
Y
AA
AA
AB
AB
1
2
3
4
5
VDDCore (Power)
VDDI/O (Power)
6
7 8
X
9 10 11 12 13 14 15 16 17 18 19 20 21 22
VTTPE (Power)
Vss (Ground)
Signals
VDDPE (Power)
VDDPEA (Power)
32 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
www.IDT.com
IDT
PES22H16 Package Drawing — 484-Pin BL484/BR484
33 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
www.IDT.com
IDT
PES22H16 Package Drawing — Page Two
34 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Revision History
April 7, 2008: Publication of Preliminary data sheet with 23x23mm FCBGA package option.
April 16, 2008: In Table 16, Thermal Specifications, revised values for θJA, θJB, and θJC.
November 17, 2008: In Table 15, Power Consumption, changed Watts value for typical PCIe Termination Supply from 0.9 to 0.8 and changed Total
Typical Power from 5.018 to 4.92.
October 21, 2009: Added Industrial temperature to ordering codes on page 36.
35 of 36
October 21, 2009
IDT 89HPES22H16 Data Sheet
Ordering Information
NN
A
AAA
NNANN
AA
Product
Family
Operating
Voltage
Device
Family
Product
Detail
Device
Revision
AA
Legend
A = Alpha Character
N = Numeric Character
A
Package Temp Range
Blank
I
Commercial Temperature
(0°C to +70°C Ambient)
Industrial Temperature
(-40° C to +85° C Ambient)
BL
BR
484-ball FCBGA
484-ball FCBGA, RoHS
ZA
ZA revision
22H16
22-lane, 16-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES22H16ZABL
484-ball FCBGA package, Commercial Temperature
89HPES22H16ZABR
484-ball RoHS FCBGA package, Commercial Temperature
89HPES22H16ZABLI
484-ball FCBGA package, Industrial Temperature
89HPES22H16ZABRI
484-ball RoHS FCBGA package, Industrial Temperature
®
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
36 of 36
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
October 21, 2009
工商网监
湘ICP备2023018690号
