89HPES24N3A
Data Sheet
24-Lane 3-Port
PCI Express® Switch
®
Device Overview
Flexible Architecture with Numerous Configuration Options
– Automatic per port link width negotiation to x8, x4, x2 or x1
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
◆
Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates twenty-four 2.5 Gbps embedded SerDes with 8B/
10B encoder/decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Supports ECRC and Advanced Error Reporting
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC and
server motherboards
◆
The 89HPES24N3A is a member of the IDT PRECISE™ family of
PCI Express® switching solutions. The PES24N3A is a 24-lane, 3-port
peripheral chip that performs PCI Express packet switching with a
feature set optimized for high performance applications such as servers,
storage, and communications/networking. It provides connectivity and
switching functions between a PCI Express upstream port and two
downstream ports and supports switching between downstream ports.
Features
◆
High Performance PCI Express Switch
– Twenty-four 2.5 Gbps PCI Express lanes
– Three switch ports
– Upstream port configurable up to x8
– Downstream ports configurable up to x8
– Low-latency cut-through switch architecture
– Support for Max Payload Size up to 2048 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Block Diagram
3-Port Switch Core
Frame Buffer
Port
Arbitration
Route Table
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Multiplexer / Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
...
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
...
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
...
Phy
Logical
Layer
SerDes
24 PCI Express Lanes
x8 Upstream Port and Two x8 Downstream Ports
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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© 2008 Integrated Device Technology, Inc.
April 23, 2008
DSC 6921
IDT 89HPES24N3A Data Sheet
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3hot and
D3cold
– Unused SerDes are disabled
◆
Testability and Debug Features
– Ability to read and write any internal register via the SMBus
◆
Eight General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
◆
Packaged in 27x27mm 420 ball BGA with 1mm ball spacing
◆
Product Description
Utilizing standard PCI Express interconnect, the PES24N3A
provides the most efficient I/O connectivity solution for applications
requiring high throughput, low latency, and simple board layout with a
minimum number of board layers. It provides connectivity for up to 3
ports across 24 integrated serial lanes. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification revision 1.1.
SMBus Interface
The PES24N3A contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES24N3A,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configuration register values of the PES24N3A to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Bit
Slave
SMBus
Address
Master
SMBus
Address
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 2, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 2(a), the master and slave SMBuses are tied together and the
PES24N3A acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES24N3A registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES24N3A may be configured to operate in a split configuration as
shown in Figure 2(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES24N3A supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
Six pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus
address pins. In the slave interface, these address pins allow the
SMBus address to which the device responds to be configured. In the
master interface, these address pins allow the SMBus address of the
serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by
sampling the corresponding address pins. When the pins are sampled,
the resulting address is assigned as shown in Table 1.
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
Table 1 Master and Slave SMBus Address Assignment
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IDT 89HPES24N3A Data Sheet
PES24N3A
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES24N3A
SSMBCLK
SSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
MSMBCLK
MSMBDAT
Processor
SMBus
Master
...
Other
SMBus
Devices
Serial
EEPROM
(b) Split Configuration and Management Buses
(a) Unified Configuration and Management Bus
Figure 2 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES24N3A supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES24N3A
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES24N3A generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES24N3A. In response to an I/O expander interrupt, the PES24N3A generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES24N3A provides eight General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO
pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
The PES24N3A is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES24N3A can operate either as a store and forward or cutthrough switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with
sophisticated resource management to enable efficient switching and I/O connectivity for servers, storage, and embedded applications.
Processor
North
Bridge
PES24N3A
PCI Express
Slots
PES24N3A
I/O
10GbE
I/O
10GbE
Memory
Memory
Memory
Memory
PES24N3A
I/O
SATA
I/O
SATA
Figure 3 I/O Expansion Application
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IDT 89HPES24N3A Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES24N3A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Note: In the PES24N3A, the two downstream ports are labeled port 2 and port 4.
Signal
Type
Name/Description
PE0RP[7:0]
PE0RN[7:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PE0TP[7:0]
PE0TN[7:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for port 0. Port 0 is the upstream port.
PE2RP[7:0]
PE2RN[7:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PE2TP[7:0]
PE2TN[7:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for port 2.
PE4RP[7:0]
PE4RN[7:0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PE4TP[7:0]
PE4TN[7:0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pairs for port 4.
PEREFCLKP[2:1]
PEREFCLKN[2:1]
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus. It is active and generating the clock only
when the EEPROM or I/O Expanders are being accessed.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Table 3 SMBus Interface Pins
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IDT 89HPES24N3A Data Sheet
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
Table 4 General Purpose I/O Pins
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a common clock is being used between the downstream device
and the downstream port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a common clock is being used between the upstream device and
the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 KHz. This value
may not be overridden.
Table 5 System Pins (Part 1 of 2)
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IDT 89HPES24N3A Data Sheet
Signal
Type
Name/Description
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside
PES24N3A and initiates a PCI Express fundamental reset.
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES24N3A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[3:0]
I
Switch Mode. These configuration pins determine the PES24N3A switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
Table 5 System Pins (Part 2 of 2)
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
Table 7 Power and Ground Pins
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IDT 89HPES24N3A Data Sheet
Signal
Type
Name/Description
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 7 Power and Ground Pins
Pin Characteristics
Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
PCI Express Interface
SMBus
Pin Name
PE0RN[7:0]
Buffer
I/O
Type
I
CML
Serial link
Diff. Clock
Input
PE0RP[7:0]
I
PE0TN[7:0]
O
PE0TP[7:0]
O
PE2RN[7:0]
I
PE2RP[7:0]
I
PE2TN[7:0]
O
PE2TP[7:0]
O
PE4RN[7:0]
I
PE4RP[7:0]
I
PE4TN[7:0]
O
PE4TP[7:0]
O
PEREFCLKN[2:1]
I
Internal
Resistor1
PEREFCLKP[2:1]
I
LVPECL/
CML
REFCLKM
I
LVTTL
Input
pull-down
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
Notes
Refer to Table 9
2
pull-up on board
MSMBCLK
I/O
MSMBDAT
I/O
STI
I
Input
SSMBCLK
I/O
STI
pull-up on board
SSMBDAT
I/O
STI
pull-up on board
GPIO[7:0]
I/O
SSMBADDR[5,3:1]
General Purpose I/O
Type
STI
LVTTL
High Drive
pull-up on board
pull-up
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
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IDT 89HPES24N3A Data Sheet
Type
Buffer
I/O
Type
Internal
Resistor1
CCLKDS
I
LVTTL
Input
pull-up
CCLKUS
I
pull-up
MSMBSMODE
I
pull-down
PERSTN
I
RSTHALT
I
pull-down
SWMODE[3:0]
I
pull-down
JTAG_TCK
I
Function
System Pins
EJTAG / JTAG
Pin Name
LVTTL
STI
pull-up
STI
pull-up
JTAG_TDI
I
JTAG_TDO
O
JTAG_TMS
I
STI
pull-up
JTAG_TRST_N
I
STI
pull-up
Notes
External pull-down
Table 8 Pin Characteristics (Part 2 of 2)
1.
Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down.
2. Schmitt Trigger Input (STI).
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IDT 89HPES24N3A Data Sheet
Logic Diagram — PES24N3A
2
PEREFCLKP
PE0TP[0]
2
PEREFCLKN
PE0TN[0]
...
Reference
Clocks
REFCLKM
PE0TP[7]
PE0RP[0]
PE0TN[7]
PE0RN[0]
...
PE2TP[0]
PE2TN[0]
PE0RP[7]
...
PCI Express
Switch
SerDes Input
Port 0
PE0RN[7]
PE2TP[7]
PE2TN[7]
PE2RP[0]
PE2RP[7]
PE4TN[0]
PES24N3A
PE2RN[7]
PE4TP[7]
PE4TN[7]
PE4RP[0]
Master
SMBus Interface
Slave
SMBus Interface
PE4RN[0]
...
PCI Express
Switch
SerDes Input
Port 4
PCI Express
Switch
SerDes Output
Port 2
PE4TP[0]
...
PE2RN[0]
...
PCI Express
Switch
SerDes Input
Port 2
PCI Express
Switch
SerDes Output
Port 0
8
GPIO[7:0]
PE4RP[7]
PCI Express
Switch
SerDes Output
Port 4
General Purpose
I/O
PE4RN[7]
MSMBADDR[4:1]
JTAG_TCK
4
JTAG_TDI
MSMBCLK
JTAG_TDO
MSMBDAT
JTAG_TMS
SSMBADDR[5,3:1]
JTAG
JTAG_TRST_N
4
SSMBCLK
SSMBDAT
VDDCORE
System
Functions
MSMBSMODE
VDDIO
CCLKDS
VDDPE
CCLKUS
VDDAPE
RSTHALT
VSS
PERSTN
SWMODE[3:0]
Power/Ground
VTTPE
4
Figure 4 PES24N3A Logic Diagram
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IDT 89HPES24N3A Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Min
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
RT
Termination Resistor
Typical
50
0.6
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
110
Ohms
Table 9 Input Clock Requirements
1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3.
RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4. AC coupling required.
AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
399.88
400
400.12
ps
0.7
.9
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
D+ / D- Tx output rise/fall time
50
TTX- IDLE-MIN
Minimum time in idle
50
TTX-IDLE-SET-TO-
Maximum time to transition to a valid Idle after sending
an Idle ordered set
20
UI
IDLE
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
20
UI
500
1300
ps
400
400.12
ps
UI
0.15
90
UI
ps
UI
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
PCIe Receive
UI
Unit Interval
399.88
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
0.4
UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89HPES24N3A Data Sheet
Max1
Units
Max time between jitter median & max deviation
0.3
UI
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
Lane to lane input skew
20
ns
Parameter
Min1
Description
TRX-EYE-MEDIUM TO
Typical1
MAX JITTER
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol
Reference
Min Max Unit
Edge
Timing
Diagram
Reference
GPIO
GPIO[7:0]1
Tpw2
None
50
—
ns
Table 11 GPIO AC Timing Characteristics
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2. The values for this symbol were determined by calculation, not by testing.
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
50.0
—
ns
See Figure 5.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
—
20
ns
—
20
ns
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
JTAG_TDO
Tsu_16b
Thld_16b
Tdo_16c
Tdz_16c
JTAG_TRST_N
JTAG_TCK rising
JTAG_TCK falling
2
Tpw_16d2
none
Table 12 JTAG AC Timing Characteristics
1.
The JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2.
The values for this symbol were determined by calculation, not by testing.
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IDT 89HPES24N3A Data Sheet
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 5 JTAG AC Timing Waveform
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
VDDCORE
Internal logic supply
0.9
1.0
1.1
V
VDDI/O
I/O supply except for SerDes LVPECL/CML
3.0
3.3
3.6
V
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 13 PES24N3A Operating Voltages
Power-Up Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES24N3A, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels. The power-down sequence must be in the reverse order of the
power-up sequence.
12 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Table 14 PES24N3A Operating Temperatures
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Core Supply
PCIe Digital
Supply
PCIe Analog
Supply
PCIe Termination Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.5V
Max
1.575V
Typ
3.3V
Max
3.6V
Typ
Power
Max
Power
mA
705
928
1037
1247
415
455
520
617
1
1
2.9W
3.9W
Watts
0.705
1.02
1.037
1.37
0.415
0.50
0.78
0.97
0.003
0.004
mA
676
845
873
1004
409
434
360
408
1
1
2.5W
3.2W
Watts
0.676
0.93
0.873
1.104
0.41
0.477
0.36
0.643
0.003
0.004
Number of active
Lanes per Port
8/8/8
8/4/4
I/O Supply
Total
Table 15 PES24N3A Power Consumption
Thermal Considerations
This section describes thermal considerations for the PES24N3A (27mm2 BXG420 package). The data in Table 16 below contains information that
is relevant to the thermal performance of the PES24N3A switch.
Symbol
Parameter
Value
TJ(max)
Junction Temperature
125
o
C
Maximum
70
oC
Maximum for commercial-rated products
10.6
oC/W
Zero air flow
8.5
o
C/W
1 m/S air flow
7.6
oC/W
2 m/S air flow
TA(max)
θJA(effective)
Ambient Temperature
Effective Thermal Resistance, Junction-to-Ambient
Units
θJB
Thermal Resistance, Junction-to-Board
6.8
oC/W
θJC
Thermal Resistance, Junction-to-Case
0.7
o
P
Power Dissipation of the Device
3.9
Watts
Conditions
C/W
Maximum
Table 16 Thermal Specifications for PES24N3A, 27x27 mm BXG420 Package
Note: The parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance
can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective
θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card.
13 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Heat Sink
Table 17 lists heat sink requirements for the PES24N3A under three common usage scenarios. As shown in this table, a heat sink is not required
in most cases.
.
Air Flow
Board Size
Board Layers
Heat Sink Requirement
Zero
3.9”x6.2” (ExpressModule form factor) or larger
10 or more
No heat sink required
Zero
Any
14 or more
No heat sink required
1 m/S or more
Any
Any
No heat sink required
Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics
Thermal Usage Examples
The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surroundings in the absence of a
heat sink. The general formula to determine θJA is:
θJA = (TJ - TA)/P
Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the
maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is:
TJ(actual) = TA + P * θJA(eff) = 70oC + 3.9W * 8.5W/oC = 103oC
The actual TJ of 103oC is well below the maximum TJ of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in
this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should be added to the device
based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is:
TA(allowed) = TJ(desired) - (P * θJA(effective))
TA(allowed) = 100oC - (3.9W * 8.5W/oC) = 100oC - 33oC = 67oC
An appropriate level of increased air flow and/or a heat sink can be added to achieve this lower ambient temperature. Please contact
ssdhelp@idt.com for further assistance.
14 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
Conditions
PCIe Transmit
VTX-DIFFp-p
VTX-DE-RATIO
Differential peak-to-peak output voltage
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
Abs delta of DC common mode voltage
between D+ and D-
25
mV
Electrical idle diff peak output
20
mV
Voltage change during receiver detection
600
mV
active-idle-delta
VTX-CM-DC-linedelta
VTX-Idle-DiffP
Serial Link
(cont.)
Min1
Description
VTX-RCV-Detect
-0.1
1
RLTX-DIFF
Transmitter Differential Return loss
12
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
15
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
Differential input impedance (DC)
80
100
120
Ω
Single-ended input impedance
40
50
60
Ω
200k
350k
PCIe Receive
ZRX-DIFF-DC
ZRX-COMM-DC
ZRX-COMM-HIGH- Powered down input common mode
impedance (DC)
Z-DC
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 18 DC Electrical Characteristics (Part 1 of 2)
15 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
CIN
—
—
8.5
pF
—
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Capacitance
Leakage
Table 18 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
16 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Package Pinout — 420-BGA Signal Pinout for PES24N3A
The following table lists the pin numbers and signal names for the PES24N3A device.
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
A1
VSS
B9
MSMBDAT
C17
VDDIO
D25
VSS
A2
VSS
B10
SSMBADDR_2
C18
VSS
D26
PEREFCLKN2
A3
VSS
B11
SSMBADDR_5
C19
VDDIO
E1
VSS
A4
JTAG_TDI
B12
SSMBDAT
C20
VSS
E2
VSS
A5
JTAG_TMS
B13
NC
C21
VDDIO
E3
VSS
A6
MSMBADDR_1
B14
SWMODE_0
C22
VSS
E4
VSS
A7
MSMBADDR_3
B15
SWMODE_2
C23
VDDIO
E5
VSS
A8
MSMBCLK
B16
NC
C24
VSS
E6
VDDCORE
A9
SSMBADDR_1
B17
VDDIO
C25
VSS
E7
VDDCORE
A10
SSMBADDR_3
B18
GPIO_00
1
C26
PEREFCLKP2
E8
VSS
A11
SSMBCLK
B19
GPIO_02
1
D1
PEREFCLKP1
E9
VDDCORE
A12
CCLKUS
B20
GPIO_04
1
D2
VSS
E10
VSS
A13
CCLKDS
B21
GPIO_06
D3
VSS
E11
VDDCORE
A14
NC
B22
MSMBSMODE
D4
VSS
E12
VSS
A15
SWMODE_1
B23
REFCLKM
D5
VDDCORE
E13
VDDCORE
A16
SWMODE_3
B24
VDDIO
D6
VDDCORE
E14
VSS
A17
PERSTN
B25
VSS
D7
VSS
E15
VDDCORE
A18
RSTHALT
B26
VSS
D8
VDDCORE
E16
VSS
A19
GPIO_01
C1
PEREFCLKN1
D9
VSS
E17
VDDCORE
A20
GPIO_03
C2
VSS
D10
VDDCORE
E18
VSS
A21
GPIO_05
C3
VSS
D11
VSS
E19
VDDCORE
A22
GPIO_07
C4
VDDCORE
D12
VDDCORE
E20
VDDCORE
A23
VSS
C5
VDDIO
D13
VDDCORE
E21
VDDCORE
A24
VSS
C6
VSS
D14
VSS
E22
VSS
A25
VSS
C7
VDDIO
D15
VDDCORE
E23
VSS
A26
VSS
C8
VSS
D16
VSS
E24
VSS
B1
VSS
C9
VDDIO
D17
VDDCORE
E25
VSS
B2
VSS
C10
VSS
D18
VDDCORE
E26
VSS
B3
VDDIO
C11
VDDIO
D19
VDDCORE
F1
VDDCORE
B4
JTAG_TCK
C12
VSS
D20
VSS
F2
VDDCORE
B5
JTAG-TDO
C13
VDDIO
D21
VDDCORE
F3
VDDAPE
B6
JTAG-TRST_N
C14
VDDCORE
D22
VDDCORE
F4
VSS
B7
MSMBADDR_2
C15
VDDIO
D23
VSS
F5
VSS
B8
MSMBADDR_4
C16
VDDCORE
D24
VSS
F22
VSS
1
1
Alt
Table 19 PES24N3A 420-pin Signal Pin-Out (Part 1 of 3)
17 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
F23
VSS
K4
VDDAPE
P1
VDDCORE
U24
VDDPE
F24
VDDAPE
K5
VDDAPE
P2
VSS
U25
PE4TP05
F25
VDDCORE
K22
VDDAPE
P3
VTTPE
U26
PE4TN05
F26
VDDCORE
K23
VDDAPE
P4
VTTPE
V1
VDDCORE
G1
PE2TN07
K24
VDDAPE
P5
VSS
V2
VSS
G2
PE2TP07
K25
VSS
P22
VSS
V3
VDDAPE
G3
VDDPE
K26
VSS
P23
VTTPE
V4
VDDAPE
G4
PE2RN07
L1
PE2TN05
P24
VTTPE
V5
VDDAPE
G5
PE2RP07
L2
PE2TP05
P25
VSS
V22
VDDAPE
G22
PE4RP00
L3
VDDPE
P26
VDDCORE
V23
VDDAPE
G23
PE4RN00
L4
PE2RN05
R1
PE2TN03
V24
VDDAPE
G24
VDDPE
L5
PE2RP05
R2
PE2TP03
V25
VSS
G25
PE4TP00
L22
PE4RP02
R3
VDDPE
V26
VDDCORE
G26
PE4TN00
L23
PE4RN02
R4
PE2RN03
W1
PE2TN01
H1
VSS
L24
VDDPE
R5
PE2RP03
W2
PE2TP01
H2
VSS
L25
PE4TP02
R22
PE4RP04
W3
VDDPE
H3
VTTPE
L26
PE4TN02
R23
PE4RN04
W4
PE2RN01
H4
VTTPE
M1
VDDCORE
R24
VDDPE
W5
PE2RP01
H5
VSS
M2
VSS
R25
PE4TP04
W22
PE4RP06
H22
VSS
M3
VTTPE
R26
PE4TN04
W23
PE4RN06
H23
VTTPE
M4
VTTPE
T1
VDDCORE
W24
VDDPE
H24
VTTPE
M5
VSS
T2
VSS
W25
PE4TP06
H25
VSS
M22
VSS
T3
VDDAPE
W26
PE4TN06
H26
VSS
M23
VTTPE
T4
VDDAPE
Y1
VSS
J1
PE2TN06
M24
VTTPE
T5
VSS
Y2
VSS
J2
PE2TP06
M25
VSS
T22
VSS
Y3
VTTPE
J3
VDDPE
M26
VDDCORE
T23
VDDAPE
Y4
VTTPE
J4
PE2RN06
N1
PE2TN04
T24
VDDAPE
Y5
VSS
J5
PE2RP06
N2
PE2TP04
T25
VSS
Y22
VSS
J22
PE4RP01
N3
VDDPE
T26
VDDCORE
Y23
VTTPE
J23
PE4RN01
N4
PE2RN04
U1
PE2TN02
Y24
VTTPE
J24
VDDPE
N5
PE2RP04
U2
PE2TP02
Y25
VSS
J25
PE4TP01
N22
PE4RP03
U3
VDDPE
Y26
VSS
J26
PE4TN01
N23
PE4RN03
U4
PE2RN02
AA1
PE2TN00
K1
VSS
N24
VDDPE
U5
PE2RP02
AA2
PE2TP00
K2
VSS
N25
PE4TP03
U22
PE4RP05
AA3
VDDPE
K3
VDDAPE
N26
PE4TN03
U23
PE4RN05
AA4
PE2RN00
Alt
Table 19 PES24N3A 420-pin Signal Pin-Out (Part 2 of 3)
18 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
AA5
PE2RP00
AC3
VDDCORE
AD11
VDDPE
AE19
PE0TP01
AA22
PE4RP07
AC4
VDDCORE
AD12
VTTPE
AE20
VSS
AA23
PE4RN07
AC5
VDDCORE
AD13
VDDPE
AE21
PE0TP00
AA24
VDDPE
AC6
VTTPE
AD14
VTTPE
AE22
VSS
AA25
PE4TP07
AC7
PE0RN07
AD15
VDDPE
AE23
VDDCORE
AA26
PE4TN07
AC8
VDDAPE
AD16
VDDAPE
AE24
VDDCORE
AB1
VSS
AC9
PE0RN06
AD17
VSS
AE25
VSS
AB2
VSS
AC10
VDDAPE
AD18
VDDPE
AE26
VSS
AB3
VDDCORE
AC11
PE0RN05
AD19
VDDPE
AF1
VSS
AB4
VDDCORE
AC12
VTTPE
AD20
VTTPE
AF2
VSS
AB5
VDDCORE
AC13
PE0RN04
AD21
VDDPE
AF3
VDDCORE
AB6
VSS
AC14
VTTPE
AD22
VSS
AF4
VDDCORE
AB7
PE0RP07
AC15
PE0RN03
AD23
VDDCORE
AF5
VDDCORE
AB8
VSS
AC16
VDDAPE
AD24
VDDCORE
AF6
VSS
AB9
PE0RP06
AC17
PE0RN02
AD25
VSS
AF7
PE0TN07
AB10
VDDAPE
AC18
VDDAPE
AD26
VSS
AF8
VSS
AB11
PE0RP05
AC19
PE0RN01
AE1
VSS
AF9
PE0TN06
AB12
VSS
AC20
VTTPE
AE2
VSS
AF10
VDDCORE
AB13
PE0RP04
AC21
PE0RN00
AE3
VDDCORE
AF11
PE0TN05
AB14
VDDAPE
AC22
VSS
AE4
VDDCORE
AF12
VDDCORE
AB15
PE0RP03
AC23
VDDCORE
AE5
VSS
AF13
PE0TN04
AB16
VSS
AC24
VDDCORE
AE6
VSS
AF14
VDDCORE
AB17
PE0RP02
AC25
VSS
AE7
PE0TP07
AF15
PE0TN03
AB18
VDDAPE
AC26
VSS
AE8
VSS
AF16
VDDCORE
AB19
PE0RP01
AD1
VSS
AE9
PE0TP06
AF17
PE0TN02
AB20
VSS
AD2
VSS
AE10
VSS
AF18
VSS
AB21
PE0RP00
AD3
VDDCORE
AE11
PE0TP05
AF19
PE0TN01
AB22
VSS
AD4
VDDCORE
AE12
VSS
AF20
VSS
AB23
VDDCORE
AD5
VDDCORE
AE13
PE0TP04
AF21
PE0TN00
AB24
VDDCORE
AD6
VTTPE
AE14
VSS
AF22
VSS
AB25
VSS
AD7
VSS
AE15
PE0TP03
AF23
VDDCORE
AB26
VSS
AD8
VDDPE
AE16
VSS
AF24
VDDCORE
AC1
VSS
AD9
VSS
AE17
PE0TP02
AF25
VSS
AC2
VSS
AD10
VDDPE
AE18
VSS
AF26
VSS
Alt
Table 19 PES24N3A 420-pin Signal Pin-Out (Part 3 of 3)
19 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Power Pins
VDDCore
VDDCore
VDDCore
VDDIO
VDDPE
VDDAPE
VTTPE
C4
F2
AE3
B3
G3
F3
H3
C14
F25
AE4
B17
G24
F24
H4
C16
F26
AE23
B24
J3
K3
H23
D5
M1
AE24
C5
J24
K4
H24
D6
M26
AF3
C7
L3
K5
M3
D8
P1
AF4
C9
L24
K22
M4
D10
P26
AF5
C11
N3
K23
M23
D12
T1
AF10
C13
N24
K24
M24
D13
T26
AF12
C15
R3
T3
P3
D15
V1
AF14
C17
R24
T4
P4
D17
V26
AF16
C19
U3
T23
P23
D18
AB3
AF23
C21
U24
T24
P24
D19
AB4
AF24
C23
W3
V3
Y3
D21
AB5
W24
V4
Y4
D22
AB23
AA3
V5
Y23
E6
AB24
AA24
V22
Y24
E7
AC3
AD8
V23
AC6
E9
AC4
AD10
V24
AC12
E11
AC5
AD11
AB10
AC14
E13
AC23
AD13
AB14
AC20
E15
AC24
AD15
AB18
AD6
E17
AD3
AD18
AC8
AD12
E19
AD4
AD19
AC10
AD14
E20
AD5
AD21
AC16
AD20
E21
AD23
AC18
F1
AD24
AD16
Table 20 PES24N3A Power Pins
20 of 31
April 23, 2008
IDT 89HPES24N3A Data Sheet
Ground Pins
Vss
Vss
Vss
Vss
Vss
A1
D9
F22
Y1
AD22
A2
D11
F23
Y2
AD25
A3
D14
H1
Y5
AD26
A23
D16
H2
Y22
AE1
A24
D20
H5
Y25
AE2
A25
D23
H22
Y26
AE5
A26
D24
H25
AB1
AE6
B1
D25
H26
AB2
AE8
B2
E1
K1
AB6
AE10
B25
E2
K2
AB8
AE12
B26
E3
K25
AB12
AE14
C2
E4
K26
AB16
AE16
C3
E5
M2
AB20
AE18
C6
E8
M5
AB22
AE20
C8
E10
M22
AB25
AE22
C10
E12
M25
AB26
AE25
C12
E14
P2
AC1
AE26
C18
E16
P5
AC2
AF1
C20
E18
P22
AC22
AF2
C22
E22
P25
AC25
AF6
C24
E23
T2
AC26
AF8
C25
E24
T5
AD1
AF18
D2
E25
T22
AD2
AF20
D3
E26
T25
AD7
AF22
D4
F4
V2
AD9
AF25
D7
F5
V25
AD17
AF26
Table 21 PES24N3A Ground Pins
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Alternate Signal Functions
Pin
GPIO
Alternate
B18
GPIO_00
P2RSTN
A19
GPIO_01
P4RSTN
B19
GPIO_02
IOEXPINTN0
B20
GPIO_04
IOEXPINTN2
A22
GPIO_07
GPEN
Table 22 PES24N3A Alternate Signal Functions
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
CCLKDS
I
A13
System
CCLKUS
I
A12
GPIO_00
I/O
B18
GPIO_01
I/O
A19
GPIO_02
I/O
B19
GPIO_03
I/O
A20
GPIO_04
I/O
B20
GPIO_05
I/O
A21
GPIO_06
I/O
B21
GPIO_07
I/O
A22
JTAG_TCK
I
B4
JTAG_TDI
I
A4
JTAG_TMS
I
A5
JTAG-TDO
O
B5
JTAG-TRST_N
I
B6
MSMBADDR_1
I
A6
MSMBADDR_2
I
B7
MSMBADDR_3
I
A7
MSMBADDR_4
I
B8
MSMBCLK
I/O
A8
MSMBDAT
I/O
B9
I
B22
MSMBSMODE
General Purpose Input/Output
JTAG
SMBus
System
Table 23 89PES24N3A Alphabetical Signal List (Part 1 of 5)
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Signal Name
I/O Type
Location
Signal Category
NC
A14
PCI Express
NC
B13
NC
B16
PE0RN00
I
AC21
PE0RN01
I
AC19
PE0RN02
I
AC17
PE0RN03
I
AC15
PE0RN04
I
AC13
PE0RN05
I
AC11
PE0RN06
I
AC9
PE0RN07
I
AC7
PE0RP00
I
AB21
PE0RP01
I
AB19
PE0RP02
I
AB17
PE0RP03
I
AB15
PE0RP04
I
AB13
PE0RP05
I
AB11
PE0RP06
I
AB9
PE0RP07
I
AB7
PE0TN00
O
AF21
PE0TN01
O
AF19
PE0TN02
O
AF17
PE0TN03
O
AF15
PE0TN04
O
AF13
PE0TN05
O
AF11
PE0TN06
O
AF9
PE0TN07
O
AF7
PE0TP00
O
AE21
PE0TP01
O
AE19
PE0TP02
O
AE17
PE0TP03
O
AE15
PE0TP04
O
AE13
PE0TP05
O
AE11
PE0TP06
O
AE9
PE0TP07
O
AE7
Table 23 89PES24N3A Alphabetical Signal List (Part 2 of 5)
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE2RN00
I
AA4
PCI Express (Cont.)
PE2RN01
I
W4
PE2RN02
I
U4
PE2RN03
I
R4
PE2RN04
I
N4
PE2RN05
I
L4
PE2RN06
I
J4
PE2RN07
I
G4
PE2RP00
I
AA5
PE2RP01
I
W5
PE2RP02
I
U5
PE2RP03
I
R5
PE2RP04
I
N5
PE2RP05
I
L5
PE2RP06
I
J5
PE2RP07
I
G5
PE2TN00
O
AA1
PE2TN01
O
W1
PE2TN02
O
U1
PE2TN03
O
R1
PE2TN04
O
N1
PE2TN05
O
L1
PE2TN06
O
J1
PE2TN07
O
G1
PE2TP00
O
AA2
PE2TP01
O
W2
PE2TP02
O
U2
PE2TP03
O
R2
PE2TP04
O
N2
PE2TP05
O
L2
PE2TP06
O
J2
PE2TP07
O
G2
PE4RN00
I
G23
PE4RN01
I
J23
PE4RN02
I
L23
PE4RN03
I
N23
Table 23 89PES24N3A Alphabetical Signal List (Part 3 of 5)
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE4RN04
I
R23
PCI Express (Cont.)
PE4RN05
I
U23
PE4RN06
I
W23
PE4RN07
I
AA23
PE4RP00
I
G22
PE4RP01
I
J22
PE4RP02
I
L22
PE4RP03
I
N22
PE4RP04
I
R22
PE4RP05
I
U22
PE4RP06
I
W22
PE4RP07
I
AA22
PE4TN00
O
G26
PE4TN01
O
J26
PE4TN02
O
L26
PE4TN03
O
N26
PE4TN04
O
R26
PE4TN05
O
U26
PE4TN06
O
W26
PE4TN07
O
AA26
PE4TP00
O
G25
PE4TP01
O
J25
PE4TP02
O
L25
PE4TP03
O
N25
PE4TP04
O
R25
PE4TP05
O
U25
PE4TP06
O
W25
PE4TP07
O
AA25
PEREFCLKN1
I
C1
PEREFCLKN2
I
D26
PEREFCLKP1
I
D1
PEREFCLKP2
I
C26
PERSTN
I
A17
System
REFCLKM
I
B23
PCI Express
RSTHALT
I
A18
System
Table 23 89PES24N3A Alphabetical Signal List (Part 4 of 5)
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Signal Name
I/O Type
Location
Signal Category
SSMBADDR_1
I
A9
SMBus
SSMBADDR_2
I
B10
SSMBADDR_3
I
A10
SSMBADDR_5
I
B11
SSMBCLK
I/O
A11
SSMBDAT
I/O
B12
SWMODE_0
I
B14
SWMODE_1
I
A15
SWMODE_2
I
B15
SWMODE_3
I
A16
SMBus
System
VDDCORE,
VDDAPE, VDDIO,
VDDPE, VTTPE
See Table 20 for a listing of power pins.
VSS
See Table 21 for a listing of ground pins.
Table 23 89PES24N3A Alphabetical Signal List (Part 5 of 5)
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April 23, 2008
IDT 89HPES24N3A Data Sheet
PES24N3A Pinout — Top View
1
2
3
4
5
6
7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
VDDCore (Power)
VTTPE (Power)
Vss (Ground)
VDDI/O (Power)
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April 23, 2008
IDT 89HPES24N3A Data Sheet
PES24N3A Package Drawing — 420-Pin BX420/BXG420
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April 23, 2008
IDT 89HPES24N3A Data Sheet
PES24N3A Package Drawing — Page Two
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Revision History
February 8, 2007: Initial publication.
April 4, 2007: In Table 3, revised description for MSMBCLK signal.
May 30, 2007: Added ZG device revision to Ordering Information.
November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements.
March 25, 2008: Added θJB and θJC parameters to Table 16, Thermal Specifications.
April 23, 2008: Added 1ZC device revision to Ordering Information.
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April 23, 2008
IDT 89HPES24N3A Data Sheet
Ordering Information
NN
A
AAA
NNAN
AAA
Product
Family
Operating
Voltage
Device
Family
Product
Detail
Device
Revision
AA
A
Package Temp Range
Legend
A = Alpha Character
N = Numeric Character
Blank
Commercial Temperature
(0°C to +70°C Ambient)
BX
BX420 420-ball BGA
BXG
BXG420 420-ball BGA, Green
ZC
ZG
1ZC
ZC revision
ZG revision
1ZC revision
24N3A
24-lane, 3-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES24N3AZCBX
420-pin BX420 package, Commercial Temperature
89HPES24N3AZGBX
420-pin BX420 package, Commercial Temperature
89HPES24N3A1ZCBX
420-pin BX420 package, Commercial Temperature
89HPES24N3AZCBXG
420-pin Green BX420 package, Commercial Temperature
89HPES24N3AZGBXG
420-pin Green BX420 package, Commercial Temperature
89HPES24N3A1ZCBXG
420-pin Green BX420 package, Commercial Temperature
®
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31 of 31
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April 23, 2008
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