89PES5T5
Data Sheet
5-Lane 5-Port PCI Express®
Switch
®
Device Overview
◆
The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral
chip that performs PCI Express Base switching. It provides connectivity
and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream
ports.
◆
Features
◆
◆
◆
High Performance PCI Express Switch
– Five 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x1
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆
◆
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates five 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC motherboards
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCIPM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
5-Port Switch Core / 5 PCI Express Lanes
Frame Buffer
Port
Arbitration
Route Table
Scheduler
Transaction Layer
Transaction Layer
Transaction Layer
Transaction Layer
Transaction Layer
Data Link Layer
Data Link Layer
Data Link Layer
Data Link Layer
Data Link Layer
Mux / Demux
Mux / Demux
Mux / Demux
Mux / Demux
Mux / Demux
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes
SerDes
SerDes
SerDes
SerDes
(Port 0)
(Port 2)
(Port 3)
(Port 4)
(Port 5)
Figure 1 Internal Block Diagram
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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© 2009 Integrated Device Technology, Inc.
May 7, 2009
IDT 89PES5T5 Data Sheet
◆
◆
11 General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect, the PES5T5 provides the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum number of board layers. It provides 2.5 GBps (20 Gbps) of aggregated, full-duplex
switching capacity through 5 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specification revision 1.1.
The PES5T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transaction layers in compliance with PCI Express Base specification Revision 1.1. The PES5T5 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity.
Processor
Processor
Memory
Memory
Memory
Memory
North
Bridge
South
Bridge
x1
PES5T5
x1
GE
LOM
x1
x1
x1
GE
LOM
GE
1394
Figure 2 I/O Expansion Application
SMBus Interface
The PES5T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES5T5, allowing every
configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of
the PES5T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an
external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
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IDT 89PES5T5 Data Sheet
Bit
Slave
SMBus
Address
Master
SMBus
Address
1
SSMBADDR[1]
MSMBADDR[1]
2
SSMBADDR[2]
MSMBADDR[2]
3
SSMBADDR[3]
MSMBADDR[3]
4
0
MSMBADDR[4]
5
SSMBADDR[5]
1
6
1
0
7
1
1
Table 1 Master and Slave SMBus Address Assignment
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
3(a), the master and slave SMBuses are tied together and the PES5T5 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES5T5 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES5T5 may be configured to operate in a split configuration as shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES5T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
PES5T5
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES5T5
SSMBCLK
SSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
MSMBCLK
MSMBDAT
Processor
SMBus
Master
...
Other
SMBus
Devices
Serial
EEPROM
(b) Split Configuration and Management Buses
(a) Unified Configuration and Management Bus
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES5T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES5T5 utilizes
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES5T5 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES5T5. In response to an I/O expander interrupt, the PES5T5 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
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IDT 89PES5T5 Data Sheet
General Purpose Input/Output
The PES5T5 provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These alternate
functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES5T5. Some of the functions listed may be multiplexed onto the same pin. The
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
Type
Name/Description
PE0RP[0]
PE0RN[0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0.
PE0TP[0]
PE0TN[0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pair for port 0.
PE2RP[0]
PE2RN[0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PE2TP[0]
PE2TN[0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pair for port 2.
PE3RP[0]
PE3RN[0]
I
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PE3TP[0]
PE3TN[0]
O
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit pair for port 3.
PE4RP[0]
PE4RN[0]
I
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
PE4TP[0]
PE4TN[0]
O
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit pair for port 4.
PE5RP[0]
PE5RN[0]
I
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
PE5TP[0]
PE5TN[0]
O
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit pair for port 5.
PEREFCLKP
PEREFCLKN
I
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal.
REFCLKM
I
PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
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IDT 89PES5T5 Data Sheet
Signal
Type
Name/Description
MSMBADDR[4:1]
I
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
MSMBCLK
I/O
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
MSMBDAT
I/O
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
SSMBADDR[5,3:1]
I
SSMBCLK
I/O
Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the slave SMBus.
SSMBDAT
I/O
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Slave SMBus Address. These pins determine the SMBus address to
which the slave SMBus interface responds.
Table 3 SMBus Interface Pins
Signal
Type
Name/Description
GPIO[0]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2
GPIO[1]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P4RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 4
GPIO[2]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN0
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 0 input
GPIO[3]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN1
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 1 input
GPIO[4]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN2
Alternate function pin type: Input
Alternate function: I/O Expander interrupt 2 input
GPIO[5]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[6]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Table 4 General Purpose I/O Pins (Part 1 of 2)
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IDT 89PES5T5 Data Sheet
Signal
Type
Name/Description
GPIO[7]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: GPEN
Alternate function pin type: Output
Alternate function: General Purpose Event (GPE) output
GPIO[8]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[9]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
GPIO[10]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
Table 4 General Purpose I/O Pins (Part 2 of 2)
Signal
Type
Name/Description
APWRDISN
I
Auxiliary Power Disable Input. When this pin is active, it disables the
device from using auxiliary power supply.
CCLKDS
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be override by modifying the SCLK bit in the downstream
port’s PCIELSTS register.
CCLKUS
I
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the PA_PCIELSTS register.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the
master SMBus should operate at 100 KHz instead of 400 kHz. This value
may not be overridden.
PERSTN
I
Fundamental Reset. Assertion of this signal resets all logic inside the
PES5T5 and initiates a PCI Express fundamental reset.
Table 5 System Pins (Part 1 of 2)
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IDT 89PES5T5 Data Sheet
Signal
Type
Name/Description
RSTHALT
I
Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES5T5 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device operation begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
SWMODE[2:0]
I
Switch Mode. These configuration pins determine the PES5T5 switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
WAKEN
I/O
Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through the WAKEDIR bit setting
in the WAKEUPCNTL register.
Table 5 System Pins (Part 2 of 2)
Signal
Type
Name/Description
JTAG_TCK
I
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI
I
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO
O
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS
I
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N
I
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
Type
Name/Description
VDDCORE
I
Core VDD. Power supply for core logic.
VDDIO
I
I/O VDD. LVTTL I/O buffer power supply.
VDDPE
I
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
VDDAPE
I
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
VTTPE
I
PCI Express Termination Power.
VSS
I
Ground.
Table 7 Power and Ground Pins
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IDT 89PES5T5 Data Sheet
Pin Characteristics
Note: Some input pads of the PES5T5 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left
floating can cause a slight increase in power consumption.
Function
PCI Express Interface
SMBus
Type
Buffer
I/O
Type
PE0RN[0]
I
CML
Serial Link
PE0RP[0]
I
Diff. Clock
Input
Pin Name
PE0TN[0]
O
PE0TP[0]
O
PE2RN[0]
I
PE2RP[0]
I
PE2TN[0]
O
PE2TP[0]
O
PE3RN[0]
I
PE3RP[0]
I
PE3TN[0]
O
PE3TP[0]
O
PE4RN[0]
I
PE4RP[0]
I
PE4TN[0]
O
PE4TP[0]
O
PE5RN[0]
I
PE5RP[0]
I
PE5TN[0]
O
PE5TP[0]
O
PEREFCLKN
I
PEREFCLKP
I
LVPECL/
CML
REFCLKM
I
LVTTL
Input
pull-down
MSMBADDR[4:1]
I
LVTTL
Input
pull-up
Notes
Refer toTable 9
1
MSMBCLK
I/O
STI
MSMBDAT
I/O
STI
SSMBADDR[5,3:1]
General Purpose I/O
Internal
Resistor
I
Input
SSMBCLK
I/O
STI
SSMBDAT
I/O
STI
GPIO[10:0]
I/O
LVTTL
High Drive
pull-up
pull-up
Table 8 Pin Characteristics (Part 1 of 2)
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IDT 89PES5T5 Data Sheet
Function
System Pins
Type
Buffer
I/O
Type
Internal
Resistor
APWRDISN
I
LVTTL
Input
pull-down
CCLKDS
I
Pin Name
1.
pull-up
CCLKUS
I
pull-up
MSMBSMODE
I
pull-down
PERSTN
I
RSTHALT
I
pull-down
SWMODE[2:0]
I
pull-down
WAKEN
EJTAG / JTAG
I/O
JTAG_TCK
I
JTAG_TDI
I
JTAG_TDO
O
JTAG_TMS
JTAG_TRST_N
Schmitt Trigger Input (STI).
Notes
open-drain
LVTTL
STI
pull-up
STI
pull-up
I
STI
pull-up
I
STI
pull-up
Table 8 Pin Characteristics (Part 2 of 2)
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IDT 89PES5T5 Data Sheet
Logic Diagram — PES5T5
Reference
Clock
PEREFCLKP
PE0TP[0]
PEREFCLKN
PE0TN[0]
REFCLKM
PCI Express
Switch
SerDes Input
Port 0
PCI Express
Switch
SerDes Input
Port 2
PE0RP[0]
PE2TP[0]
PE0RN[0]
PE2TN[0]
PE2RP[0]
PE3TP[0]
PE3RP[0]
PE4TN[0]
PES5T5
PE4RP[0]
PE5TN[0]
Master
SMBus Interface
Slave
SMBus Interface
PCI Express
Switch
SerDes Output
Port 4
PE4RN[0]
PE5TP[0]
PCI Express
Switch
SerDes Input
Port 5
PCI Express
Switch
SerDes Output
Port 3
PE3RN[0]
PE4TP[0]
PCI Express
Switch
SerDes Input
Port 4
PCI Express
Switch
SerDes Output
Port 2
PE2RN[0]
PE3TN[0]
PCI Express
Switch
SerDes Input
Port 3
PCI Express
Switch
SerDes Output
Port 0
PCI Express
Switch
SerDes Output
Port 5
PE5RP[0]
PE5RN[0]
11
MSMBADDR[4:1]
General Purpose
I/O
JTAG_TCK
4
JTAG_TDI
MSMBCLK
JTAG_TDO
MSMBDAT
SSMBADDR[5,3:1]
GPIO[10:0]
JTAG Pins
JTAG_TMS
4
JTAG_TRST_N
SSMBCLK
VDDCORE
SSMBDAT
VDDIO
VDDPE
System
Pins
VDDAPE
MSMBSMODE
CCLKDS
VSS
Power/Ground
VTTPE
CCLKUS
RSTHALT
PERSTN
SWMODE[2:0]
3
WAKEN
APWRDISN
Figure 4 PES5T5 Logic Diagram
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IDT 89PES5T5 Data Sheet
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14.
Parameter
Description
Min
Typical
Max
Unit
1251
MHz
60
%
0.2*RCUI
RCUI3
1.6
V
125
ps
PEREFCLK
RefclkFREQ
Input reference clock frequency range
100
RefclkDC2
Duty cycle of input clock
40
TR, TF
Rise/Fall time of input clocks
VSW
Differential input voltage swing4
Tjitter
Input clock jitter (cycle-to-cycle)
50
0.6
Table 9 Input Clock Requirements
1.
The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM.
2. ClkIn must be AC coupled. Use 0.01 — 0.1 µF ceramic capacitors.
3. RCUI (Reference Clock Unit Interval) refers to the reference clock period.
4.
AC coupling required.
AC Timing Characteristics
Parameter
Description
Min1
Typical1
Max1
Units
399.88
400
400.12
ps
0.7
.9
PCIe Transmit
UI
Unit Interval
TTX-EYE
Minimum Tx Eye Width
TTX-EYE-MEDIAN-toMAX-JITTER
Maximum time between the jitter median and maximum
deviation from the median
TTX-RISE, TTX-FALL
D+ / D- Tx output rise/fall time
50
TTX- IDLE-MIN
Minimum time in idle
50
TTX-IDLE-SET-TO-
20
UI
IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set
TTX-IDLE-TO-DIFF-
Maximum time to transition from valid idle to diff data
20
UI
UI
0.15
90
UI
ps
UI
DATA
TTX-SKEW
Transmitter data skew between any 2 lanes
500
1300
ps
TBTEn
Time from asserting Beacon TxEn to beacon being transmitted on the lane
30
80
ns
400
400.12
ps
PCIe Receive
UI
Unit Interval
399.88
TRX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance)
0.4
UI
Table 10 PCIe AC Timing Characteristics (Part 1 of 2)
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IDT 89PES5T5 Data Sheet
Max1
Units
Max time between jitter median & max deviation
0.3
UI
Unexpected Idle Enter Detect Threshold Integration Time
10
ms
Lane to lane input skew
20
ns
Parameter
Min1
Description
TRX-EYE-MEDIUM TO
Typical1
MAX JITTER
TRX-IDLE-DET-DIFFENTER TIME
TRX-SKEW
Table 10 PCIe AC Timing Characteristics (Part 2 of 2)
1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1
Signal
Symbol
Reference
Min Max Unit
Edge
Timing
Diagram
Reference
GPIO
GPIO[10:0]1
Tpw_13b2
None
50
—
ns
See Figure 5.
Table 11 GPIO AC Timing Characteristics
1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if
they are asynchronous.
2.
The values for this symbol were determined by calculation, not by testing.
EXTCLK
Tdo_13a
Tdo_13a
GPIO (synchronous output)
Tpw_13b
GPIO (asynchronous input)
Figure 5 GPIO AC Timing Waveform
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IDT 89PES5T5 Data Sheet
Signal
Symbol
Reference
Edge
Min
Max
Unit
Timing
Diagram
Reference
Tper_16a
none
25.0
50.0
ns
See Figure 6.
10.0
25.0
ns
2.4
—
ns
1.0
—
ns
JTAG_TCK falling
—
11.3
ns
—
11.3
ns
none
25.0
—
ns
JTAG
JTAG_TCK
Thigh_16a,
Tlow_16a
JTAG_TMS1,
JTAG_TDI
Tsu_16b
JTAG_TCK rising
Thld_16b
JTAG_TDO
Tdo_16c
Tdz_16c2
JTAG_TRST_N
Tpw_16d2
Table 12 JTAG AC Timing Characteristics
1. The
JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N
changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK
when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state.
2. The values for this symbol were determined by calculation, not by testing.
Tlow_16a
Tper_16a
Thigh_16a
JTAG_TCK
Thld_16b
Tsu_16b
JTAG_TDI
Thld_16b
Tsu_16b
JTAG_TMS
Tdo_16c
Tdz_16c
JTAG_TDO
Tpw_16d
JTAG_TRST_N
Figure 6 JTAG AC Timing Waveform
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May 7, 2009
IDT 89PES5T5 Data Sheet
Recommended Operating Supply Voltages
Symbol
Parameter
Minimum
Typical
Maximum
Unit
0.9
1.0
1.1
V
3.135
3.3
3.465
V
VDDCORE
Internal logic supply
VDDI/O
I/O supply except for SerDes LVPECL/CML
VDDPE
PCI Express Digital Power
0.9
1.0
1.1
V
VDDAPE
PCI Express Analog Power
0.9
1.0
1.1
V
VTTPE
PCI Express Serial Data Transmit
Termination Voltage
1.425
1.5
1.575
V
VSS
Common ground
0
0
0
V
Table 13 PES5T5 Operating Voltages
Power-Up/Power-Down Sequence
This section describes the sequence in which various voltages must be applied to the part during power-up to ensure proper functionality. For the
PES5T5, the power-up sequence must be as follows:
1. VDDI/O — 3.3V
2. VDDCore, VDDPE, VDDAPE — 1.0V
3. VTTPE — 1.5V
When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues
are avoided. There are no maximum time limitations in ramping to valid power levels.
The power-down sequence must be in the reverse order of the power-up sequence.
Recommended Operating Temperature
Grade
Temperature
Commercial
0°C to +70°C Ambient
Industrial
-40°C to +85°C Ambient
Table 14 PES5T5 Operating Temperatures
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May 7, 2009
IDT 89PES5T5 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13.
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13.
All power measurements assume that the part is mounted on a 10 layer printed circuit board with 0 LFM airflow.
Core Supply
PCIe Digital
Supply
PCIe Analog
Supply
PCIe Termination Supply
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
1.5V
Max
1.575V
Typ
3.3V
Max
3.465V
mA
290
385
250
308
124
143
115
141
3
3.3
Watts
0.29
0.42
0.25
0.34
0.12
0.16
0.17
0.22
0.01
0.01
Number of
Connected
Lanes
1/1/1/1/1
I/O Supply
Total
Typ
Power
Max
Power
0.85
1.15
Table 15 PES5T5 Power Consumption
Thermal Considerations
This section describes thermal considerations for the PES5T5 (15mm2 BCG196 package). The data in Table 16 below contains information that is
relevant to the thermal performance of the PES5T5 switch.
Symbol
Parameter
Value
Units
Conditions
TJ(max)
Junction Temperature
125
oC
Maximum
70
oC
Maximum for commercial-rated products
85
oC
Maximum for industrial-rated products
33.3
oC/W
Zero air flow
29
oC/W
1 m/S air flow
26.6
oC/W
2 m/S air flow
TA(max)
TA(max)
θJA(effective)
Ambient Temperature
Ambient Temperature
Effective Thermal Resistance, Junction-to-Ambient
θJB
Thermal Resistance, Junction-to-Board
18.7
oC/W
θJC
Thermal Resistance, Junction-to-Case
9.8
oC/W
P
Power Dissipation of the Device
1.15
Watts
Maximum
Table 16 Thermal Specifications for PES5T5, 15x15mm BCG196 Package
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May 7, 2009
IDT 89PES5T5 Data Sheet
DC Electrical Characteristics
Values based on systems running at recommended supply voltages, as shown in Table 13.
Note: See Table 8, Pin Characteristics, for a complete I/O listing.
I/O Type
Serial Link
Parameter
Min1
Description
Typ1
Max1
Unit
800
1200
mV
-3
-4
dB
3.7
V
Conditions
PCIe Transmit
VTX-DIFFp-p
VTX-DE-RATIO
Differential peak-to-peak output voltage
De-emphasized differential output voltage
VTX-DC-CM
DC Common mode voltage
VTX-CM-ACP
RMS AC peak common mode output voltage
20
mV
VTX-CM-DC-
Abs delta of DC common mode voltage
between L0 and idle
100
mV
Abs delta of DC common mode voltage
between D+ and D-
25
mV
Electrical idle diff peak output
20
mV
Voltage change during receiver detection
600
mV
active-idle-delta
VTX-CM-DC-linedelta
VTX-Idle-DiffP
VTX-RCV-Detect
-0.1
1
RLTX-DIFF
Transmitter Differential Return loss
10
dB
RLTX-CM
Transmitter Common Mode Return loss
6
dB
ZTX-DEFF-DC
DC Differential TX impedance
80
100
120
Ω
ZOSE
Single ended TX Impedance
40
50
60
Ω
Transmitter Eye
Diagram
TX Eye Height (De-emphasized bits)
505
650
mV
Transmitter Eye
Diagram
TX Eye Height (Transition bits)
800
950
mV
VRX-DIFFp-p
Differential input voltage (peak-to-peak)
175
VRX-CM-AC
Receiver common-mode voltage for AC
coupling
RLRX-DIFF
Receiver Differential Return Loss
10
dB
RLRX-CM
Receiver Common Mode Return Loss
6
dB
Differential input impedance (DC)
80
100
120
Ω
Single-ended input impedance
40
50
60
Ω
200k
350k
PCIe Receive
ZRX-DIFF-DC
ZRX-COMM-DC
ZRX-COMM-HIGH- Powered down input common mode
impedance (DC)
Z-DC
VRX-IDLE-DET-
Electrical idle detect threshold
65
Input Capacitance
1.5
1200
mV
150
mV
Ω
175
mV
DIFFp-p
PCIe REFCLK
CIN
—
pF
Table 17 DC Electrical Characteristics (Part 1 of 2)
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May 7, 2009
IDT 89PES5T5 Data Sheet
I/O Type
Min1
Typ1
Max1
Unit
Conditions
IOL
—
2.5
—
mA
VOL = 0.4v
IOH
—
-5.5
—
mA
VOH = 1.5V
IOL
—
12.0
—
mA
VOL = 0.4v
IOH
—
-20.0
—
mA
VOH = 1.5V
Parameter
Description
Other I/Os
LOW Drive
Output
High Drive
Output
Schmitt Trigger Input
(STI)
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
Input
VIL
-0.3
—
0.8
V
—
VIH
2.0
—
VDDIO +
0.5
V
—
CIN
—
—
8.5
pF
—
Inputs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK W/O
Pull-ups/downs
—
—
+ 10
μA
VDDI/O (max)
I/OLEAK WITH
Pull-ups/downs
—
—
+ 80
μA
VDDI/O (max)
Capacitance
Leakage
Table 17 DC Electrical Characteristics (Part 2 of 2)
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1.
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May 7, 2009
IDT 89PES5T5 Data Sheet
Package Pinout — 196-BGA Signal Pinout for PES5T5
The following table lists the pin numbers and signal names for the PES5T5 device.
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
Pin
Function
Alt
A1
VSS
C7
VDDAPE
E13
VDDCORE
H5
VSS
A2
NC
C8
VDDAPE
E14
VSS
H6
VDDCORE
A3
VSS
C9
VTTPE
F1
MSMBDAT
H7
VDDCORE
A4
NC
C10
CCLKDS
F2
SSMBADDR_2
H8
VSS
A5
NC
C11
VSS
F3
SSMBADDR_5
H9
VSS
A6
VSS
C12
VDDIO
F4
VDDIO
H10
VDDCORE
A7
NC
C13
VSS
F5
VSS
H11
VDDCORE
A8
NC
C14
SWMODE_0
F6
VDDCORE
H12
GPIO_05
A9
VSS
D1
SSMBCLK
F7
VDDCORE
H13
GPIO_03
1
A10
NC
D2
SSMBDAT
F8
VSS
H14
GPIO_02
1
A11
PE0TN00
D3
VSS
F9
VDDCORE
J1
JTAG_TDO
A12
VSS
D4
VDDIO
F10
VDDCORE
J2
JTAG_TRST_N
A13
PE0RP00
D5
VDDCORE
F11
VDDIO
J3
JTAG_TMS
A14
VSS
D6
VDDCORE
F12
GPIO_00
J4
VDDCORE
B1
VSS
D7
VDDPE
F13
PERSTN
J5
VSS
B2
NC
D8
VDDPE
F14
VSS
J6
VDDCORE
B3
VSS
D9
VDDCORE
G1
MSMBADDR_4
J7
VSS
B4
NC
D10
VDDIO
G2
MSMBCLK
J8
VDDCORE
B5
NC
D11
VDDCORE
G3
VDDIO
J9
VDDCORE
B6
VSS
D12
VSS
G4
VSS
J10
VSS
B7
NC
D13
SWMODE_2
G5
VDDCORE
J11
VDDIO
B8
NC
D14
SWMODE_1
G6
VSS
J12
VDDIO
B9
VSS
E1
SSMBADDR_1
G7
VSS
J13
GPIO_06
B10
NC
E2
SSMBADDR_3
G8
VDDCORE
J14
GPIO_04
B11
PE0TP00
E3
VDDIO
G9
VSS
K1
JTAG_TDI
B12
VSS
E4
VDDCORE
G10
VSS
K2
VDDIO
B13
PE0RN00
E5
VSS
G11
VSS
K3
VDDAPE
B14
VSS
E6
VSS
G12
VDDIO
K4
VSS
C1
WAKEN
E7
VSS
G13
GPIO_01
K5
VDDCORE
C2
APWRDISN
E8
VSS
G14
RSTHALT
K6
VSS
C3
CCLKUS
E9
VSS
H1
MSMBADDR_1
K7
VSS
C4
VSS
E10
VDDCORE
H2
MSMBADDR_2
K8
VSS
C5
VSS
E11
VSS
H3
MSMBADDR_3
K9
VSS
C6
VTTPE
E12
VDDIO
H4
VDDCORE
K10
VSS
1
1
1
Table 18 PES5T5 196-pin Signal Pin-Out (Part 1 of 2)
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May 7, 2009
IDT 89PES5T5 Data Sheet
Pin
Function
Alt
Pin
Function
K11
VDDCORE
L12
VSS
K12
VSS
L13
GPIO_10
K13
GPIO_08
L14
GPIO_09
K14
GPIO_07
M1
L1
JTAG_TCK
L2
Alt
Pin
Function
Alt
Pin
Function
M13
MSMBSMODE
N14
PE5RN00
1
M14
VSS
P1
PEREFCLKP
1
N1
PEREFCLKN
P2
VSS
VSS
N2
VSS
P3
PE2RP00
M2
VDDCORE
N3
PE2RN00
P4
VSS
VSS
M3
VDDCORE
N4
VSS
P5
PE2TN00
L3
VSS
M4
VSS
N5
PE2TP00
P6
PE3TP00
L4
VDDIO
M5
VDDIO
N6
PE3TN00
P7
VSS
L5
VDDCORE
M6
VTTPE
N7
VSS
P8
PE3RP00
L6
VDDCORE
M7
VDDAPE
N8
PE3RN00
P9
PE4RN00
L7
VDDPE
M8
VDDAPE
N9
PE4RP00
P10
VSS
L8
VDDPE
M9
VTTPE
N10
VSS
P11
PE4TP00
L9
VDDCORE
M10
VDDIO
N11
PE4TN00
P12
PE5TN00
L10
VDDCORE
M11
VDDIO
N12
PE5TP00
P13
VSS
L11
VSS
M12
REFCLKM
N13
VSS
P14
PE5RP00
1
Alt
Table 18 PES5T5 196-pin Signal Pin-Out (Part 2 of 2)
Alternate Signal Functions
Pin
GPIO
Alternate
F12
GPIO_00
P2RSTN
G13
GPIO_01
P4RSTN
H14
GPIO_02
IOEXPINTN0
H13
GPIO_03
IOEXPINTN1
J14
GPIO_04
IOEXPINTN2
K14
GPIO_07
GPEN
L14
GPIO_09
P3RSTN
L13
GPIO_10
P5RSTN
Table 19 PES5T5 Alternate Signal Functions
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May 7, 2009
IDT 89PES5T5 Data Sheet
Power Pins
VDDCore
VDDCore
VDDIO
VDDPE
VDDAPE
VTTPE
D5
H10
C12
D7
C7
C6
D6
H11
D4
D8
C8
C9
D9
J4
D10
L7
K3
M6
D11
J6
E3
L8
M7
M9
E4
J8
E12
E10
J9
F4
E13
K5
F11
F6
K11
G3
F7
L5
G12
F9
L6
J11
F10
L9
J12
G5
L10
K2
G8
M2
L4
H4
M3
M5
H6
M10
H7
M11
M8
Table 20 PES5T5 Power Pins
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May 7, 2009
IDT 89PES5T5 Data Sheet
Ground Pins
Vss
Vss
Vss
Vss
A1
D3
G10
L3
A3
D12
G11
L11
A6
E5
H5
L12
A9
E6
H8
M1
A12
E7
H9
M4
A14
E8
J5
M14
B1
E9
J7
N2
B3
E11
J10
N4
B6
E14
K4
N7
B9
F5
K6
N10
B12
F8
K7
N13
B14
F14
K8
P2
C4
G4
K9
P4
C5
G6
K10
P7
C11
G7
K12
P10
C13
G9
L2
P13
Table 21 PES5T5 Ground Pins
No Connection Pins
Pin
Pin
A2
B2
A4
B4
A5
B5
A7
B7
A8
B8
A10
B10
Table 22 PES5T5 No Connection Pins
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May 7, 2009
IDT 89PES5T5 Data Sheet
Signals Listed Alphabetically
Signal Name
I/O Type
Location
Signal Category
APWRDISN
I
C2
System
CCLKDS
I
C10
CCLKUS
I
C3
GPIO_00
I/O
F12
GPIO_01
I/O
G13
GPIO_02
I/O
H14
GPIO_03
I/O
H13
GPIO_04
I/O
J14
GPIO_05
I/O
H12
GPIO_06
I/O
J13
GPIO_07
I/O
K14
GPIO_08
I/O
K13
GPIO_09
I/O
L14
GPIO_10
I/O
L13
JTAG_TCK
I
L1
JTAG_TDI
I
K1
JTAG_TDO
O
J1
JTAG_TMS
I
J3
JTAG_TRST_N
I
J2
MSMBADDR_1
I
H1
MSMBADDR_2
I
H2
MSMBADDR_3
I
H3
MSMBADDR_4
I
G1
MSMBCLK
I/O
G2
MSMBDAT
I/O
F1
I
M13
MSMBSMODE
NC
General Purpose Input/Output
JTAG
SMBus
System
See Table 22 for a listing of No Connection pins.
PE0RN00
I
B13
PE0RP00
I
A13
PE0TN00
O
A11
PE0TP00
O
B11
PE2RN00
I
N3
PE2RP00
I
P3
PE2TN00
O
P5
PCI Express
Table 23 PES5T5 Alphabetical Signal List (Part 1 of 2)
22 of 28
May 7, 2009
IDT 89PES5T5 Data Sheet
Signal Name
I/O Type
Location
Signal Category
PE2TP00
O
N5
PCI Express (cont.)
PE3RN00
I
N8
PE3RP00
I
P8
PE3TN00
O
N6
PE3TP00
O
P6
PE4RN00
I
P9
PE4RP00
I
N9
PE4TN00
O
N11
PE4TP00
O
P11
PE5RN00
I
N14
PE5RP00
I
P14
PE5TN00
O
P12
PE5TP00
O
N12
PEREFCLKN
I
N1
PEREFCLKP
I
P1
PERSTN
I
F13
System
REFCLKM
I
M12
PCI Express
RSTHALT
I
G14
System
SSMBADDR_1
I
E1
SMBus
SSMBADDR_2
I
F2
SSMBADDR_3
I
E2
SSMBADDR_5
I
F3
SSMBCLK
I/O
D1
SSMBDAT
I/O
D2
SWMODE_0
I
C14
SWMODE_1
I
D14
SWMODE_2
I
D13
I/O
C1
WAKEN
SMBus
System
VDDCORE,
VDDAPE, VDDIO,
VDDPE, VTTPE
See Table 20 for a listing of power pins.
VSS
See Table 21 for a listing of ground pins.
Table 23 PES5T5 Alphabetical Signal List (Part 2 of 2)
23 of 28
May 7, 2009
IDT 89PES5T5 Data Sheet
PES5T5 Pinout — Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
A
B
B
C
C
X
X
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
X
X
N
N
P
P
1
2
3
4
VDDCore (Power)
VDDI/O (Power)
5
x
6
7
8
VTTPE (Power)
VDDPE (Power)
9
10
11
12
Vss (Ground)
13
14
Signals
No Connect
VDDAPE (Power)
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May 7, 2009
IDT 89PES5T5 Data Sheet
PES5T5 Package Drawing — 196-Pin BC196/BCG196
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May 7, 2009
IDT 89PES5T5 Data Sheet
PES5T5 Package Drawing — Page Two
26 of 28
May 7, 2009
IDT 89PES5T5 Data Sheet
Revision History
March 31, 2008: Publication of final data sheet.
August 6, 2008: Added industrial temperature information to Tables 14 and 16 and to Ordering Information section.
May 7, 2009: Revised labels in Table 15, Power Consumption, for greater clarification.
27 of 28
May 7, 2009
IDT 89PES5T5 Data Sheet
Ordering Information
NN
A
AAA
NNAN
Product
Family
Operating
Voltage
Device
Family
Product
Detail
AA
AA
Device
Revision
A
Package Temp Range
Blank
I
Legend
A = Alpha Character
N = Numeric Character
Commercial Temperature
(0°C to +70°C Ambient)
Industrial Temperature
(-40° C to +85° C Ambient)
BC
BC196 196-ball CABGA
BCG
BCG196 196-ball CABGA, Green
ZB
ZB revision
5T5
5-lane, 5-port
PES
PCI Express Switch
H
1.0V +/- 0.1V Core Voltage
89
Serial Switching Product
Valid Combinations
89HPES5T5ZBBC
196-pin BC196 package, Commercial Temperature
89HPES5T5ZBBCG
196-pin Green BCG196 package, Commercial Temperature
89HPES5T5ZBBCI
196-pin BC196 package, Industrial Temperature
89HPES5T5ZBBCGI
196-pin Green BCG196 package, Industrial Temperature
®
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for SALES:
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www.idt.com
28 of 28
for Tech Support:
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phone: 408-284-8208
May 7, 2009
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