8EN31AKLFT

ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8EN31AK is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout HiPerClockS™ Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8EN31AK has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • Nine differential 3.3V LVPECL outputs ICS Guaranteed output skew and part-to-part skew characteristics make the ICS8EN31AK ideal for high performance workstation and server applications. • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency: 500MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input • Output skew: 40ps (maximum) • Part-to-part skew: 350ps (maximum) • Propagation delay: 1.9ns (maximum) • 3.3V operating supply • 0°C to 70°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages • Industrial temperature information available upon request BLOCK DIAGRAM VCCO nQ2 Q2 CLK_SEL Pulldown nQ1 PCLK Pullup nPCLK Pulldown Q1 Q CLK Pullup nCLK Pulldown nQ0 D Q0 VCCO CLK_EN Pullup PIN ASSIGNMENT 32 31 30 29 28 27 26 25 LE 0 Q0 nQ0 1 Q1 nQ1 Q2 nQ2 Q3 nQ3 VCC 1 24 VCCO CLK 2 23 Q3 nCLK 3 22 nQ3 CLK_SEL 4 21 Q4 PCLK 5 20 nQ4 nPCLK 6 19 Q5 VEE 7 18 nQ5 CLK_EN 8 17 VCCO ICS8EN31AK 9 10 11 12 13 14 15 16 Vcco Q6 nQ6 Q7 nQ7 Q8 Q5 nQ5 nQ8 Vcco Q4 nQ4 32-Lead VFQFN 5mm x 5mm x 0.95 package body K Package Top View Q6 nQ6 Q7 nQ7 Q8 nQ8 8EN31AK www.icst.com/products/hiperclocks.html 1 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 VCC Power Type 2 CLK Input 3 nCLK Input 4 CLK_SEL Input 5 PCLK Input Description Power supply pin. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Clock Select input. When HIGH, selects PCLK, nPCLK inputs. Pulldown When LOW, selects CLK, nCLK. LVTTL / LVCMOS interface levels. Pulldown Non-inver ting differential LVPECL clock input. 6 nPCLK Input 7 VEE Power Pullup 8 CLK_EN Input VCCO Power Output supply pins. Pullup Inver ting differential LVPECL clock input. Negative supply pin. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVTTL / LVCMOS interface levels. 9, 16, 17, 24, 25, 32 10, 11 nQ8, Q8 Output Differential output pair. LVPECL interface level. 12, 13 nQ7, Q7 Output Differential output pair. LVPECL interface level. 14, 15 nQ6, Q6 Output Differential output pair. LVPECL interface level. 18, 19 nQ5, Q5 Output Differential output pair. LVPECL interface level. 20, 21 nQ4, Q4 Output Differential output pair. LVPECL interface level. 22, 23 nQ3 Q3 Output Differential output pair. LVPECL interface level. 26, 27 nQ2, Q2 Output Differential output pair. LVPECL interface level. 28, 2 9 nQ1, Q1 Output Differential output pair. LVPECL interface level. 30, 31 nQ0, Q0 Output Differential output pair. LVPECL interface level. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8EN31AK www.icst.com/products/hiperclocks.html 2 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL Outputs Selected Source Q0:Q8 nQ0:nQ8 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ8 Q0:Q8 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK or PCLK Outputs nCLK or nPCLK Q0:Q8 nQ0:nQ8 Input to Output Mode Polarity 0 1 LOW HIGH Differential to Differential Non Inver ting 1 0 HIGH LOW Differential to Differential Non Inver ting 0 Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting 1 Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8EN31AK www.icst.com/products/hiperclocks.html 3 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 34.8°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCO Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 80 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VIH CLK_EN, CLK_SEL Test Conditions Minimum 2 Typical VCC + 0.3 V VIL CLK_EN, CLK_SEL -0.3 0. 8 V IIH Input High Current IIL Input Low Current CLK_EN VCC = VIN = 3.465V 5 µA CLK_SEL VCC = VIN = 3.465V 150 µA CLK_EN VIN = 0V, VCC = 3.465V -150 µA CLK_SEL VIN = 0V, VCC = 3.465V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK Minimum Typical VCC = VIN = 3.465V Units 150 µA nCLK VCC = VIN = 3.465V CLK VIN = 0V, VCC = 3.465V -5 µA nCLK VIN = 0V, VCC = 3.465V -150 µA 5 Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR VEE + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is VCC + 0.3V. NOTE 2: Common mode input voltage is defined as VIH. VPP 8EN31AK Maximum www.icst.com/products/hiperclocks.html 4 µA 1. 3 V VCC - 0.85 V REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units PCLK VCC = VIN = 3.465V Test Conditions 150 µA nPCLK VCC = VIN = 3.465V 5 µA IIH Input High Current IIL Input Low Current VPP VOH Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Output High Voltage; NOTE 3 VOL Output Low Voltage; NOTE 3 VCMR Minimum Typical PCLK VIN = 0V, VCC = 3.465V -5 µA nPCLK VIN = 0V, VCC = 3.465V -150 µA 0.3 1 V VEE + 1.5 VCC V VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 1.0 V Maximum Units 500 MHz 1.9 ns VSWING Peak-to-Peak Output Voltage Swing 0.6 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VCC + 0.3V. NOTE 3: Outputs terminated with 50Ω to VCCO - 2V. TABLE 5. AC CHARACTERISTICS, VCC = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum Typical 0.9 t sk(o) Output Skew; NOTE 2, 4 40 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 350 ps t R / tF Output Rise/Fall Time 600 ps 55 % 20% to 80% 250 o dc Output Duty Cycle 45 50 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8EN31AK www.icst.com/products/hiperclocks.html 5 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V V CC , VCCO Qx V CC SCOPE nCLK, nPCLK LVPECL V V Cross Points PP nQx CMR CLK, PCLK VEE -1.3V ± 0.165V VEE 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL PART 1 nQx nQx Qx Qx PART 2 nQy nQy Qy Qy tsk(o) tsk(o) OUTPUT SKEW PART-TO-PART SKEW nQ0:nQ8 80% 80% Q0:Q8 VSW I N G Clock Outputs t PW 20% 20% tR t PERIOD tF odc = t PW x 100% t PERIOD OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD nCLK, nPCLK CLK, PCLK nQ0:nQ8 Q0:Q8 tPD PROPAGATION DELAY 8EN31AK www.icst.com/products/hiperclocks.html 6 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VCC R1 1K CLK_IN + V_REF - C1 0.1uF R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 8EN31AK www.icst.com/products/hiperclocks.html 7 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 8EN31AK www.icst.com/products/hiperclocks.html 8 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE faces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input inter- 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK PCLK R1 100 Zo = 50 Ohm nPCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R3 1K R4 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 8EN31AK HiPerClockS PCLK/nPCLK R2 125 FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 9 HiPerClockS PCL K/n PC LK R2 1K REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TERMINATION FOR LVPECL OUTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. ance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched imped- 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 5A. LVPECL OUTPUT TERMINATION 8EN31AK FIN 50Ω 84Ω FIGURE 5B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 10 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8EN31AK. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8EN31AK is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 9 * 30mW = 270mW Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 270mW = 547.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming 0 air flow and a multi-layer board, the appropriate value is 34.8°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.547W * 34.8°C/W = 89°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 32-PIN LQFP FORCED CONVECTION θJA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 8EN31AK 34.8°C/W www.icst.com/products/hiperclocks.html 11 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8EN31AK www.icst.com/products/hiperclocks.html 12 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN θJA 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 34.8°C/W TRANSISTOR COUNT The transistor count for ICS8EN31AK is: 632 8EN31AK www.icst.com/products/hiperclocks.html 13 REV. A APRIL 27, 2006 ICS8EN31AK Integrated Circuit Systems, Inc. PACKAGE OUTLINE AND LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS VHHD-2 SYMBOL MINIMUM NOMINAL A 0.80 A1 0 -- 1.00 -- 0.05 0.25 Ref. A3 b MAXIMUM 32 N 0.18 0.25 0.30 ND 8 NE 8 5.00 BASIC D D2 1.25 2.25 5.00 BASIC E E2 1.25 2.25 3.25 0.50 BASIC e L 3.25 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 8EN31AK www.icst.com/products/hiperclocks.html 14 REV. A APRIL 27, 2006 Integrated Circuit Systems, Inc. ICS8EN31AK LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8EN31AK ICS8EN31AK 32 Lead VFQFN tray 0°C to 70°C ICS8EN31AKT ICS8EN31AK 32 Lead VFQFN 2500 tape & reel 0°C to 70°C ICS8EN31AKLF ICS8EN31AKL 32 Lead "Lead-Free" VFQFN tray 0°C to 70°C ICS8EN31AKLFT ICS8EN31AKL 32 Lead "Lead-Free" VFQFN 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8EN31AK www.icst.com/products/hiperclocks.html 15 REV. A APRIL 27, 2006