Universal Frequency Synthesizer
IDT8N3PF10VA-159I
DATA SHEET
General Description
Features
The IDT8N3PF10VA-159I is a programmable LVPECL synthesizer
that is “forward” footprint compatible with standard 5mm x 7mm
oscillators. The device uses IDT’s fourth generation FemtoClock®
NG technology for an optimum of high clock frequency and low
phase noise performance. Forward footprint compatibility means that
a board designed to accommodate the crystal oscillator interface
and the optional control pins is also fully compatible with a canned
oscillator footprint - the canned oscillator will drop onto the
10-VFQFN footprint for second sourcing purposes. This capability
provides designers with programability and lead time advantages of
silicon/crystal based solutions while maintaining compatibility with
industry standard 5mm x 7mm oscillator footprints for ease of supply
chain management.
•
•
•
Fourth Generation FemtoClock® NG technology
•
•
One differential LVPECL output pair
•
•
•
•
RMS phase jitter @ 156.25MHz, 10kHz – 1MHz: 0.201ps (typical)
Footprint compatible with 5mm x 7mm differential oscillators
Generates 100MHz or 156.25MHz from a 25MHz crystal, or
212.5MHz or 106.25MHz from a 26.5625MHz mode crystal
Crystal oscillator interface which can also be overdriven using a
single-ended reference clock
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
The IDT8N3PF10VA-159I generates four default frequencies
100MHz or 156.25MHz from a 25MHz fundamental mode crystal, or
212.5MHz or 106.25MHz from a 26.5625MHz fundamental mode
crystal. The output frequency is selected by FSEL0 and FSEL1 pins.
Pin Assignment
Block Diagram
Pullup
XTAL_IN
PFD
&
LPF
OSC
XTAL_OUT
FemtoClock® NG
VCO
2 - 2.5GHz
FSEL0
FSEL1
OE
Q
nQ
÷N
÷M
FSEL0
FSEL1
Pullup
Pullup
Control
Logic
IDT8N3PF10VA-159I
10-Lead VFQFN
5mm x 7mm x 1mm package body
ePAD size: 1.70mm x 3.70mm
NR Package
Top View
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Table 1. Pin Descriptions
Number
Name
1
OE
Input
Type
Description
2
RESERVED
Reserved
3
VEE
Power
Negative supply pin.
4,
5
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. Crystal
oscillator interface which can also be overdriven using a single-ended reference
clock.
6, 7
Q, nQ
Output
Differential output pair. LVPECL interface levels.
8
VCC
Power
Power supply pin.
9
FSEL0
Input
Pullup
Output divider control inputs. Sets the output divider value to one of four values. See
Table 3. LVCMOS/LVTTL interface levels.
10
FSEL1
Input
Pullup
Output divider control inputs. Sets the output divider value to one of four values. See
Table 3. LVCMOS/LVTTL interface levels
Pullup
Output enable. LVCMOS/LVTTL interface levels.
Reserved pin. Do not connect.
NOTE: Pullup refers to internal input resistor. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
Function Table
Table 3. Divider Function Table
FSEL[1:0]
Output (MHz)
Input Crystal (MHz)
00
100
25
01
156.25
25
10
212.5
26.5625
1 1 (default)
106.25
26.5625
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
36.8°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Power Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
118
140
mA
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
115
135
mA
Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC
Power Supply Voltage
IEE
Power Supply Current
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
OE,
FSEL[1:0]
VCC = VIN = 3.465V or 2.625V
IIL
Input
Low Current
OE,
FSEL[1:0]
VCC = 3.465V or 2.625V, VIN = 0V
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
Test Conditions
Minimum
VCC = 3.465V
Maximum
Units
2
VCC + 0.3
V
VCC = 2.625V
1.7
VCC + 0.3
V
VCC = 3.465V
-0.3
0.8
V
VCC = 2.625V
-0.3
0.7
V
5
µA
3
-150
Typical
µA
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Table 4D. LVPECL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
Minimum
Typical
Maximum
Units
VCC – 1.3
VCC – 0.8
V
VCC – 2.0
VCC – 1.6
V
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCC – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Maximum
Units
Fundamental
25
MHz
26.5625
MHz
Frequency
Equivalent Series Resistance (ESR)
50
Ω
Shunt Capacitance
7
pF
Maximum
Units
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
tjit(Ø)
Parameter
RMS Phase Jitter (Random);
NOTE 1
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 2
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
212.5MHz,
Integration Range: 10kHz – 1MHz
0.197
ps
156.25MHz,
Integration Range: 10kHz – 1MHz
0.201
ps
156.25MHz,
Integration Range: 12kHz – 20MHz
0.300
ps
106.25MHz,
Integration Range: 12kHz – 20MHz
0.285
ps
100MHz,
Integration Range: 12kHz – 20MHz
0.276
ps
20% to 80%
20
ps
100
400
ps
48
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using a 25MHz, 12pF resonant crystal.
NOTE 1: Please refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Parameter Measurement Information
2V
2V
Q
VCC
SCOPE
VCC
LVPECL
Q
SCOPE
LVPECL
nQ
nQ
VEE
VEE
-1.3V±0.165V
-0.5V±0.125V
3.3V LVPECL Output Load Test Circuit
2.5V LVPECL Output Load Test Circuit
Noise Power
Phase Noise Plot
nQ
Q
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Offset Frequency
f1
f2
RMS Phase Jitter =
1
* Area Under Curve Defined by the Offset Frequency Markers
2* *ƒ
RMS Phase Jitter
Cycle-to-Cycle Jitter
nQ
nQ
Q
80%
80%
t PW
VSW I N G
PERIOD
20%
20%
Q
t
tR
tF
odc =
t PW
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Noise PowerdBc / Hz
Phase Jitter Plot at 156.25MHz (3.3V)
Offset Frequency (Hz)
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Applications Information
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
VCC
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50Ω applications,
R1 and R2 can be 100Ω. This can also be accomplished by removing
R1 and changing R2 to 50Ω. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
XTAL_OUT
R1
100
Ro
Rs
C1
Zo = 50 ohms
XTAL_IN
R2
100
Zo = Ro + Rs
.1uf
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
LVPECL Driver
R1
50
R2
50
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
R3
125Ω
3.3V
3.3V
Zo = 50Ω
3.3V
R4
125Ω
3.3V
3.3V
+
Zo = 50Ω
+
_
LVPECL
Input
Zo = 50Ω
R1
50Ω
_
LVPECL
R2
50Ω
R1
84Ω
VCC - 2V
RTT =
1
* Zo
((VOH + VOL) / (VCC – 2)) – 2
Input
Zo = 50Ω
R2
84Ω
RTT
Figure 2A. 3.3V LVPECL Output Termination
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
Figure 2B. 3.3V LVPECL Output Termination
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 3B can be eliminated and the termination is
shown in Figure 3C.
Figure 3A and Figure 3B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50Ω
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
R3
250Ω
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 3A. 2.5V LVPECL Driver Termination Example
Figure 3B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 3C. 2.5V LVPECL Driver Termination Example
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 4. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Schematic Layout
Figure 5 (next page) shows an example of IDT8N3PF10VA-159I
application schematic in which the device is operated at VCC = 3.3V.
The schematic example focuses on functional connections and is
intended as an example only and may not represent the exact user
configuration. Refer to the pin description and functional tables in the
datasheet to ensure the logic control inputs are properly set. For
example OE, FSET0 and FSEL1 can be configured from an FPGA
instead of pull up and pull down resistors as shown.
GND on the PCB through vias in order to improve heat dissipation. If
not connected, the area below the ePAD must be treated as a
keep-out region.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter performance
isolation of the VCC pin from power supply is required. In order to
achieve the best possible filtering, it is recommended that the
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1uF
capacitor on the VCC pin must be placed on the device side with
direct return to the ground plane though vias. The remaining filter
components can be on the opposite side of the PCB.
There are two LVPECL termination options shown; the simple three
resistor termination of R5, R6 and R7 and an AC termination, used
when coupling the IDT8N3PF10VA-159I LVPECL output stage to a
different logic family receiver. Note that the pull down resistors R8
and R9 that bias the LVPECL output stage are to be placed on the
IDT8N3PF10VA-159I side of the PCB directly adjacent to pins 6 and
7 for best signal integrity. Most often each output of a 3.3V LVPECL
driver will be DC terminated with a 130Ω pull up and an 82 ohm pull
down resistor at the 3.3V LVPECL receiver. This is also a valid option
with the IDT8N3PF10VA-159I, though the three resistor termination
is simpler in regard to component count and layout as well as lower
in power dissipation.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at
approximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally, good general design
practices for power plane voltage stability suggests adding bulk
capacitance in the local area of all devices.
NOTE: This device package has an ePAD that is connected to ground
internally. Though not necessary, the ePAD should be connected to
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
.
Logic Control Input Examples
VCC
Set Logic
Input to '1'
VC C
Set Logic
Input to '0'
3.3V
RU1
1K
RU2
N ot I nstall
To Logic
Input
pins
VC C
2
To Logic
Input
pins
RD1
N ot Ins tall
F B1
C4
10uF
1
BLM18BB221SN 1
C5
0. 1uF
RD2
1K
Place 0.1uF bypass cap directly adjacent to the
VCC pin and on the component side.
VC C
2
5
25MH z (12pf )
4
8
OE
Q
Q
Zo = 50 Ohm
+
R ESERVED
XTAL_I N
nQ
7
Zo = 50 Ohm
nQ
+3.3 V PEC L R eceiv er
XTAL_OU T
VEE
X1
C2
4pF
3
C1
4pF
6
R5
50
R6
50
C7
Q
R7
50
ePAD
1
OE
F SEL0
F SEL1
11
9
10
F SEL0
F SEL1
C3
0.1u F
VC C
U1
Z o = 50 O hm
VC C _R x
0. 1u
R8
180
R3
C6
0.0 1uF
R1
50
-
R4
R2
50
C8
nQ
+
R eceiv er
Z o = 50 O hm
0. 1u
R9
180
Alternate AC coupled LVPECL Termination
Select R3 and R4 to center the LVPECL swing in the common
mode center of the Receiver.
Place R8 and R9 pull down resistors on the U1 side of the board at
pins 6 and 7 respectively.
Figure 5. IDT8N3PF10VA-159I Application Schematic
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N3PF10VA-159I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8N3PF10VA-159I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW
•
Power (outputs)MAX = 32mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 32mW = 517.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 36.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.517W * 36.8°C/W = 104°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 10 Lead VFQFN, Forced Convection
θJA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
0
1
2.5
36.8°C/W
31.7°C/W
30.1°C/W
13
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
The LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to loading, use the following equations which assume a 50Ω load, and a termination voltage
of VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50Ω] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50Ω] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
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©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Reliability Information
Table 8. θJA vs. Air Flow Table for a 10 Lead VFQFN
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
36.8°C/W
31.7°C/W
30.1°C/W
Transistor Count
The transistor count for IDT8N3PF10VA-159I is: 47,515
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
15
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
10 Lead VFQFN, NR Suffix Package Outline
D
A
B
aaa C 2x
E
4
INDEX AREA
(D/2 xE/2)
aaa C 2x
9
TOP VIEW
C
A
A1
ccc C
8
SEATING
PLANE
SIDE VIEW
0.08 C
e1
NX L2
7
NX b1
bbb
C A B
NX b2
7
C A B
e2
E2
bbb
4
INDEX AREA
(D/2 xE/2)
D2
BOTTOM VIEW
NX L1
PIN#1 ID
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
DRAFT
1
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
MLP QUAD
PACKAGE OUTLINE
ENGINEERING MANAGER
TOOLING MANAGER
ARAVEN
TECH. SALES MANAGER
KANDA
DATE
2007-APR-18
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
5.00x7.00 MLPQ 10LD
1.00/2.54 Pitch
Page 1 Of 4
16
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
10 Lead VFQFN, NR Suffix Package Outline, continued
COMMON DIMENSION
TOLERANCE OF FORM AND POSITION
0.15
0.10
0.10
aaa
bbb
ccc
SYMBOL
MIN
0.80
0.00
1, 2
A
A1
NOTES
COMMON DIMENSION
V : Very thin
NOM
0.90
0.02
1, 2
Summary Table
Body
Size
5.00X7.00
Lead
Count
10
Lead
Pitch (e1 & e2)
1.00/2.54
MAX
1.00
0.05
1, 2
Very Very Thin
Variation
Pin #1 ID
VNJR-1
R0.30
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
DRAFT
1
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
MLP QUAD
PACKAGE OUTLINE
ENGINEERING MANAGER
TOOLING MANAGER
ARAVEN
TECH. SALES MANAGER
KANDA
DATE
2007-APR-18
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
5.00x7.00 MLPQ 10LD
1.00/2.54 Pitch
PAGE: 2 of 4
17
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
10 Lead VFQFN, NR Suffix Package Outline, continued
NOTE:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters, angles are in degrees(°).
3. N is the total number of terminals.
4. The location of the terminal #1 identifier and terminal numbering convention
conforms to JEDEC publication 95 SPP-002.
5. ND and NE refer to the number of terminals on each D and E side respectively.
6. NJR refers to NON JEDEC REGISTERED
7. Dimension b applies to metallized terminal and is measured between 0.10mm
and 0.30mm from the terminal tip. If the terminal has the optional radius
on the other end of the terminal, the dimension b should not be measured
in that radius area.
8. Coplanarity applies to the terminals and all other bottom surface metallization.
9. Drawing shown are for illustration only.
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
DRAFT
1
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
MLP QUAD
PACKAGE OUTLINE
ENGINEERING MANAGER
TOOLING MANAGER
ARAVEN
TECH. SALES MANAGER
KANDA
DATE
2007-APR-18
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
5.00x7.00 MLPQ 10LD
1.00/2.54 Pitch
PAGE: 3 of 4
18
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
10 Lead VFQFN, NR Suffix Package Outline, continued
Var
ia
Sym tion
VNJR-1
bol
D BSC
5.00
7.00
E BSC
MIN
0.35
b1 NOM
0.40
MAX
0.45
MIN
1.35
b2 NOM
1.40
MAX
1.45
MIN
1.55
D2 NOM
1.70
1.80
MAX
3.55
MIN
3.70
E2 NOM
3.80
MAX
0.45
MIN
0.55
L1 NOM
0.65
MAX
MIN
1.00
L2 NOM
1.10
MAX
1.20
N
10
ND
2
NE
3
NOTES
PAD DESIGN
Not
e
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
DRAFT
1
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
MLP QUAD
PACKAGE OUTLINE
ENGINEERING MANAGER
TOOLING MANAGER
ARAVEN
TECH. SALES MANAGER
KANDA
DATE
2007-APR-18
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
5.00x7.00 MLPQ 10LD
1.00/2.54 Pitch
PAGE: 4 of 4
19
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
Ordering Information
Table 9. Ordering Information
Part/Order Number
8N3PF10VA-159NRGI
8N3PF10VA-159NRGI
Marking
IDT8N3PF10VA-159NRGI
IDT8N3PF10VA-159NRGI
IDT8N3PF10VA-159NRGI REVISION A OCTOBER 3, 2012
Package
“Lead-Free” 10 Lead VFQFN
“Lead-Free” 10 Lead VFQFN
20
Shipping Packaging
Tray
Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
©2012 Integrated Device Technology, Inc.
IDT8N3PF10VA-159I Data Sheet
Universal Frequency Synthesizer
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