8N3Q001LG-0009CDI

Quad-Frequency Programmable XO IDT8N3Q001 REV G DATA SHEET General Description Features The IDT8N3Q001 is a Quad-Frequency Programmable Clock Oscillator with very flexible frequency programming capabilities. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 10-lead Ceramic 5mm x 7mm x 1.55mm package. • • Fourth generation FemtoClock® NG technology • Four power-up default frequencies (see part number order codes), re-programmable by I2C • I2C programming interface for the output clock frequency and internal PLL control registers Besides the four default power-up frequencies set by the FSEL0 and FSEL1 pins, the IDT8N3Q001 can be programmed via the I2C interface to output clock frequencies between 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to a very high degree of precision with a frequency step size of 435.9Hz ÷ N (N is the PLL output divider). Since the FSEL0 and FSEL1 pins are mapped to 4 independent PLL M and N divider registers (P, MINT, MFRAC and N), reprogramming those registers to other frequencies under control of FSEL0 and FSEL1 is supported. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. • • • • • Frequency programming resolution is 435.9Hz ÷N • RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.265ps (typical), integer PLL feedback configuration • • • Full 2.5V or 3.3V supply modes Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz One 2.5V, 3.3V LVPECL clock output Two control inputs for the power-up default frequency LVCMOS/LVTTL compatible control inputs RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.244ps (typical), integer PLL feedback configuration -40°C to 85°C ambient operating temperature Available in Lead-free (RoHS 6) package Block Diagram Q nQ ÷N DNU 1 fXTAL ÷MINT, MFRAC 2 7 25 FSEL1 FSEL0 SCLK SDATA OE Pulldown Pulldown Configuration Register (ROM) (Frequency, APR, Polarity) Pullup Pullup 9 SDATA FemtoClock® NG VCO 1950-2600MHz I2C Control 8 VCC OE 2 7 nQ VEE 3 6 Q FSEL1 5 PFD & LPF 10 SCLK ÷P FSEL0 4 OSC Pin Assignment IDT8N3Q001 10-lead Ceramic 5mm x 7mm x 1.55mm package body CD Package Top View Pullup IDT8N3Q001GCD REVISION A MARCH 6, 2012 1 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Table 1. Pin Descriptions Number Name Type 1 DNU Unused 2 OE Input 3 VEE Power Description Do not use. Pullup Output enable pin. See Table 3 for function. LVCMOS/LVTTL interface levels. Pulldown Default frequency select pins. See the Default Frequency Order Codes section. LVCMOS/LVTTL interface levels. Negative power supply. 5, 4 FSEL1, FSEL0 Input 6, 7 Q, nQ Output Differential clock output. LVPECL interface levels. 8 VCC Power Power supply pin. 9 SDATA Input/Output Pullup I2C Data Input/Output. Input: LVCMOS/LVTTL compatible interface levels. Output: Open drain. 10 SCLK Input Pullup I2C Clock Input. LVCMOS/LVTTL compatible interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 5.5 pF RPULLUP Input Pullup Resistor 50 k RPULLDOWN Input Pulldown Resistor 50 k Function Tables Table 3A. OE Configuration Input OE 0 1 (default) Output Enable Outputs Q, nQ are in high-impedance state. Outputs are enabled. NOTE: OE is an asynchronous control. Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MMHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. IDT8N3Q001GCD REVISION A MARCH 6, 2012 2 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Block Diagram with Programming Registers ÷P OSC Output Divider N PFD & LPF FemtoClock® NG VCO 1950-2600MHz ÷N Q nQ fXTAL 2 Feedback Divider M (25 Bit) MINT  (7 bits) 7 MFRAC  (18 bits)   18 7 27 Programming Registers I2C Control 30 P0 MINT0 MFRAC0 N0 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P1 MINT1 MFRAC1 N1 I C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P2 MINT2 MFRAC2 N2 I C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits P3 MINT3 MFRAC3 N3 I2C: 2 bits 7 bits 18 bits 7 bits Def: 2 bits 7 bits 18 bits 7 bits 2 30 SCLK SDATA Pullup 2 Pullup 30 30 FSEL[1:0] OE 34 00 34 01 34 34 10 34 11 34 Pulldown Pullup 2 Def (default): Power-up default register setting for I2C registers Pn, MINTn, MFRACn and Nn IDT8N3Q001GCD REVISION A MARCH 6, 2012 3 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Principles of Operation The block diagram consists of the internal 3rd overtone crystal and oscillator which provide the reference clock fXTAL of either 114.285 MHz or 100MHz. The PLL includes the FemtoClock NG VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference and must be configured correctly for proper operation. The feedback divider is fractional supporting a huge number of output frequencies. The configuration of the feedback divider to integer-only values results in an improved output phase noise characteristics at the expense of the range of output frequencies. In addition, internal registers are used to hold up to four different factory pre-set P, M, and N configuration settings. These default pre-sets are stored in the I2C registers at power-up. Each configuration is selected via the the FSEL[1:0] pins and can be read back using the SCLK and SDATA pins. As identified previously, the configurations of P, M (MINT & MFRAC) and N divider settings are stored the I2C register, and the configuration loaded at power-up is determined by the FSEL[1:0] pins. Table 4. Frequency Selection Input The user may choose to operate the device at an output frequency different than that set by the factory. After power-up, the user may write new P, N and M settings into one or more of the four configuration registers and then use the FSEL[1:0] pins to select the newly programmed configuration. Note that the I2C registers are volatile and a power supply cycle will reload the pre-set factory default conditions. FSEL1 FSEL0 Selects Register 0 (def.) 0 (def.) Frequency 0 P0, MINT0, MFRAC0, N0 0 1 Frequency 1 P1, MINT1, MFRAC1, N1 1 0 Frequency 2 P2, MINT2, MFRAC2, N2 1 1 Frequency 3 P3, MINT3, MFRAC3, N3 Frequency Configuration An order code is assigned to each frequency configuration programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information Section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. If the user does choose to write a different P, M, and N configuration, it is recommended to write to a configuration which is not currently selected by FSEL[1:0] and then change to that configuration after the I2C transaction has completed. Changing the FSEL[1:0] controls results in an immediate change of the output frequency to the selected register values. The P, M, and N frequency configurations support an output frequency range 15.476MHz to 866.67MHz and 975MHz to 1,300MHz. For more information and guidelines on programming of the device for custom frequency configurations, the register description, the selection of fractional and integer-feedback configurations and the serial interface description, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determined by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: 1 MFRAC + 0.5 f OUT = f XTAL  ------------  MINT + ----------------------------------- (1) 18 PN 2 The four configuration registers for the P, M (MINT & MFRAC) and N dividers which are named Pn, MINTn, MFRACn and Nn with n=0 to 3. “n” denominates one of the four possible configurations. IDT8N3Q001GCD REVISION A MARCH 6, 2012 4 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (SDATA) Outputs, IO (LVPECL) Continuous Current Surge Current 10mA  50mA 100mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C  DC Electrical Characteristics Table 5A. Power Supply DC Characteristics,VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 140 mA Table 5B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 136 mA Table 5C. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL IIH IIL Input Low Voltage Input High Current Input Low Current Test Conditions Minimum FSEL[1:0], OE VCC =3.3V +5% FSEL[1:0], OE Typical Maximum Units 1.7 VCC +0.3 V VCC =2.5V +5% 1.7 VCC +0.3 V FSEL[1:0] VCC =3.3V +5% -0.3 0.5 V OE VCC =3.3V +5% -0.3 0.8 V FSEL[1:0] VCC =2.5V +5% -0.3 0.5 V OE VCC =2.5V +5% -0.3 0.8 V OE VCC = VIN = 3.465V or 2.625V 10 µA SDATA, SCLK VCC = VIN = 3.465V or 2.625V 5 µA FSEL0, FSEL1 VCC = VIN = 3.465V or 2.625V 150 µA OE VCC = 3.465V or 2.625V, VIN = 0V -500 µA SDATA, SCLK VCC = 3.465V or 2.625V, VIN = 0V -150 µA FSEL0, FSEL1 VCC = 3.465V or 2.625V, VIN = 0V -5 µA IDT8N3Q001GCD REVISION A MARCH 6, 2012 5 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Table 5D. LVPECL DC Characteristics, VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC – 1.4 VCC – 0.8 V VCC – 2.0 VCC – 1.5 V 0.55 1.0 V NOTE 1: Outputs terminated with 50 to VCC – 2V. AC Electrical Characteristics Table 6. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency Q, nQ fI Initial Accuracy fS Temperature Stability fA fT Aging Total Stability tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tjit(per) RMS Period Jitter; NOTE 1 RMS Phase Jitter (Random); Fractional PLL feedback and fXTAL=100.000MHz (2xxx order  codes) tjit(Ø) RMS Phase Jitter (Random); Integer PLL feedback and fXTAL=100.00MHz (1xxx order codes) RMS Phase Jitter (Random) Fractional PLL feedback and fXTAL=114.285MHz (0xxx order codes) Test Conditions Minimum Maximum Units Output Divider, N = 3 to126 15.476 Typical 866.67 MHz Output Divider, N = 2 975 1,300 MHz Measured at 25°C ±10 ppm Option code = A or B ±100 ppm Option code = E or F ±50 ppm Option code = K or L ±20 ppm Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm Option code A or B (10 year life) ±113 ppm Option code E or F (10 year life) ±63 ppm Option code K or L (10 year life) ±33 ppm 20 ps 2.85 4 ps 17 MHz fOUT 1300MHz, NOTE 2,3,4 0.440 0.995 ps 500 MHz fOUT 1300MHz, NOTE 2,3,4 0.240 0.390 ps 125 MHz fOUT 500MHz, NOTE 2,3,4 0.245 0.425 ps 17 MHz fOUT 125MHz, NOTE 2,3,4 0.350 0.555 ps fOUT 156.25MHz, NOTE 2, 3, 4 0.244 ps fOUT 156.25MHz, NOTE 2, 3, 5 0.265 ps 17 MHz fOUT 1300 MHz, NOTE 2, 3, 4 0.475 0.990 ps N(100) Single-side band phase noise,  100Hz from Carrier 156.25MHz -94.7 dBc/Hz N(1k) Single-side band phase noise,  1kHz from Carrier 156.25MHz -121.3 dBc/Hz N(10k) Single-side band phase noise,  10kHz from Carrier 156.25MHz -131.1 dBc/Hz IDT8N3Q001GCD REVISION A MARCH 6, 2012 6 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Symbol Parameter N(100k) Single-side band phase noise,  100kHz from Carrier 156.25MHz -137.3 dBc/Hz N(1M) Single-side band phase noise,  1MHz from Carrier 156.25MHz -139.0 dBc/Hz N(10M) Single-side band phase noise,  10MHz from Carrier 156.25MHz -154.9 dBc/Hz PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise 1kHz - 50kHz -54 dB tR / tF Output Rise/Fall Time odc Output Duty Cycle tSTARTUP Oscillator Start-Up Time tSET Output frequency settling time after FSEL0 and FSEL1 values are changed Test Conditions 20% to 80% Minimum Typical Maximum Units 100 425 ps 45 55 % 20 ms 470 µs NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Please refer to the phase noise plots. NOTE 3: Please see the FemtoClockNG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes and configures DSM_ENA = 0 and ADC_EN = 0. NOTE 4: Integration range: 12kHz-20MHz. NOTE 5: Integration range: 1kHz-40MHz. IDT8N3Q001GCD REVISION A MARCH 6, 2012 7 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Noise Power dBc Hz Typical Phase Noise at 156.25MHz (12kHz - 20MHz) Offset Frequency (Hz) NOTE: RMS Phase Noise (Random) for Integer PLL Feedback and fXTAL=100.000MHz. IDT8N3Q001GCD REVISION A MARCH 6, 2012 8 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx nQx SCOPE nQx VEE VEE -1.3V±0.165V -0.5V± 0.125V 2.5V LVPECL Output Load AC Test Circuit 3.3V LVPECL Output Load AC Test Circuit Phase Noise Plot Noise Power VOH VREF f1 Offset Frequency VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements f2 Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter Period Jitter nQ nQ 80% 80% Q VSW I N G ➤ 20% 20% tR ➤ tcycle n+1 ➤ tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles tF Output Rise/Fall Time IDT8N3Q001GCD REVISION A MARCH 6, 2012 tcycle n ➤ Q Cycle-to-Cycle Jitter 9 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Parameter Measurement Information, continued nQ Q t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Select Pins The FSEL[1:0] pins have internal pulldowns and OE control pins have internal pullups; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. SCLK and SDATA should be left floating if not used. IDT8N3Q001GCD REVISION A MARCH 6, 2012 10 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω R1 50Ω _ LVPECL R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 Input Zo = 50Ω R2 84Ω RTT Figure 1A. 3.3V LVPECL Output Termination IDT8N3Q001GCD REVISION A MARCH 6, 2012 Figure 1B. 3.3V LVPECL Output Termination 11 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Termination for 2.5V LVPECL Outputs level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C. Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250Ω R3 250Ω 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50Ω 2.5V LVPECL Driver R2 62.5Ω R2 50Ω R4 62.5Ω R3 18Ω Figure 2A. 2.5V LVPECL Driver Termination Example Figure 2B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50Ω R2 50Ω Figure 2C. 2.5V LVPECL Driver Termination Example IDT8N3Q001GCD REVISION A MARCH 6, 2012 12 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Schematic Layout Figure 3 shows an example of IDT8N3Q001 application schematic. In this example, the device is operated at VCC = 3.3V. As with any high speed analog circuitry, the power supply pins are vulnerable to noise. To achieve optimum jitter performance, power supply isolation is required. The IDT8N3Q001 provides separate power supplies to isolate from coupling into the internal PLL. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supply frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitances in the local area of all devices. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1uF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. VCC R2 SP SCLK SDATA R1 SP BLM18BB221SN1 10 9 VCC C1 SCLK SDATA U1 1 2 3 C2 0.1uF 2 Ferrite Bead 10uF C3 0.1uF 3.3V DNU OE VEE VCC nQ Q 8 7 6 R3 133 R4 133 Zo = 50 Ohm Q + FSEL0 FSEL1 OE 1 3.3V Zo = 50 Ohm - 4 5 nQ FSEL0 FSEL1 R5 82.5 R6 82.5 VCC=3.3V Logic Control Input Examples Zo = 50 Ohm Set Logic Input to '1' VCC RU1 1K Set Logic Input to '0' VCC + Zo = 50 Ohm - RU2 Not Install To Logic Input pins RD1 Not Install R7 50 To Logic Input pins RD2 1K Optional Y-Termination R8 50 R9 50 Figure 3. IDT8N3Q001 Application Schematic IDT8N3Q001GCD REVISION A MARCH 6, 2012 13 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Power Considerations This section provides information on power dissipation and junction temperature for the IDT8N3Q001.  Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N3Q001 is the sum of the core power plus the power dissipated in the load(s).  The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485.1mW • Power (outputs)MAX = 34.2mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 485.1mW + 34.2mW = 519.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.519W * 49.4°C/W = 110.7°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 7. Thermal Resistance JA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8N3Q001GCD REVISION A MARCH 6, 2012 0 1 2.5 49.4°C/W 44.2°C/W 41°C/W 14 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V (VCC_MAX – VOH_MAX) = 0.8V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.5V (VCC_MAX – VOL_MAX) = 1.5V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.8V)/50] * 0.8V = 19.2mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.5V)/50] * 1.5V = 15mW Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW IDT8N3Q001GCD REVISION A MARCH 6, 2012 15 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Reliability Information Table 8. JA vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 49.4°C/W 44.2°C/W 41°C/W NOTE: For proper thermal dissipation, the PCB layout for the pin pad should at minimum equal the package pin dimensions. Transistor Count The transistor count for IDT8N3Q001 Rev G is: 47,372 IDT8N3Q001GCD REVISION A MARCH 6, 2012 16 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Package Outline and Package Dimensions IDT8N3Q001GCD REVISION A MARCH 6, 2012 17 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. Shown below are the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy, contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 10-lead Ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and to the VCXO pull range of minimum 100 ppm. Other default frequencies and order codes are available from IDT on request. For more information on available default frequencies, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Part Order/Number 8N X X XXX X X - dddd XX X X Shipping Package 8: Tape & Reel (no letter): Tray FemtoClock NG Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) I/O Identifier 0: LVCMOS 3: LVPECL 4: LVDS Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin 001 XO 10 OE@2 003 XO 10 OE@1 V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 — 085 XO 6 OE@1 270 XO 6 OE@1 271 XO 6 OE@2 272 XO 6 nOE@2 273 XO 6 nOE@1 IDT8N3Q001GCD REVISION A MARCH 6, 2012 Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. dddd fXTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO Integer XO Fractional XO 1000 to 1999 2000 to 2999 100.000 Last digit = L: configuration pre-programmed and not changable Die Revision G Option Code (Supply Voltage and Frequency-Stability) A: VCC = 3.3V±5%, ±100ppm B: VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm F: VCC = 2.5V±5%, ±50ppm K: VCC = 3.3V±5%, ±20ppm L: VCC = 2.5V±5%, ±20ppm 18 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Table 9. Device Marking Industrial Temperature Range (TA = -40°C to 85°C) Marking IDT8N3x001yG- ddddCDI Commercial Temperature Range (TA = 0°C to 70°C) IDT8N3x001yG- ddddCD x = Number of Default Frequencies, y = Option Code, dddd=Default-Frequency and VCXO Pull Range IDT8N3Q001GCD REVISION A MARCH 6, 2012 19 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO Revision History Sheet Rev Table Page A 9 19 Description of Change Date Table 9 Device Marking, corrected marking. IDT8N3Q001GCD REVISION A MARCH 6, 2012 20 3/6/12 ©2012 Integrated Device Technology, Inc. IDT8N3Q001 REV G Data Sheet QUAD-FREQUENCY PROGRAMMABLE-XO We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2012. 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