8N3SV75KC-0080CDI8

LVPECL Frequency-Programmable VCXO IDT8N3SV75 DATASHEET General Description Features The IDT8N3SV75 is a LVPECL Frequency-Programmable VCXO with very flexible frequency and pull-range programming capabilities. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package. • • Fourth generation FemtoClock® NG technology • • Frequency programming resolution is 218Hz and better • Absolute pull range (APR) programmable from typical ±4.5 to ±754.5ppm • • • • • • One 2.5V/3.3V LVPECL clock output The device can be factory-programmed to any frequency in the range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to the very high degree of frequency precision of 218Hz or better. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz Factory-programmable VCXO pull range and control voltage polarity Output enable control input, LVCMOS/LVTTL compatible RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.5ps (typical), 2.5V or 3.3V supply voltage -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package Block Diagram Pin Assignment PFD & LPF ÷P OSC FemtoClock® NG VCO 1950-2600MHz Q nQ ÷N A/D VC ÷MINT, MFRAC 7 1 6 VCC 2 5 nQ VEE 3 4 Q IDT8N3SV75 6-lead ceramic 5mm x 7mm x 1.55mm package body CD Package Top View 114.285 MHz 2 VC OE 7 25 Configuration Register (ROM) (Frequency, Pull-range, Polarity) OE Pullup IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 1 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VC Input 2 OE Input 3 VEE Power Negative power supply. 4, 5 Q, nQ Output Differential clock output. LVPECL interface levels. 6 VCC Power Positive power supply. VCXO Control Voltage input. Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance RPULLUP Input Pullup Resistor Minimum Typical Maximum Units OE 5.5 pF VC 10 pF 50 k Function Tables Table 3A. OE Configuration Input OE 0 1 (default) Output Enable Outputs Q, nQ are in high-impedance state. Outputs are enabled. Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 2 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Principles of Operation Frequency Configuration The block diagram consists of the internal 3rd overtone crystal and oscillator which provide the reference clock fXTAL of 114.285MHz. The PLL includes the FemtoClock® NG VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference. The feedback divider is fractional supporting a huge number of output frequencies. Internal registers are used to hold up the factory pre-set configuration setting. The P, M, and N frequency configurations support an output frequency range 15.476MHz to 866.67MHz and 975MHz to 1,300MHz. An order code is assigned to each frequency configuration and the VCXO pull-range programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information Section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. For more information on programming capabilities of the device for custom frequency and pull-range configurations, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determined by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: 1 MFRAC + 0.5 f OUT = f XTAL  -------------  MINT + ------------------------------------PN 18 2 IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 3 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Power Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 130 160 mA Minimum Typical Maximum Units 2.375 2.5 2.625 V 120 155 mA Typical Maximum Units Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Power Supply Voltage IEE Power Supply Current Test Conditions Table 4C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.8 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50 to VCC – 2V. Table 4D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.8 V VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V NOTE 1: Outputs terminated with 50 to VCC – 2V. IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 4 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Table 4E. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol VIH Parameter Input High Voltage Test Conditions Minimum VCC = 3.3V Maximum Units 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = VIN = 3.465V -0.3 0.8 V VCC = VIN = 2.5V -0.3 0.7 V 5 µA VIL Input Low Voltage IIH Input High Current OE VCC = VIN = 3.465V or 2.625V IIL Input Low Current OE VCC = 3.465V or 2.625V, VIN = 0V IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 Typical 5 -150 µA ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO AC Electrical Characteristics Table 5A. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency Q, nQ fI Initial Accuracy fS fA fT Temperature Stability Test Conditions Minimum Typical Maximum Units 15.476 866.67 MHz 975 1,300 MHz Measured @ 25°C, VC = VCC/2 ±10 ppm Option code = A or B ±100 ppm Option code = E or F ±50 ppm Option code = K or L ±20 ppm Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm Option code A, B (10 year life) ±113 ppm Option code E, F (10 year life) ±63 ppm Option code K, L (10 year life) ±33 ppm 6 12 ps 1.8 2.8 ps Aging Total Stability tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 tjit(per) Period Jitter; NOTE 1 tjit(Ø) RMS Phase Jitter (Random); NOTE 2, 3 156.25MHz, Integration Range: 12kHz - 20MHz 0.5 0.66 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2,3 156.25MHz, Integration Range: 1kHz - 40MHz 0.9 1.3 ps 500MHz fOUT 1300MHz 0.44 0.77 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2,3,4 fXTAL = 114.285mhz 100MHz fOUT 500MHz 0.52 0.90 ps 15MHz fOUT 100MHz 0.74 1.2 ps N(100) Single-side band phase noise, 100Hz from Carrier 156.25MHz -69 dBc/Hz N(1k) Single-side band phase noise, 1kHz from Carrier 156.25MHz -98 dBc/Hz N(10k) Single-side band phase noise, 10kHz from Carrier 156.25MHz -123 dBc/Hz N(100k) Single-side band phase noise, 100kHz from Carrier 156.25MHz -128 dBc/Hz N(1M) Single-side band phase noise, 1MHz from Carrier 156.25MHz -140 dBc/Hz N(10M) Single-side band phase noise, 10MHz from Carrier 156.25MHz -145 dBc/Hz PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise 1kHz - 50MHz -71.2 dBc tR / tF Output Rise/Fall Time odc Output Duty Cycle tSTARTUP Device startup time after power up 20% to 80% 80 500 ps 45 55 % 10 ms Notes continued on next page. IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 6 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE: Characterized with VC = VCC/2. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Refer to the phase noise plot. NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Table 5B. VCXO Control Voltage Input (VC) Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol KV Parameter Test Conditions Minimum Oscillator Gain, NOTE 1, 2, 3 VCC = 3.3V Oscillator Gain, NOTE 1, 2, 3 Typical Maximum Units 7.57 477.27 ppm/V VCC = 2.5V 10 630 ppm/V BSL Variation -1 +1 % LVC Control Voltage Linearity; NOTE 4 BW Modulation Bandwidth 100 kHz ZVC VC Input Impedance 500 k VCNOM Nominal Control Voltage VCC/2 V VC Control Voltage Tuning Range; NOTE 4 0 ±0.1 VCC V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: VC = 10% to 90% of VCC. NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V. E.g. for ADC_GAIN [6:0] = 000001 the pull range is ± 12.5ppm, resulting in an oscillator gain of 25ppm ÷ 3.3V = 7.57ppm/V. NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application. NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VCC. IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 7 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Noise Power (dBc/Hz) Typical Phase Noise at 156.25MHz (12kHz - 20MHz) Offset Frequency (Hz) IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 8 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx SCOPE nQx nQx VEE VEE -1.3V±0.165V -0.5V± 0.125V 2.5 LVPECL Output Load AC Test Circuit 3.3V LVPECL Output Load AC Test Circuit nQ Q RMS Phase Jitter Output Rise/Fall Time nQ nQ Q Q tcycle n tcycle n+1 tjit(cc) = tcycle n – tcycle n+1 1000 Cycles Output Duty Cycle /Pulse Width/Period IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 Cycle -to-Cycle Jitter 9 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Parameter Measurement Information, continued VOH VREF 1 2 3 4 6 VOL contains 68.26% of all measurements contains 95.4% of all measurements contains 99.73% of all measurements contains 99.99366% of all measurements contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) Histogram Mean Period (First edge after trigger) Period Jitter Applications Information Termination for 3.3V LVPECL Outputs transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ LVPECL Input Zo = 50 R1 84 Figure 1A. 3.3V LVPECL Output Termination IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 R2 84 Figure 1B. 3.3V LVPECL Output Termination 10 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Termination for 2.5V LVPECL Outputs level. The R3 in Figure 2B can be eliminated and the termination is shown in Figure 2C. Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 50 R3 250 + 50 + 50 – 50 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 2A. 2.5V LVPECL Driver Termination Example Figure 2B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 – 2.5V LVPECL Driver R1 50 R2 50 Figure 2C. 2.5V LVPECL Driver Termination Example IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 11 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Schematic Layout the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. Figure 3 shows an example of IDT8N3SV75 application schematic. In this example, the device is operated at VCC = 3.3V. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. Figure 3. IDT8N3SV75 Application Schematic IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 12 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Power Considerations This section provides information on power dissipation and junction temperature for the IDT8N3SV75. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N3SV75 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 160mA = 554.40mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 554.40mW + 30mW = 584.40mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.584W * 49.4°C/W = 113.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 6 Lead Ceramic VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 0 1 2 49.4°C/W 44.2°C/W 42.1°C/W 13 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V Figure 4. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V (VCC_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V (VCC_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 14 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Reliability Information Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 49.4°C/W 44.2°C/W 42.1°C/W Transistor Count The transistor count for IDT8N3SV75 is: 47,414 IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 15 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Package Outline and Package Dimensions B D2 C F (TYP.) N A D1 N E (TYP.) PIN 1 INDEX O 1 6 Terminal Option Pkg. J (TYP.) Metalized A B C DIMENSION IN MM MIN. NOM. MAX. 4.85 5.00 5.15 6.85 7.00 7.15 1.35 1.50 1.65 D1 2.41 2.54 2.67 D2 E F G H J 4.95 2.47 0.47 1.27 - 5.08 2.6 0.60 1.40 0.15 Ref. 0.65 Ref. 5.21 2.73 0.73 1.53 - SYMBOL IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 16 H (TYP.) 1 G (TYP.) ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Ordering Information for FemtoClock® NG Ceramic-Package XO and VCXO Products programmable VCXO with a voltage supply of 2.5V, a 50 ppm crystal frequency accuracy, industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100 MHz and the VCXO pull range of min. 100 ppm. The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequencies, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. Table 8 specifies the available order codes, including the device options. Example part number: the order code 8N3SV75FC-0001CDI specifies a Other default frequencies and order codes are available from IDT on request. Table 8. Order Codes Part/Order Number 8N X X XXX X X - dddd XX X X Shipping Package 8: Tape & Reel (no letter): Tray FemtoClock NG Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) I/O Identifier 0: LVCMOS 3: LVPECL 4: LVDS Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin 001 XO 10 OE@2 003 XO 10 OE@1 V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 — 085 XO 6 OE@1 270 XO 6 OE@1 271 XO 6 OE@2 272 XO 6 nOE@2 273 XO 6 nOE@1 Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. dddd fXTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO Integer XO Fractional XO 1000 to 1999 2000 to 2999 100.000 Last digit = L: configuration pre-programmed and not changeable Die Revision C Option Code (Supply Voltage and Frequency-Stability) A: VCC = 3.3V±5%, ±100ppm B: VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm F: VCC = 2.5V±5%, ±50ppm K: VCC = 3.3V±5%, ±20ppm L: VCC = 2.5V±5%, ±20ppm NOTE: For order information, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 17 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Table 9. Device Marking Industrial Temperature Range (TA = -40°C to 85°C) Marking IDT8N3SV75yCddddCDI Commercial Temperature Range (TA = 0°C to 70°C) IDT8N3SV75yCddddCD y = Option Code, dddd=Default-Frequency and VCXO Pull Range IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 18 ©2013 Integrated Device Technology, Inc. IDT8N3SV75 Data Sheet LVPECL-FREQUENCY PROGRAMMABLE VCXO Revision History Sheet Rev Table Page A 5A 6 Description of Change Date RMS Phase Jitter, Test Conditions, corrected typos for 500MHz and 100MHz; “” to “” IDT8N3SV75CCD REVISION A NOVEMBER 19, 2013 19 11/19/2013 ©2013 Integrated Device Technology, Inc. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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