8N4DV85LC-0049CDI8

LVDS Dual-Frequency Programmable VCXO IDT8N4DV85 DATASHEET General Description Features The IDT8N4DV85 is a LVDS Dual-Frequency Programmable VCXO with very flexible frequency and pull-range programming capabilities. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package. • • Fourth generation FemtoClock® NG technology • • • • • • • • • Two factory-programmed output frequencies The device can be factory-programmed to any two frequencies in the range of 15.476MHz to 866.67MHz and from 975MHz to 1300 MHz to the very high degree of frequency precision of 218Hz or better. The output frequency is selected by the FSEL pin. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1300MHz Frequency programming resolution is 218Hz and better Absolute pull range (APR) programmable from ±4.5 to ±754.5ppm One 2.5V or 3.3V LVDS clock output Output enable control input, LVCMOS/LVTTL compatible RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.47ps (typical) 2.5V or 3.3V supply voltage -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package Block Diagram Pin Assignment PFD & LPF ÷P OSC FemtoClock® NG VCO 1950-2600MHz Q nQ ÷N 114.285 MHz 2 A/D VC FSEL Pulldown VC 1 6 VCC FSEL 2 5 nQ GND 3 4 Q ÷MINT, MFRAC 9 7 23 Configuration Register (ROM) (Frequency, Pull range, Polarity) IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 1 IDT8N4DV85 6-lead ceramic 5mm x 7mm x 1.55mm package body CD Package Top View ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VC Input 2 FSEL Input 3 GND Power Negative power supply. 4, 5 Q, nQ Output Differential clock output. LVDS interface levels. 6 VCC Power Positive power supply. VCXO Control Voltage input. Pulldown NOTE 1 Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels. NOTE 1.Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance RPULLDOWN Input Pulldown Resistor Minimum Typical Maximum Units FSEL 5.5 pF VC 10 pF 50 k IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 2 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Function Tables Table 3A. Output Frequency RangeNOTE 1 15.476MHz to 866.67MHz 975MHz to 1300MHz NOTE 1.Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. Principles of Operation The block diagram consists of the internal 3RD overtone crystal and oscillator which provide the reference clock fXTAL of 114.285MHz. The PLL includes the FemtoClock NG VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference. The feedback divider is fractional supporting a huge number of output frequencies. Internal registers are used to hold up to two different factory pre-set configuration settings. The configuration is selected via the FSEL pin. Changing the FSEL control results in an immediate change of the output frequency to the selected register values. The P, M, and N frequency configurations support an output frequency range 15.476MHz to 866.67MHz and 975MHz to 1,300MHz. Table 3B. Frequency Selection Input IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 Selects 0 (default) Frequency 0 1 Frequency 1 Frequency Configuration An order code is assigned to each frequency configuration and the VCXO pull-range programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information Section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determined by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: 1 MFRAC + 0.5 f OUT = f XTAL  ------------  MINT + ------------------------------------PN 18 2 FSEL For more information on programming capabilities of the device for custom frequency and pull-range configurations, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. (1) 3 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI -0.5V to VCC+ 0.5V Outputs, IO (LVDS) Continuous Current Surge Current  10mA 15mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VCC Power Supply Voltage IDD Power Supply Current Test Conditions Minimum 3.135 Typical Maximum Units 3.3 3.465 V 140 175 mA Minimum Typical Maximum Units 3.135 3.3 3.465 V 136 170 mA Maximum Units Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VCC Power Supply Voltage IDD Power Supply Current Test Conditions Table 4C. LVCMOS/LVTTL DC Characteristic, VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current FSEL VCC = VIN = 3.465V or 2.625V IIL Input Low Current FSEL VCC = 3.465V or 2.625V, VIN = 0V IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 Test Conditions Minimum VCC = 3.3V 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = VIN = 3.465V -0.3 0.8 V VCC = VIN = 2.5V -0.3 0.7 V 150 µA 4 -5 Typical µA ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Table 4D. LVDS DC Characteristics, VCC = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 330 454 mV 50 mV 1.31 V 50 mV 1.14 1.23 Table 4E. LVDS DC Characteristics, VCC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 Test Conditions Minimum Typical Maximum Units 247 320 454 mV 50 mV 1.30 V 50 mV 1.13 5 1.22 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO AC Electrical Characteristics Table 5A. AC Characteristics, VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency Q fI Initial Accuracy fS fA fT tjit(cc) Test Conditions Temperature Stability Typical Maximum Units 15.476 866.67 MHz 975 1300 MHz Measured @ 25°C, VC = VCC/2 ±10 ppm Option code = A or B ±100 ppm Option code = E or F ±50 ppm Option code = K or L ±20 ppm Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm Option code A, B (10 year life) ±113 ppm Option code E, F (10 year life) ±63 ppm Option code K, L (10 year life) ±33 ppm 6 14 ps 4 6 ps 156.25MHz, Integration Range: 12kHz - 20MHz 0.47 0.71 ps 15.576MHz  fout  100MHz, Integration Range: 12kHz - 20MHz 0.76 1.4 ps 100MHz < fout 500MHz, Integration Range: 12kHz - 20MHz 0.48 0.63 ps 500MHz < fout 1300MHz, Integration Range: 12kHz - 20MHz 0.46 0.67 ps Aging Total Stability NOTE 1 Cycle-to-Cycle Jitter JitterNOTE1 tjit(per) RMS Period tjit(Ø) RMS Phase Jitter (Random)NOTE 2,3 tjit(Ø) Minimum RMS Phase Jitter (Random)NOTE 2,3  fXTAL = 114.285MHz N(100) Single-side band phase noise, 100Hz from Carrier 156.25MHz -58 dBc/Hz N(1k) Single-side band phase noise,  1kHz from Carrier 156.25MHz -86 dBc/Hz N(10k) Single-side band phase noise,  10kHz from Carrier 156.25MHz -111 dBc/Hz N(100k) Single-side band phase noise, 100kHz from Carrier 156.25MHz -117 dBc/Hz N(1M) Single-side band phase noise,  1MHz from Carrier 156.25MHz -126 dBc/Hz N(10M) Single-side band phase noise,  10MHz from Carrier 156.25MHz -136 dBc/Hz PSNR Power Supply Noise Ratio 50mV Sinusoidal Noise 1kHz - 50MHz -58.7 dBc/Hz tR / tF Output Rise/Fall Time IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 20% to 80% 6 80 500 ps ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Table 5A. AC Characteristics, VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter odc Output Duty Cycle tOSC tSET Test Conditions Minimum Typical Maximum Units 55 % Device startup time after power-up 15 ms Output frequency settling time after FSEL0 and FSEL1 values are changed 1 ms 45 NOTE 1.This parameter is defined in accordance with JEDEC standard 65. NOTE 2. Refer to the phase noise plot. NOTE 3. Refer to the FemtoClock NG Ceramic 5 x 7 Modules Programming Guide for additional information on PLL feedback modes and the optimum configuration for phase noise. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: Characterized with VC = VCC/2. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. Table 5B. VCXO Control Voltage Input (VC) Characteristics, VCC = 3.3V ± 5% or VCC = 2.5V ± 5%, TA = -40°C to 85°C Symbol KV Parameter Test Conditions Minimum Oscillator Gain; NOTE 1, 2, 3 VCC = 3.3V Oscillator Gain NOTE 1, 2, 3 Typical Maximum Units 7.57 477.27 ppm/V VCC = 2.5V 10 630 ppm/V BSL Variation -1 +1 % LVC Control Voltage Linearity BW Modulation Bandwidth 100 kHz ZVC VC Input Impedance 500 k VCNOM Nominal Control Voltage VCC/2 V VC Control Voltage Tuning Range; NOTE 4 0 ±0.1 VCC V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1. VC = 0V to VCC. Oscillator gain is programmed by IDT. Gain = (25 * N) ÷ VCC and is in the range of n = 1 to n = 63. NOTE 2. Nominal oscillator gain: Refer to the programming guide for optimal pull range and control voltage tuning NOTE 3. For best phase noise performance, use the lowest KV that meets the requirements of the application. NOTE 4. BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC in percent. VC ranges from 10% to 90% VCC. IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 7 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO SSB Phase Noise (dBc/Hz) RMS Phase Jitter Offset from Carrier Frequency (Hz) IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 8 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Parameter Measurement Information SCOPE SCOPE 3.3V±5% POWER SUPPLY + Float GND – Q VCC Q VCC 2.5V±5% POWER SUPPLY + Float GND – nQ nQ 2.5V LVDS Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit nQ Q tcycle n tcycle n+1 tjit(cc) = |tcycle n – tcycle n+1| 1000 Cycles Cycle-to-Cycle Jitter RMS Phase Jitter VOH nQ VREF VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Reference Point (Trigger Edge) Q Histogram Mean Period (First edge after trigger) Output Duty Cycle/Pulse Width/Period RMS Period Jitter IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 9 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Parameter Measurement Information, continued nQ 80% 80% VOD Q 20% 20% tR tF Output Rise/Fall Time Differential Output Voltage Setup Offset Voltage Setup IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 10 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Applications Information Recommendations for Unused Input Pins Inputs: LVCMOS Pins All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The LVDS Driver standard termination schematic as shown in Figure 1A can be used with either type of output structure. Figure 1B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. ZO ZT ZT LVDS Receiver Figure 1A. Standard Termination LVDS Driver ZO  ZT C ZT 2 LVDS ZT Receiver 2 Figure 1B. Optional Termination IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 11 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Power Considerations This section provides information on power dissipation and junction temperature for the IDT8N4DV85.  Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N4DV85 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. • Power (core)MAX = VCC_MAX * ICC_MAX = 3.465V * 175mA = 606.375mW • 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.606W * 49.4°C/W = 114.9°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for a 6-Lead Ceramic 5mm x 7mm Package, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 0 1 2 49.4°C/W 44.2°C/W 42.1°C/W 12 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Reliability Information Table 7. JA vs. Air Flow Table for a 6-Lead Ceramic 5mm x 7mm Package JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 49.4°C/W 44.2°C/W 42.1°C/W Transistor Count The transistor count for IDT8N4DV85 is: 47,414 IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 13 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Package Outline and Package Dimensions IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 14 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. The table below specifies the available order codes, including the device options and default frequency configurations. Example part number: the order code 8N3QV01FG-0001CDI specifies a programmable, quad default-frequency VCXO with a voltage supply of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy, contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and to the VCXO pull range of min. 100 ppm. Other default frequencies and order codes are available from IDT on request. For more information on available default frequencies, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Part/Order Number 8N X X XXX X X - dddd XX X X Shipping Package 8: Tape & Reel (no letter): Tray FemtoClock NG Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) I/O Identifier 0: LVCMOS 3: LVPECL 4: LVDS Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin 001 XO 10 OE@2 003 XO 10 OE@1 V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 — 085 XO 6 OE@1 270 XO 6 OE@1 271 XO 6 OE@2 272 XO 6 nOE@2 273 XO 6 nOE@1 Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. dddd fXTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO 1000 to 1999 2000 to 2999 100.000 Integer XO Fractional XO Last digit = L: configuration pre-programmed and not Die Revision C Option Code (Supply Voltage and Frequency-Stability) A: VCC = 3.3V±5%, ±100ppm B: VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm F: VCC = 2.5V±5%, ±50ppm K: VCC = 3.3V±5%, ±20ppm L: VCC = 2.5V±5%, ±20ppm NOTE: For order information, also see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 15 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Device Marking Table 8. Device Marking Industrial Temperature Range (TA = -40°C to 85°C) Marking IDT8N4DV85yC- ddddCDI Commercial Temperature Range (TA = 0°C to 70°C) IDT8N4DV85yC- ddddCD x = Number of Default Frequencies, y = Option Code, dddd = Default-Frequency and VCXO Pull Range. IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 16 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO Revision History Sheet Rev A B B Table Page T6 4 12 T7 13 T4D T4E 5A Description of Change Date Absolute Maximum Rating - corrected Package Thermal Impedance. Power Considerations - corrected Thermal Resistance table, updated Junction Temperature calculation. Corrected Air Flow table. 4/27/12 4 5 3.3V LVDS DC Characteristics Table - updated specs. 2.5V LVDS DC Characteristics Table - updated specs. Per PCN #N1206-02. 8/22/12 6 RMS Phase Jitter, Test Conditions, fixed test conditions:  15.576MHz – 100MHz, to 15.576MHz  fout  100MHz,  100MHz – 500MHz, to 100MHz < fout 500MHz,  500MHz – 1300MHz, to 500MHz < fout 1300MHz IDT8N4DV85CCD REVISION B NOVEMBER 20, 2013 17 11/20/2013 ©2013 Integrated Device Technology, Inc. IDT8N4DV75 Data Sheet LVDS DUAL-FREQUENCY PROGRAMMABLE VCXO We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support Sales netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2013. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. (Rev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan www.renesas.com For further information on a product, technology, the most up-to-date version of a document, or your nearest sales office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners. © 2020 Renesas Electronics Corporation. All rights reserved.