Quad-Frequency Programmable
VCXO
IDT8N4QV01 REV G
DATASHEET
General Description
Features
The IDT8N4QV01 is a Quad-Frequency Programmable VCXO with
very flexible frequency and pull-range programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum of high clock frequency and low phase noise
performance. The device accepts 2.5V or 3.3V supply and is
packaged in a small, lead-free (RoHS 6) 10-lead ceramic 5mm x
7mm x 1.55mm package.
•
•
Fourth generation FemtoClock® NG technology
•
Four power-up default frequencies (see part number order codes),
re-programmable by I2C
•
I2C programming interface for the output clock frequency, APR
and internal PLL control registers
•
•
Frequency programming resolution is 435.9Hz ÷N
•
•
•
•
One 2.5V or 3.3V LVDS differential clock output
Besides the 4 default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4QV01 can be programmed via the I2C
interface to any output clock frequency between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷N (N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to 4
independent PLL, P, M and N divider registers (P, MINT, MFRAC and
N), reprogramming those registers to other frequencies under
control of FSEL0 and FSEL1 is supported. The extended
temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements.
•
•
•
•
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Absolute pull-range (APR) programmable from ±4.5ppm to
±754.5ppm
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.494ps
(typical)
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.594ps (typical)
2.5V or 3.3V supply voltage modes
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
114.285 MHz
2
A/D
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
7
VC 1
8 VDD
OE 2
7 nQ
GND 3
÷MINT, MFRAC
VC
9 SDATA
Q
nQ
÷N
7
25
Configuration Register (ROM)
(Frequency, APR, Polarity)
I2C Control
6 Q
FSEL1 5
OSC
FemtoClock® NG
VCO
1950-2600MHz
PFD
&
LPF
FSEL0 4
÷P
10 SCLK
Pin Assignment
IDT8N4QV01 REV G DATA SHEET
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
Pullup
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 1. Pin Descriptions
Number
Name
Type
Description
1
VC
Input
2
OE
Input
3
GND
Power
4, 5
FSEL0,
FSEL1
Input
6, 7
Q, nQ
Output
Differential clock output. LVDS interface levels.
8
VDD
Power
Power supply pin.
9
SDATA
Input
Pullup
I2C Data Input. LVCMOS/LVTTL interface levels.
10
SCLK
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
VCXO Control Voltage. The control voltage versus frequency characteristics are
set by the ADC_GAIN[5:0] register bits.
Pullup
Output enable pin. See Table 3B for function. LVCMOS/LVTTL interface levels.
Power supply ground.
Pulldown
Default frequency select pins. See Table 3A for function and Table 8 for the
default frequency order codes. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
RPULLUP
RPULLDOWN
Test Conditions
Minimum
Typical
Maximum
Units
FSEL[1:0], SDATA, SCLK
5.5
pF
VC
10
pF
Input Pullup Resistor
50
k
Input Pulldown Resistor
50
k
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Function Tables
Table 3A. Default Frequency Selection
Input
FSEL1
FSEL0
Operation
0 (default)
0 (default)
Default frequency 0
0
1
Default frequency 1
1
0
Default frequency 2
1
1
Default frequency 3
NOTE: The default frequency is the output frequency after power-up. One of four default frequencies is selected by FSEL[1:0]. See
programming section for details.
Table 3B. OE Configuration
Input
OE
0
1 (default)
Output Enable
Outputs Q, nQ are in high-impedance state.
Outputs are enabled.
NOTE: OE is an asynchronous control.
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Block Diagram with Programming Registers
÷P
OSC
Output Divider N
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
114.285 MHz
2
Feedback Divider M (25 Bit)
MINT
(7 bits)
7
MFRAC
(18 bits)
A/D
VC
7
18
7
34
Programming Registers
I2C Control
7
ADC_GAIN
ADC_POL
I2C:
6 bits
1 bit
Def:
6 bits
1 bit
P0
30
SCLK
SDATA
Pullup
Pullup
30
30
FSEL[1:0]
OE
MFRAC0
7
N0
I2C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
P1
MINT1
MFRAC1
N1
I C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
P2
MINT2
MFRAC2
N2
I2C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
2
30
MINT0
41
P3
MINT3
MFRAC3
N3
I2C:
2 bits
7 bits
18 bits
7 bits
Def:
2 bits
7 bits
18 bits
7 bits
00
34
01
34
34
10
34
11
34
Pulldown, Pulldown
Pullup
Def: Power-up default register setting for I2C registers
ADC_GAINn, ADC_POL, Pn, MINTn, MFRACn and Nn
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Principles of Operation
The block diagram consists of the internal 3rd overtone crystal and
oscillator which provide the reference clock fXTAL of either
114.285MHz or 100MHz. The PLL includes the FemtoClock NG VCO
along with the Pre-divider (P), the feedback divider (M) and the post
divider (N). The P, M, and N dividers determine the output frequency
based on the fXTAL reference and must be configured correctly for
proper operation. The feedback divider is fractional supporting a
huge number of output frequencies. The configuration of the
feedback divider to integer-only values results in an improved output
phase noise characteristics at the expense of the range of output
frequencies. In addition, internal registers are used to hold up to four
different factory pre-set P, M, and N configuration settings. These
default pre-sets are stored in the I2C registers at power-up. Each
configuration is selected via the FSEL[1:0] pins and can be read back
using the SCLK and SDATA pins.
As identified previously, the configurations of P, M (MINT & MFRAC)
and N divider settings are stored the I2C register, and the
configuration loaded at power-up is determined by the FSEL[1:0]
pins.
Table 4. Frequency Selection
Input
The user may choose to operate the device at an output frequency
different than that set by the factory. After power-up, the user may
write new P, N and M settings into one or more of the four
configuration registers and then use the FSEL[1:0] pins to select the
newly programmed configuration. Note that the I2C registers are
volatile and a power supply cycle will reload the pre-set factory
default conditions.
FSEL1
FSEL0
Selects
Register
0 (def.)
0 (def.)
Frequency 0
P0, MINT0, MFRAC0, N0
0
1
Frequency 1
P1, MINT1, MFRAC1, N1
1
0
Frequency 2
P2, MINT2, MFRAC2, N2
1
1
Frequency 3
P3, MINT3, MFRAC3, N3
Frequency Configuration
An order code is assigned to each frequency configuration
programmed by the factory (default frequencies). For more
information on the available default frequencies and order codes,
please see the Ordering Information Section in this document. For
available order codes, see the FemtoClock NG Ceramic-Package XO
and VCXO Ordering Product Information document.
If the user does choose to write a different P, M, and N configuration,
it is recommended to write to a configuration which is not currently
selected by FSEL[1:0] and then change to that configuration after the
I2C transaction has completed. Changing the FSEL[1:0] controls
results in an immediate change of the output frequency to the
selected register values. The P, M, and N frequency configurations
support an output frequency range 15.476MHz to 866.67MHz and
975MHz to 1,300MHz.
For more information and guidelines on programming of the device
for custom frequency configurations, the register description, the
pull-range programming and the serial interface description, see the
FemtoClock NG Ceramic 5x7 Module Programming Guide.
The devices use the fractional feedback divider with a delta-sigma
modulator for noise shaping and robust frequency synthesis
capability. The relatively high reference frequency minimizes phase
noise generated by frequency multiplication and allows more efficient
shaping of noise by the delta-sigma modulator.
The output frequency is determined by the 2-bit pre-divider (P), the
feedback divider (M) and the 7-bit post divider (N). The feedback
divider (M) consists of both a 7-bit integer portion (MINT) and an
18-bit fractional portion (MFRAC) and provides the means for
high-resolution frequency generation. The output frequency fOUT is
calculated by:
1
MFRAC + 0.5
f OUT = f XTAL ------------- MINT + ----------------------------------- (1)
PN
18
2
The four configuration registers for the P, M (MINT & MFRAC) and N
dividers which are named Pn, MINTn, MFRACn and Nn with n = 0 to
3. “n” denominates one of the four possible configurations.
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.63V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO (SDATA)
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
Package Thermal Impedance, JA
49.4C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
10mA
15mA
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDD = 3.3V ±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Power Supply Voltage
IDD
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
160
mA
Table 5B. Power Supply DC Characteristics, VDD = 2.5V ±5%, TA = -40°C to 85°C
Symbol
Parameter
VDD
Power Supply Voltage
IDD
Power Supply Current
IDT8N4QV01GCD REVISION A MARCH 11, 2014
Test Conditions
6
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
155
mA
©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 5C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High
Voltage
VIL
Input Low
Voltage
Test Conditions
Minimum
SEL [1:0], OE
VCC =3.3V +5%
SEL [1:0], OE
Typical
Maximum
Units
1.7
VCC +0.3
V
VCC =2.5V +5%
1.7
VCC +0.3
V
SEL [1:0]
VCC =3.3V +5%
-0.3
0.5
V
OE
VCC =3.3V +5%
-0.3
0.8
V
SEL [1:0]
VCC =2.5V +5%
-0.3
0.5
V
OE
VCC =2.5V +5%
-0.3
0.8
V
10
µA
OE
IIH
Input High
Current
SDATA,
SCLK
VDD = VIN = 3.465V or 2.625V
5
µA
FSEL0,
FSEL1
VDD = VIN = 3.465V or 2.625V
150
µA
OE
IIL
Input Low
Current
-500
µA
SDATA,
SCLK
VDD = 3.465V or 2.625V,
VIN = 0V
-150
µA
FSEL0,
FSEL1
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA
Table 5D. LVDS DC Characteristics, VDD = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C
Symbol
Parameter
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
IDT8N4QV01GCD REVISION A MARCH 11, 2014
Test Conditions
Minimum
Typical
Maximum
Units
247
350
454
mV
50
mV
1.375
V
50
mV
1.0
7
1.20
©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
AC Electrical Characteristics
Table 6A. VCXO Control Voltage Input (VC) Characterisitics, VDD = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C
Symbol
Parameter
Oscillator Gain, NOTE 1, 2, 3
VDD = 3.3V
KV
Oscillator Gain, NOTE 1, 2, 3
VDD = 2.5V
Test Conditions
Minimum
Typical
Maximum
Units
ADC_GAIN[5:0] = 000001
7.57
ppm/V
ADC_GAIN[5:0] = 000010
15.15
ppm/V
ADC_GAIN[5:0] = XXXXXX
2·12.5 ÷ VDD
ADC_GAIN
ppm/V
ADC_GAIN[5:0] = 111110
469.69
ppm/V
ADC_GAIN[5:0] = 111111
477.27
ppm/V
ADC_GAIN[5:0] = 000001
10
ppm/V
ADC_GAIN[5:0] = 000010
20
ppm/V
ADC_GAIN[5:0] = XXXXXX
2·12.5 ÷ VDD
ADC_GAIN
ppm/V
ADC_GAIN[5:0] = 111110
620
ppm/V
ADC_GAIN[5:0] = 111111
630
ppm/V
BSL Variation; NOTE 4
-5
Incremental; NOTE 5
-10
±1
+5
±5
+10
%
LVC
Control Voltage Linearity
BW
Modulation Bandwidth
100
kHz
ZVC
VC Input Impedance
500
k
VCNOM
Nominal Control Voltage
VDD÷2
V
VC
Control Voltage Tuning
Range; NOTE 4
0
VDD
%
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: VC = 0V to VDD.
NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V.
E.g. for ADC_GAIN[6:0] = 00.0001 the pull range is ±12.5ppm, resulting in an oscillator gain of 2 * 12.5ppm ÷ 3.3V = 7.57ppm/V.
NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application.
NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VDD.
NOTE 5: Incremental slope is defined as the linearity in percent of the raw data (not relative to BSL) from 10% to 90% VDD.
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Table 6B. AC Characteristics, VDD = 3.3V ±5% or 2.5V ±5%, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency Q, nQ
fVCO
VCO Frequency
fI
Initial Accuracy
fS
fA
fT
Temperature Stability
Aging
Total Stability
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tjit(per)
Period Jitter; NOTE 1
Test Conditions
Minimum
Output Divider, N = 3 to126
Maximum
Units
15.476
866.67
MHz
975
1,300
MHz
1980
2600
MHz
Measured at 25°C
±10
ppm
Option code = A or B
±100
ppm
Option code = E or F
±50
ppm
Option code = K or L
±20
ppm
Frequency drift over 10 year life
±3
ppm
Output Divider, N = 2
Typical
Frequency drift over 15 year life
±5
ppm
Option code A or B (10 year life)
±113
ppm
Option code E or F (10 year life)
±63
ppm
Option code K or L (10 year life)
±33
ppm
20
ps
2.85
4
ps
0.475
0.990
ps
fOUT 156.25MHz, NOTE 2, 3, 4
0.494
0.757
ps
fOUT 156.25MHz, NOTE 2, 3, 5
0.594
ps
17MHz fOUT 1300MHz,
NOTE 2,3,4
tjit(Ø)
RMS Phase Jitter (Random)
Fractional PLL feedback and
fXTAL=114.285MHz (0xxx order
codes)
N(100)
Single-side band phase noise,
100 Hz from Carrier
156.25MHz
-73.8
dBc/Hz
N(1k)
Single-side band phase noise,
1kHz from Carrier
156.25MHz
-99.8
dBc/Hz
N(10k)
Single-side band phase noise,
10kHz from Carrier
156.25MHz
-126.1
dBc/Hz
N(100k)
Single-side band phase noise,
100kHz from Carrier
156.25MHz
-129.3
dBc/Hz
N(1M)
Single-side band phase noise,
1MHz from Carrier
156.25MHz
-140.3
dBc/Hz
N(10M)
Single-side band phase noise,
10MHz from Carrier
156.25MHz
-144.3
dBc/Hz
PSNR
Power Supply Noise Rejection
50mV Sinusoidal Noise
1kHz - 50MHz
-54
db
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
tOSC
Oscillator Start-Up Time
tSET
Output Frequency Settling Time
after FSEL0 and FSEL1 Values
are Changed
20% to 80%
100
425
45
55
%
20
ms
470
ps
µs
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. All AC parameters are characterized with P=1 and pull range ±250 ppm.
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.
NOTE 2: Please refer to the phase noise plots.
NOTES continued on next page.
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on finding the optimum configuration
for phase noise.
NOTE 4: Integration range: 12kHz-20MHz.
NOTE 5: Integration range: 1kHz-40MHz.
Noise Power
dBc
Hz
Typical Phase Noise at 156.25MHz (12kHz - 20MHz)
Offset Frequency (Hz)
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Parameter Measurement Information
SCOPE
SCOPE
3.3V±5%
POWER SUPPL
+ Float GND
Q
VDD
Q
VDD
2.5V±5%
POWER SUPPL
+ Float GND
nQ
nQ
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
VOH
VREF
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Histogram
Reference Point
Mean Period
(Trigger Edge)
(First edge after trigger)
RMS Phase Jitter
Period Jitter
nQ
nQ
Q
t PW
Q
t PW
➤
odc =
PERIOD
➤
tcycle n+1
➤
tjit(cc) = tcycle n tcycle n+1
1000 Cycles
x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
IDT8N4QV01GCD REVISION A MARCH 11, 2014
tcycle n
➤
t
Cycle-to-Cycle Jitter
11
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Parameter Measurement Information (continued)
VDDMIN
nQ
80%
80%
VDD
VOD
Q
Correct Frequency
20%
20%
Output
tR
tF
➤
Output Rise/Fall Time
Start-Up
Differential Output Voltage Setup
Offset Voltage Setup
IDT8N4QV01GCD REVISION A MARCH 11, 2014
12
t startup
➤
Not to Scale
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IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
Applications Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Select Pins
All control pins have internal pulldowns; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
LVDS Driver Termination
standard termination schematic as shown in Figure 1A can be used
with either type of output structure. Figure 1B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
ZO ZT
ZT
LVDS
Receiver
Figure 1A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 1B. Optional Termination
LVDS Termination
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8N4QV01.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the IDT8N4QV01 is the sum of the core power plus the power dissipated in the load(s). The following is the
power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 160mA = 554.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 49.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.554W * 49.4°C/W = 112.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead Ceramic 5mm x 7mm Package, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT8N4QV01GCD REVISION A MARCH 11, 2014
0
1
2.5
49.4°C/W
44.2°C/W
41°C/W
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QUAD-FREQUENCY PROGRAMMABLE-VCXO
Reliability Information
Table 8. JA vs. Air Flow Table for a 10-lead Ceramic 5mm x 7mm Package
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
49.4°C/W
44.2°C/W
41°C/W
Transistor Count
The transistor count for IDT8N4QV01 is: 47,372
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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Package Outline and Package Dimensions
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products
contains a 114.285MHz internal crystal as frequency source,
industrial temperature range, a lead-free (6/6 RoHS) 10-lead ceramic
5mm x 7mm x 1.55mm package and is factory-programmed to the
default frequencies of 100, 122.88, 125 and 156.25MHz and to the
VCXO pull range of min. 100 ppm.
The programmable VCXO and XO devices support a variety of
devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient
temperature range and the frequency accuracy. The device options,
default frequencies and default VCXO pull range must be specified at
the time of order and are programmed by IDT before the shipment.
The table below specifies the available order codes, including the
device options and default frequency configurations. Example part
number: the order code 8N3QV01FG-0001CDI specifies a
programmable, quad default-frequency VCXO with a voltage supply
of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy,
Other default frequencies and order codes are available from IDT on
request. For more information on available default frequencies, see
the FemtoClock NG Ceramic-Package XO and VCXO Ordering
Product Information document.
Part/Order Number
8N X
X
XXX X X - dddd XX X
X
Shipping Package
8: Tape & Reel
(no letter): Tray
FemtoClock NG
Ambient Temperature Range
“I”: Industrial: (TA = -40°C to 85°C)
(no letter) : (TA = 0°C to 70°C)
I/O Identifier
0: LVCMOS
3: LVPECL
4: LVDS
Package Code
CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm
Number of Default Frequencies
S: 1: Single
D: 2: Dual
Q: 4: Quad
Part Number
Function
#pins
OE fct. at
pin
001
XO
10
OE@2
003
XO
10
OE@1
V01
VCXO
10
OE@2
V03
VCXO
10
OE@1
V75
VCXO
6
OE@2
V76
VCXO
6
nOE@2
V85
VCXO
6
—
085
XO
6
OE@1
270
XO
6
OE@1
271
XO
6
OE@2
272
XO
6
nOE@2
273
XO
6
nOE@1
IDT8N4QV01GCD REVISION A MARCH 11, 2014
Default-Frequency and VCXO Pull Range
See document FemtoClock NG Ceramic-Package XO and VCXO
Ordering Product Information.
dddd
fXTAL (MHz)
PLL feedback
Use for
0000 to 0999
114.285
Fractional
VCXO, XO
Integer
XO
Fractional
XO
1000 to 1999
2000 to 2999
100.000
Last digit = L: configuration pre-programmed and not changeable
Die Revision
G (opt. 207)
Option Code (Supply Voltage and Frequency-Stability)
A: VCC = 3.3V±5%, ±100ppm
B: VCC = 2.5V±5%, ±100ppm
E: VCC = 3.3V±5%, ±50ppm
F: VCC = 2.5V±5%, ±50ppm
K: VCC = 3.3V±5%, ±20ppm
L: VCC = 2.5V±5%, ±20ppm
17
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Table 9. Device Marking
Industrial Temperature Range (TA = -40°C to 85°C)
Marking
IDT8N4xV01yGddddCDI
Commercial Temperature Range (TA = 0°C to 70°C)
IDT8N4xV01yGddddCD
x = Number of Default Frequencies, y = Option Code, dddd=Default-Frequency and VCXO Pull Range
IDT8N4QV01GCD REVISION A MARCH 11, 2014
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Revision History Sheet
Rev
Table
Page
Description of Change
A
T9
18
Table 9 Device Marking, corrected marking.
3/6/12
A
T1
T6A
2
8
Deleted “(see table 3C)” from the first table row, description column.
NOTE 2; Deleted “from table 3C”.
3/13/14
IDT8N4QV01GCD REVISION A MARCH 11, 2014
Date
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©2014 Integrated Device Technology, Inc.
IDT8N4QV01 REV G DATA SHEET
QUAD-FREQUENCY PROGRAMMABLE-VCXO
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