8N4SV75EC-0007CDI

LVDS Frequency-Programmable VCXO IDT8N4SV75 DATA SHEET General Description Features The IDT8N4SV75 is a LVDS Frequency-Programmable VCXO with very flexible frequency and pull-range programming capabilities. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package. • • Fourth generation FemtoClock® NG technology • • Frequency programming resolution is 218Hz and better • Absolute pull-range (APR) programmable from ±4.5 to ±754.5ppm • • • One 2.5V / 3.3V LVDS clock output • • • 2.5V or 3.3V supply voltage The device can be factory-programmed to any frequency in the range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to the very high degree of frequency precision of 218Hz or better. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz Factory-programmable VCXO pull range and control voltage polarity Output enable control input, LVCMOS/LVTTL compatible RMS phase jitter @ 156.25MHz (12kHz - 20MHz):  0.53ps (typical) -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package Block Diagram Pin Assignment PFD & LPF ÷P OSC FemtoClock® NG VCO 1950-2600MHz Q nQ ÷N VC 1 6 VDD OE 2 5 nQ GND 3 4 Q 114.285 MHz 2 A/D VC ÷MINT, MFRAC 7 7 25 Configuration Register (ROM) (Frequency, APR, Polarity) OE IDT8N4SV75 6-lead ceramic 5mm x 7mm x 1.55mm package body CD Package Top View Pullup IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 1 ©2013 Integrated Device Technology, Inc. IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VC Input 2 OE Input 3 GND Power Power supply ground. 4, 5 Q, nQ Output Differential clock output pair. LVDS interface levels. 6 VDD Power Power supply pin. VCXO Control Voltage input. Pullup Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance RPULLUP Input Pullup Resistor Test Conditions Minimum Typical Maximum Units OE 5.5 pF VC 10 pF 50 k IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 2 ©2013 Integrated Device Technology, Inc. IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Function Tables Table 3A. OE Configuration Input OE Output Enable 0 Outputs Q, nQ are in high-impedance state. 1 (default) Outputs are enabled. Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. Principles of Operation The block diagram consists of the internal 3RD overtone crystal and oscillator which provide the reference clock fXTAL of 114.285MHz. The PLL includes the FemtoClock® NG VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference. The feedback divider is fractional supporting a huge number of output frequencies. Internal registers are used to hold up to two different factory pre-set configuration settings. The configuration is selected via the FSEL pin. Changing the FSEL control results in an immediate change of the output frequency to the selected register values. The P, M, and N frequency configurations support an output frequency range 15.476MHz to 866.67MHz and 975MHz to 1,300MHz. Table 3C. Frequency Selection Input IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 Selects 0 (default) Frequency 0 1 Frequency 1 Frequency Configuration The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determined by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: 1 MFRAC + 0.5 f OUT = f XTAL  ------------  MINT + ------------------------------------PN 18 2 FSEL An order code is assigned to each frequency configuration and the VCXO pull-range programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information Section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. For more information on programming capabilities of the device for custom frequency and pull range configurations, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. (1) 3 ©2013 Integrated Device Technology, Inc. IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.  These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond  those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for  extended periods may affect product reliability. Item Rating Supply Voltage, VDD 3.63V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current  10mA 15mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C  DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 140 175 mA Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 2.5 2.625 V 136 170 mA Table 4C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V or 2.625V IIL Input Low Current OE VDD = 3.465V or 2.625V, VIN = 0V IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 Test Conditions Minimum VDD = 3.3V Maximum Units 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 5 µA 4 -150 Typical µA ©2013 Integrated Device Technology, Inc. IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 330 454 mV 50 mV 1.31 V 50 mV 1.14 1.23 Table 4E. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change IDT8N4SV75CCD REVISION B NOVEMBER 6, 2013 Test Conditions Minimum Typical Maximum Units 247 320 454 mV 50 mV 1.30 V 50 mV 1.13 5 1.22 ©2013 Integrated Device Technology, Inc. IDT8N4SV75 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO AC Electrical Characteristics Table 5A. AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency Q, nQ fI Initial Accuracy fS fA fT Temperature Stability Test Conditions Minimum Typical Maximum Units 15.476 866.67 MHz 975 1,300 MHz Measured @ 25°C, VC = VDD/2 ±10 ppm Option code = A or B ±100 ppm Option code = E or F ±50 ppm Option code = K or L ±20 ppm Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm Option code A, B (10 year life) ±113 ppm Option code E, F (10 year life) ±63 ppm Option code K, L (10 year life) ±33 ppm Aging Total Stability tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 6 14 ps tjit(per) Period Jitter; NOTE 1 4 6 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2, 3 156.25MHz, Integration Range: 12kHz - 20MHz 0.53 0.73 ps 500MHz