8N4SV76LC-0044CDI

LVDS Frequency-Programmable VCXO IDT8N4SV76 DATASHEET Factory Datasheet. Contains Confidential Information. Do not send to customers. General Description Features The IDT8N4SV76 is an LVDS Frequency-Programmable VCXO with very flexible frequency and pull-range programming capabilities. The device uses IDT’s fourth generation FemtoClock® NG technology for an optimum of high clock frequency and low phase noise performance. The device accepts 2.5V or 3.3V supply and is packaged in a small, lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package. • • Fourth generation FemtoClock® NG technology • • Frequency programming resolution is 218Hz and better • Absolute pull-range (APR) programmable from ±4.5 to ±754.5ppm • • • • • • One 2.5V or 3.3V LVDS clock output The device can be factory-programmed to any frequency in the range of 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz to the very high degree of frequency precision of 218Hz or better. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. Programmable clock output frequency from 15.476MHz to 866.67MHz and from 975MHz to 1,300MHz Factory-programmable VCXO pull range and control voltage polarity Output enable control input, LVCMOS/LVTTL compatible RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.53ps (typical) 2.5V or 3.3V supply voltage -40°C to 85°C ambient operating temperature Lead-free (RoHS 6) 6-lead ceramic 5mm x 7mm x 1.55mm package Block Diagram Pin Assignment PFD & LPF ÷P OSC FemtoClock® NG VCO 1950-2600MHz Q nQ ÷N 114.285 MHz 2 A/D VC 6 VDD 5 nQ GND 3 4 Q ÷MINT, MFRAC 7 7 25 Configuration Register (ROM) (Frequency, Pull-range, Polarity) nOE VC 1 nOE 2 Pulldown IDT8N4SV76 6-lead ceramic 5mm x 7mm x 1.55mm package body CD Package Top View Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 1 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Pin Description and Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 VC Input 2 nOE Input 3 GND Power Power supply ground. 4, 5 Q, nQ Output Differential clock output pair. LVDS interface levels. 6 VDD Power Power supply pin. VCXO Control Voltage input. Pulldown Output enable pin. See Table 3A for function. LVCMOS/LVTTL interface levels. NOTE: Pulldown refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions CIN Input Capacitance RPULLDOWN Input Pulldown Resistor Minimum Typical Maximum Units nOE 5.5 pF VC 10 pF 50 k Function Tables Table 3A. nOE Configuration Input nOE 0 (default) 1 Output Enable Outputs are enabled. Outputs Q, nQ are in high-impedance state. . Table 3B. Output Frequency Range 15.476MHz to 866.67MHz 975MHz to 1,300MHz NOTE: Supported output frequency range. The output frequency can be programmed to any frequency in this range and to a precision of 218Hz or better. Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 2 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Block Diagram with Factory-Configuration Registers ÷P OSC Output Divider N PFD & LPF FemtoClock® NG VCO 1950-2600MHz ÷N Q nQ 114.285MHz 2 Feedback Divider M (25 Bit) MINT (7 bits) 7 MFRAC (18 bits) A/D VC 7 18 7 34 Factory - Programming Registers nOE ADC_GAIN ADC_POL I2C: 6 bits 1 bit Def: 6 bits 1 bit P MINT MFRAC I2C: 2 bits 7 bits 18 bits Def: 2 bits 7 bits 18 bits 41 7 34 Pulldown Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 3 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Principles of Operation Frequency Configuration The block diagram consists of the internal 3rd overtone crystal and oscillator which provide the reference clock fXTAL of 114.285MHz. The PLL includes the FemtoClock® VCO along with the Pre-divider (P), the feedback divider (M) and the post divider (N). The P, M, and N dividers determine the output frequency based on the fXTAL reference. The feedback divider is fractional supporting a huge number of output frequencies. Internal registers are used to hold up the factory pre-set configuration setting. The P, M, and N frequency configurations support an output frequency range 15.476MHz to 866.67MHz and 975MHz to 1,300MHz. An order code is assigned to each frequency configuration and the VCXO pull-range programmed by the factory (default frequencies). For more information on the available default frequencies and order codes, please see the Ordering Information Section in this document. For available order codes, see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. For more information on programming capabilities of the device for custom frequency and pull-range configurations, see the FemtoClock NG Ceramic 5x7 Module Programming Guide. The devices use the fractional feedback divider with a delta-sigma modulator for noise shaping and robust frequency synthesis capability. The relatively high reference frequency minimizes phase noise generated by frequency multiplication and allows more efficient shaping of noise by the delta-sigma modulator. The output frequency is determined by the 2-bit pre-divider (P), the feedback divider (M) and the 7-bit post divider (N). The feedback divider (M) consists of both a 7-bit integer portion (MINT) and an 18-bit fractional portion (MFRAC) and provides the means for high-resolution frequency generation. The output frequency fOUT is calculated by: 1 MFRAC + 0.5 f OUT = f XTAL  -------------  MINT + ------------------------------------PN 18 2 Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 4 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 3.63V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Package Thermal Impedance, JA 49.4C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 140 175 mA Minimum Typical Maximum Units 2.375 2.5 2.625 V 135 170 mA Maximum Units Table 4B. Power Supply DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current Test Conditions Table 4C. LVCMOS/LVTTL DC Characteristic, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VIL Input Low Voltage IIH Input High Current nOE VDD = VIN = 3.465V or 2.625V IIL Input Low Current nOE VDD = 3.465V or 2.625V, VIN = 0V Typical VDD = 3.3V 2 VDD + 0.3 V VDD = 2.5V 1.7 VDD + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.5V -0.3 0.7 V 150 µA -5 µA Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 5 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Table 4D. LVDS DC Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 330 454 mV 50 mV 1.31 V 50 mV 1.14 1.23 Table 4E. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter VOD Differential Output Voltage VOD VOD Magnitude Change VOS Offset Voltage VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 247 320 454 mV 50 mV 1.30 V 50 mV 1.13 1.22 Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 6 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. AC Electrical Characteristics Table 5A. AC Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency Q, nQ fI Initial Accuracy fS fA fT Temperature Stability Test Conditions Minimum Typical Maximum Units 15.476 866.67 MHz 975 1,300 MHz Measured @ 25°C, VC = VDD/2 ±10 ppm Option code = A or B ±100 ppm Option code = E or F ±50 ppm Option code = K or L ±20 ppm Frequency drift over 10 year life ±3 ppm Frequency drift over 15 year life ±5 ppm Option code A, B (10 year life) ±113 ppm Option code E, F (10 year life) ±63 ppm Option code K, L (10 year life) ±33 ppm Aging Total Stability tjit(cc) Cycle-to-Cycle Jitter; NOTE 1 6 14 ps tjit(per) Period Jitter; NOTE 1 4 6 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2,3 156.25MHz, Integration Range: 12kHz - 20MHz 0.53 0.73 ps 500MHz < fOUT 1300MHz 0.46 0.67 ps tjit(Ø) RMS Phase Jitter (Random); NOTE 2,3 fXTAL = 114.285mhz 100MHz < fOUT 500MHz 0.48 0.63 ps 15MHz fOUT 100MHz 0.76 1.4 ps N(100) Single-side Band Phase Noise, 100Hz from Carrier 156.25MHz -67 dBc/Hz N(1k) Single-side Band Phase Noise, 1kHz from Carrier 156.25MHz -89 dBc/Hz N(10k) Single-side Band Phase Noise, 10kHz from Carrier 156.25MHz -113 dBc/Hz N(100k) Single-side Band Phase Noise, 100kHz from Carrier 156.25MHz -118 dBc/Hz N(1M) Single-side Band Phase Noise, 1MHz from Carrier 156.25MHz -127 dBc/Hz N(10M) Single-side Band Phase Noise, 10MHz from Carrier 156.25MHz -137 dBc/Hz PSNR Power Supply Noise Rejection 50mV Sinusoidal Noise 1kHz - 50MHz -58.7 dBc tR / tF Output Rise/Fall Time odc Output Duty Cycle tSTARTUP Device Startup Time after Power-up 20% to 80% 80 500 ps 45 55 % 15 ms Notes are continued on next page. Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 7 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. Notes continued on next page. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE: Characterized with VC = VDD/2. NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing. NOTE 1: This parameter is defined in accordance with JEDEC standard 65. NOTE 2: Please refer to the phase noise plots. NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the optimum configuration for phase noise. Table 5B. VCXO Control Voltage Input (VC) Characteristics, VDD = 3.3V ± 5% or 2.5V ± 5, TA = -40°C to 85°C Symbol KV Parameter Test Conditions Minimum Oscillator Gain, NOTE 1, 2, 3 VDD = 3.3V Oscillator Gain, NOTE 1, 2, 3 Typical Maximum Units 7.57 477.27 ppm/V VDD = 2.5V 10 630 ppm/V BSL Variation -1 +1 % LVC Control Voltage Linearity; NOTE 4 BW Modulation Bandwidth 100 kHz ZVC VC Input Impedance 500 k VCNOM Nominal Control Voltage VDD/2 V VC Control Voltage Tuning Range; NOTE 4 0 ±0.1 VDD V NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: VC = 10% to 90% of VDD. NOTE 2: Nominal oscillator gain: Pull range divided by the control voltage tuning range of 3.3V. E.g. for ADC_GAIN [6:0] = 000001 the pull range is ± 12.5ppm, resulting in an oscillator gain of 25ppm ÷ 3.3V = 7.57ppm/V. NOTE 3: For best phase noise performance, use the lowest KV that meets the requirements of the application. NOTE 4: BSL = Best Straight Line Fit: Variation of the output frequency vs. control voltage VC, in percent. VC ranges from 10% to 90% VDD. Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 8 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Noise Power (dBc/Hz) Typical Phase Noise at 156.25MHz (12kHz - 20MHz) Offset Frequency (Hz) Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 9 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Parameter Measurement Information SCOPE 2.5V±5% POWER SUPPL + Float GND SCOPE Q VDD 3.3V±5% POWER SUPPL + Float GND Q VDD nQ nQ 2.5V LVDS Output Load AC Test Circuit 3.3V LVDS Output Load AC Test Circuit VOH VREF VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements Histogram Reference Point Mean Period (Trigger Edge) (First edge after trigger) RMS Phase Jitter Period Jitter nQ nQ Q t PW Q t ➤ tcycle n ➤ tcycle n+1 ➤ ➤ tjit(cc) = tcycle n tcycle n+1 1000 Cycles odc = PERIOD t PW x 100% t PERIOD Cycle-to-Cycle Jitter Output Duty Cycle/Pulse Width/Period Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 10 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Parameter Measurement Information, continued nQ 80% 80% VOD Q 20% 20% tR tF Output Rise/Fall Time Offset Voltage Setup Differential Output Voltage Setup Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 11 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Applications Information LVDS Driver Termination standard termination schematic as shown in Figure 1A can be used with either type of output structure. Figure 1B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The ZO  ZT LVDS Driver ZT LVDS Receiver Figure 1A. Standard Termination ZO  ZT LVDS Driver C ZT 2 LVDS ZT Receiver 2 Figure 1B. Optional Termination LVDS Termination Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 12 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Schematic Layout Figure 2 shows an example of IDT8N4SV76 application schematic. In this example, the device is operated at VDD = 3.3V. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10 kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1µF capacitor in each power pin filter should be placed on the device side of the PCB and the other components can be placed on the opposite side. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The Figure 2. IDT8N4SV76 Application Schematic Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 13 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Power Considerations This section provides information on power dissipation and junction temperature for the IDT8N4SV76. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the IDT8N4SV76 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 175mA = 606mW • Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.3V, with all outputs switching) = 606mW + 30mW = 636.38mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 49.4°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.636W * 49.4°C/W = 116.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for 6 Lead Ceramic VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 49.4°C/W 44.2°C/W 42.1°C/W Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 14 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Reliability Information Table 7. JA vs. Air Flow Table for a 6-lead Ceramic 5mm x 7mm Package JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 49.4°C/W 44.2°C/W 42.1°C/W Transistor Count The transistor count for IDT8N4SV76 is: 47,414 Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 15 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Package Outline and Package Dimensions Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 16 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Ordering Information for FemtoClock NG Ceramic-Package XO and VCXO Products default-frequency VCXO with a voltage supply of 2.5V, a LVPECL output, a 50 ppm crystal frequency accuracy, contains a 114.285MHz internal crystal as frequency source, industrial temperature range, a lead-free (6/6 RoHS) 6-lead ceramic 5mm x 7mm x 1.55mm package and is factory-programmed to the default frequencies of 100MHz, 122.88MHz, 125MHz and 156.25MHz and to the VCXO pull range of min. 100 ppm. The programmable VCXO and XO devices support a variety of devices options such as the output type, number of default frequencies, internal crystal frequency, power supply voltage, ambient temperature range and the frequency accuracy. The device options, default frequencies and default VCXO pull range must be specified at the time of order and are programmed by IDT before the shipment. Table 8 specifies the available order codes, including the device options, the default frequency codes can be obtained from the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Example part number: the order code 8N4SV76FC-0001CDI specifies a programmable, quad Other default frequencies and order codes are available from IDT on request. Table 8. Order Codes Part/Order Number 8N X X XXX X X - dddd XX X X Shipping Package 8: Tape & Reel (no letter): Tray FemtoClock NG Ambient Temperature Range “I”: Industrial: (TA = -40°C to 85°C) (no letter) : (TA = 0°C to 70°C) I/O Identifier 0: LVCMOS 3: LVPECL 4: LVDS Package Code CD: Lead-Free, 6/10-lead ceramic 5mm x 7mm x 1.55mm Number of Default Frequencies S: 1: Single D: 2: Dual Q: 4: Quad Part Number Function #pins OE fct. at pin 001 XO 10 OE@2 003 XO 10 OE@1 V01 VCXO 10 OE@2 V03 VCXO 10 OE@1 V75 VCXO 6 OE@2 V76 VCXO 6 nOE@2 V85 VCXO 6 — 085 XO 6 OE@1 270 XO 6 OE@1 271 XO 6 OE@2 272 XO 6 nOE@2 273 XO 6 nOE@1 Default-Frequency and VCXO Pull Range See document FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information. dddd fXTAL (MHz) PLL feedback Use for 0000 to 0999 114.285 Fractional VCXO, XO Integer XO Fractional XO 1000 to 1999 2000 to 2999 100.000 Last digit = L: configuration pre-programmed and not changeable Die Revision C (opt. 208) Option Code (Supply Voltage and Frequency-Stability) A: VCC = 3.3V±5%, ±100ppm B: VCC = 2.5V±5%, ±100ppm E: VCC = 3.3V±5%, ±50ppm F: VCC = 2.5V±5%, ±50ppm K: VCC = 3.3V±5%, ±20ppm L: VCC = 2.5V±5%, ±20ppm NOTE: For order information, also see the FemtoClock NG Ceramic-Package XO and VCXO Ordering Product Information document. Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 17 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Table 9. Device Marking Industrial Temperature Range (TA = -40°C to 85°C) Marking IDT8N4SV76yCddddCDI Commercial Temperature Range (TA = 0°C to 70°C) IDT8N4SV76yCddddCD y = Option Code, dddd=Default-Frequency and VCXO Pull Range Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 18 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. Revision History Sheet Rev Table Page Absolute Maximum Ratings - Thermal Impedance changed from 41.4 to 41.9. Power Considerations - corrected Thermal Resistance table and updated calculations. Reliability Information - corrected thermal table. 4/25/12 T7 5 14 15 B T4D T4E 6 6 3.3V LVDS DC Characteristics Table - updated specs. 2.5V LVDS DC Characteristics Table - updated specs. Per PCN #N1206-02. 8/22/12 B 5A 7 RMS Phase Jitter, Test Conditions, corrected typos for 500MHz and 100MHz; “” to “” A Description of Change Date 11/20/2013 Factory Datasheet. Contains Confidential Information. Do not send to customers. IDT8N4SV76CCD REVISION B NOVEMBER 20, 2013 19 ©2013 Integrated Device Technology, Inc. IDT8N4SV76 Data Sheet LVDS FREQUENCY PROGRAMMABLE VCXO Factory Datasheet. Contains Confidential Information. Do not send to customers. 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The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. 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