8S58021AKILFT

Differential-to-LVPECL/ECL Fanout Buffer ICS8S58021I DATA SHEET General Description Features The ICS8S58021I is a high speed 1-to-4 Differentialto-LVPECL/ECL Fanout Buffer. The ICS8S58021I is HiPerClockS™ optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVPECL and CML to be easily interfaced to the input with minimal use of external components. The ICS8S58021I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. • • Four LVPECL/ECL outputs • • • • • • • 50Ω internal input termination to VT ICS • • • Block Diagram IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML Output frequency: 2.5GHz (maximum) Output skew: 30ps (maximum) Part-to-part skew: 150ps (maximum) Additive phase jitter, RMS: 0.02ps (typical) Propagation Delay: 425ps (maximum) LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V ECL mode operating voltage supply range: VCC = 0V, VEE = -3.465V to 2.375V -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package IN nQ0 IN 1 nQ0 VCC VE E Q0 Q0 Pin Assignment 16 15 14 13 12 Q1 11 nQ1 VT 2 Q2 6 7 8 9 nQ2 ICS8S58021I nQ2 16-Lead VFQFN 3mm x 3mm x 0.925mm package body K Package Top View Q3 nQ3 ICS8S58021AKI REVISION A FEBRUARY 22, 2010 5 Q3 nIN 4 nQ1 VCC VREF_AC 10 Q2 VREF- AC 3 VEE nIN Q1 nQ3 VT 1 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1 IN Input Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT. 2 VT Input Input for termination. Both IN, nIN inputs are terminated to this pin. See Application Information section, Differential Input with Built-In 50Ω Termination Interface. 3 VREF_AC Output 4 nIN Input Inverting differential LVPECL clock input. RT = 50Ω termination to VT. Reference voltage for AC-coupled applications. 5, 16 VEE Power Negative supply pins. 6, 7 nQ3, Q3 Output Differential output pair. LVPECL/ECL interface levels. 8, 13 Vcc Power Power supply pins. 9, 10 nQ2, Q2 Output Differential output pair. LVPECL/ECL interface levels. 11, 12 nQ1, Q1 Output Differential output pair. LVPECL/ECL interface levels. 14, 15 nQ0, Q0 Output Differential output pair. LVPECL/ECL interface levels. ICS8S58021AKI REVISION A FEBRUARY 22, 2010 2 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V) Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V) Inputs, VI (LVPECL mode) -0.5V to VCC + 0.5V Inputs, VI (ECL mode) 0.5V to VEE – 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Input Current, IN, nIN ±25mA VT Current, IVT ±50mA Input Sink/Source, IREF_AC ±2mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, θJA, (Junction-to-Ambient) 74.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 2A. Power Supply DC Characteristics, VCC = 2.5V ± 5%, 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 2.375 3.3 3.465 V 80 mA Table 2B. Differential DC Characteristics, VCC = 2.5V ± 5%, 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter RIN Differential Input Resistance; NOTE 1 VIH Test Conditions Minimum Typical Maximum Units (IN, nIN) 40 50 60 Ω Input High Voltage (IN, nIN) 1.2 VCC V VIL Input Low Voltage (IN, nIN) 0 VIH – 0.15 V VIN Input Voltage Swing 0.15 1.4 V VDIFF_IN Differential Input Voltage Swing 0.3 2.8 V IIN Input Current; NOTE 1 35 mA VREF_AC Bias Voltage VCC – 1.17 V (IN, nIN) VCC – 1.52 VCC – 1.37 NOTE 1: Guaranteed by design. ICS8S58021AKI REVISION A FEBRUARY 22, 2010 3 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Table 2C. LVPECL DC Characteristics, VCC = 2.5V ± 5%, 3.3V ± 5%, TA = -40°C to 85°C Symbol Parameter VOH Test Conditions Minimum Typical Maximum Units Output High Voltage; NOTE 1 VCC – 1.16 VCC – 0.94 VCC – 0.765 V VOL Output Low Voltage; NOTE 1 VCC – 1.955 VCC – 1.78 VCC – 1.57 V VOUT Output Voltage Swing 0.6 1.1 V VDIFF_OUT Differential Output Voltage Swing 1.2 2.2 V NOTE 1: Outputs terminated with 50Ω to VCC – 2V. AC Electrical Characteristics Table 3. AC Characteristics, VCC = 0V; VEE = -3.3V ± 5%, -2.5V ± 5% or VCC = 2.5V ± 5%, 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter fOUT Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Test Conditions Minimum Typical Maximum Units 2.5 GHz 425 ps Output Skew; NOTE 2, 4 30 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 150 ps tjit Buffer Additive Jitter; RMS; refer to Additive Phase Jitter Section tR / tF Output Rise/Fall Time 200 156.25MHz, Integration Range: 12kHz – 20MHz 20% to 80% 0.02 25 ps 250 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters characterized at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS8S58021AKI REVISION A FEBRUARY 22, 2010 4 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz 156.25MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.02ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS8S58021AKI REVISION A FEBRUARY 22, 2010 The source generator "Rohde & Schwarz SMA 100A Signal Generator, via the clock synthesis as external input to drive the input clock IN, nIN". 5 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Parameter Measurement Information 2V VCC Qx nQ0:nQ3 SCOPE 80% 80% VOUT 20% 20% Q0:Q3 LVPECL tR nQx tF VEE -0.375V to -1.465V Output Load AC Test Circuit Output Rise/Fall Time Par t 1 nQx nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(o) tsk(pp) Part-to-Part Skew Output Skew nIN VIN, VOUT IN VDIFF_IN, VDIFF_OUT nQ0:nQ3 Q0:Q3 tPD Single-ended & Differential Input/Output Voltage Swing ICS8S58021AKI REVISION A FEBRUARY 22, 2010 Propagation Delay 6 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Application Information Recommendations for Unused Output Pins Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Wiring the Differential Input to Accept Single-Ended Levels Figure 1 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50Ω applications, R3 and R4 can be 100Ω. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8S58021AKI REVISION A FEBRUARY 22, 2010 7 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER 3.3V Differential Input with Built-In 50Ω Termination Interface the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. The differential signal must meet the VIN and VIH input requirements. Figures 2A to 2D show interface examples for the IN/nIN input with built-in 50Ω terminations driven by 3.3V 3.3V 3.3V 3.3V Zo = 50Ω Zo = 50Ω IN IN VT Zo = 50Ω VT Zo = 50Ω nIN nIN Receiver LVDS Receiver LVPECL With With R1 50 Built-In Built-In 50Ω 50Ω Figure 2B. IN/nIN Input with Built-In 50Ω Driven by an LVPECL Driver Figure 2A. IN/nIN Input with Built-In 50Ω Driven by an LVDS Driver 3.3V 3.3V 3.3V Zo = 50Ω 3.3V Zo = 50Ω IN Zo = 50Ω IN VT Zo = 50Ω nIN nIN Receiver CML – Open Collector CML – Built-in 50Ω Pull-up With Receiver With Built-In Built-In 50Ω 50Ω Figure 2D. IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Built-In 50Ω Pullup Figure 2C. IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Open Collector ICS8S58021AKI REVISION A FEBRUARY 22, 2010 VT 8 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER 2.5V Differential Input with Built-In 50Ω Termination Interface suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The IN /nIN with built-in 50Ω terminations accept LVDS, LVPECL, CML and other differential signals. The differential signal must meet the VIN and VIH input requirements. Figures 3A to 3D show interface examples for the HiPerClockS IN/nIN with built-in 50Ω termination input driven by the most common driver types. The input interfaces 2.5V 2.5V 2.5V 3.3V or 2.5V Zo = 50Ω Zo = 50Ω IN IN Zo = 50Ω VT Zo = 50Ω VT nIN nIN Receiver LVDS Receiver LVPECL With With R1 18 Built-In Built-In 50Ω 50Ω Figure 3B. IN/nIN Input with Built-In 50Ω Driven by an LVPECL Driver Figure 3A. IN/nIN Input with Built-In 50Ω Driven by an LVDS Driver 2.5V 2.5V 2.5V Zo = 50Ω 2.5V Zo = 50Ω IN Zo = 50Ω IN VT Zo = 50Ω nIN nIN Receiver CML CML - Built-in 50Ω Pull-up With Receiver With Built-In Built-In 50Ω 50Ω Figure 3D. IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Built-In 50Ω Pullup Figure 3C. IN/nIN Input with Built-In 50Ω Driven by a CML Driver with Open Collector ICS8S58021AKI REVISION A FEBRUARY 22, 2010 VT 9 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω R3 125Ω 3.3V 3.3V Zo = 50Ω 3.3V R4 125Ω 3.3V 3.3V + Zo = 50Ω + _ LVPECL Input Zo = 50Ω R1 50Ω _ LVPECL R2 50Ω R1 84Ω VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC – 2)) – 2 Input Zo = 50Ω R2 84Ω RTT Figure 4A. 3.3V LVPECL Output Termination ICS8S58021AKI REVISION A FEBRUARY 22, 2010 Figure 4B. 3.3V LVPECL Output Termination 10 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Termination for 2.5V LVPECL Outputs level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 5A. 2.5V LVPECL Driver Termination Example Figure 5B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 5C. 2.5V LVPECL Driver Termination Example ICS8S58021AKI REVISION A FEBRUARY 22, 2010 11 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 6. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) ICS8S58021AKI REVISION A FEBRUARY 22, 2010 12 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8S58021I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8S58021I is the sum of the core power plus the power dissipation in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipation in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW • Power (outputs)MAX = 32.4mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32.4mW = 129.6mW Total Power_MAX (3.3V, with all outputs switching) = 277.2mW + 129.6mW = 406.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature f is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.407W * 74.7°C/W = 115.4°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 4. Thermal Resistance θJA for 16 Lead VFQFN, Forced Convection θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS8S58021AKI REVISION A FEBRUARY 22, 2010 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W 13 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. The LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL 50Ω VCC - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.765V (VCC_MAX – VOH_MAX) = 0.765V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.57V (VCC_MAX – VOL_MAX) = 1.57V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) = [(2V – 0.765V)/50Ω] * 0.765V = 18.9mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) = [(2V – 1.57V)/50Ω] * 1.57V = 13.5mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.4mW ICS8S58021AKI REVISION A FEBRUARY 22, 2010 14 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Reliability Information Table 5. θJA vs. Air Flow Table for a 16 Lead VFQFN θJA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 74.7°C/W 65.3°C/W 58.5°C/W Transistor Count The transistor count for ICS8S58021I is: 262 ICS8S58021AKI REVISION A FEBRUARY 22, 2010 15 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Package Outline and Package Dimensions Package Outline - K Suffix for 16 Lead VFQFN (Ref.) Seating Plane ND & NE Even (ND-1)x e (R ef.) A1 Index Area A3 N Top View L N e (Typ.) 2 If ND & NE 1 Anvil Singulation or Sawn Singulation are Even 2 E2 (NE -1)x e (Re f.) E2 2 b A (Ref.) D e ND & NE Odd Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C D2 2 Thermal Base D2 C Bottom View w/Type A ID Bottom View w/Type B ID Bottom View w/Type C ID BB 4 CHAMFER 4 N N-1 There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1) 2 1 2 1 CC 2 1 4 N N-1 DD 4 RADIUS 4 N N-1 AA 4 Table 6. Package Dimensions JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS8S58021AKI REVISION A FEBRUARY 22, 2010 16 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Ordering Information Table 7. Ordering Information Part/Order Number 8S58021AKILF 8S58021AKILFT Marking 1AIL 1AIL Package “Lead-Free” 16 Lead VFQFN “Lead-Free” 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Temperature -40°C to 85°C -40°C to 85°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. ICS8S58021AKI REVISION A FEBRUARY 22, 2010 17 ©2010 Integrated Device Technology, Inc. ICS8S58021I Data Sheet 6024 Silver Creek Valley Road San Jose, California 95138 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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