Low Skew, 2:1 LVPECL MUX with 1:8
Fanout and Internal Termination
8S89202
DATA SHEET
General Description
Features
The 8S89202 is a high speed 1-to-8 Differential-to-LVPECL Clock
Divider and is part of the high performance clock solutions from IDT.
The 8S89202 is optimized for high speed and very low output skew,
making it suitable for use in demanding applications such as SONET,
1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally
terminated differential inputs and VREF_AC pins allow other
differential signal families such as LVPECL, LVDS and CML to be
easily interfaced to the input with minimal use of external
components.
•
•
Three output banks, consisting of eight LVPECL output pairs total
•
•
•
•
•
•
•
•
•
•
•
Selectable output divider values of ÷1, ÷2 and ÷4
The device also has a selectable ÷1, ÷2, ÷4 output divider, which can
allow the part to support multiple output frequencies from the same
reference clock.
The 8S89202 is packaged in a small 5mm x 5mm 32-pin VFQFN
package which makes it ideal for use in space-constrained
applications.
INx, nINx inputs can accept the following differential input levels:
LVPECL, LVDS, CML
Maximum output frequency: 1.5GHz
Maximum input frequency: 3GHz
Bank skew: 6ps (typical)
Part-to-part skew: 250ps (maximum)
Additive phase jitter, RMS: 0.166ps (typical)
Propagation delay: 854ps (typical)
Output rise time: 156ps (typical)
Full 2.5V±5% and 3.3V±10% operating supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
nQC
QC
VCC
VE E
VE E
VCC
nQA3
QA3
Pin Assignment
nQA2
25
24 23 22 21 20 19 18 17
16
QB 0
13
nQB 1
29
12
QB 2
QA0
30
11
nQB 2
VCC
31
10
VCC
nMR
32
9
EN
2
3
4
VT
1
5
6
7
8
DIV S E L_C
28
DIV S E L_B
QA1
nQA0
nIN
QB 1
V R E F _AC
nQB 0
14
IN
15
27
DIV S E L_A
26
VE E
QA2
nQA1
8S89202
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
8S89202 Rev B 7/1/15
1
©2015 Integrated Device Technology, Inc.
8S89202 DATA SHEET
Block Diagram
Pullup
D IVSEL_A
QA0
nQ A 0
÷1
÷1
QA1
nQ A 1
IN
RIN=50
VT
QA2
÷2
÷2
nQ A 2
RIN=50
nIN
QA3
÷4
EN
nM R
nQ A 3
Pullup
Pullup
QB0
nQ B 0
V R E F _A C
÷2
QB1
nQ B 1
÷4
QB2
D IVSEL_B
nQ B 2
Pullup
÷2
QC
nQ C
÷4
D IVSEL_C
Pullup
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
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Rev B 7/1/15
8S89202 DATA SHEET
Table 1. Pin Descriptions
Number
Name
1, 20, 21
VEE
Power
Type
Description
2
DIVSEL_A
Input
3
IN
Input
Non-inverting differential LVPECL clock input. RIN = 50 termination to VT.
Termination center-tap input.
Negative supply pins.
Pullup
Output divider select pin. Controls output divider settings for Bank A.
See Table 3 for additional information. LVCMOS/LVTTL interface levels.
4
VT
Input
5
VREF_AC
Output
6
nIN
Input
7
DIVSEL_B
Input
Pullup
Output divider select pin. Controls output divider settings for Bank B.
See Table 3 for additional information. LVCMOS/LVTTL interface levels.
8
DIVSEL_C
Input
Pullup
Output divider select pin. Controls output divider settings for Bank C.
See Table 3 for additional information. LVCMOS/LVTTL interface levels.
9
EN
Input
Pullup
Output enable pin. See Table 3 for additional information.
LVCMOS/LVTTL interface levels.
10, 19, 22, 31
VCC
Power
Positive supply pins.
11, 12
nQB2, QB2
Output
Differential output pair. LVPECL interface levels.
13, 14
nQB1, QB1
Output
Differential output pair. LVPECL interface levels.
15, 16
nQB0, QB0
Output
Differential output pair. LVPECL interface levels.
17, 18
nQC, QC
Output
Differential output pair. LVPECL interface levels.
23, 24
nQA3, QA3
Output
Differential output pair. LVPECL interface levels.
25, 26
nQA2, QA2
Output
Differential output pair. LVPECL interface levels.
27, 28
nQA1, QA1
Output
Differential output pair. LVPECL interface levels.
29, 30
nQA0, QA0
Output
Differential output pair. LVPECL interface levels.
32
nMR
Input
Reference voltage for AC-coupled applications.
Inverting differential LVPECL clock input. RIN = 50 termination to VT.
Pullup
Master Reset. See additional 3 for additional information.
LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistor. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Test Conditions
Minimum
Typical
Maximum
Units
Symbol
Parameter
CIN
Input Capacitance
2
pF
RPULLUP
Input Pullup Resistor
25
k
Rev B 7/1/15
3
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
Function Tables
Table 3. SEL Function Table
nMR
EN
DIVSEL_A
DIVSEL_B
DIVSEL_C
Output Bank
A
Output Bank
B
Output Bank
C
0
n/a
n/a
n/a
n/a
0
0
0
1
0
n/a
n/a
n/a
0
0
0
1
1
0
0
0
÷1
÷2
÷2
1
1
1
1
1
÷2
÷4
÷4
1
2
3
4
nIN
IN
tRR
nMR
nMR asynchronously resets the outputs
VCC/2
EN
nQ
1 Output
Q
® ¬t /MR-Q
PD
nQ
2 Output
Q
nQ
4 Output
Q
Outputs go HIGH simultaneously after 4 complete input clock (IN) periods after nMR is de-asserted
Figure 1A. Reset with Output Enabled
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
4
Rev B 7/1/15
8S89202 DATA SHEET
Figure 1B. Enabled Timing
1
2
3
4
nIN
IN
EN
VCC/2
Enabled asserted
nQ
1 Output
Q
nQ
2 Output
Q
nQ
4 Output
Q
Outputs go HIGH simultaneously after EN is asserted.
The number of IN clock cycles after EN is asserted before
the outputs go HIGH varies from 2 to 6 cycles (4 cycles shown).
1
2
3
4
nIN
IN
EN
VCC/2
Enabled de-asserted to disable Q[0:7] outputs
nQ
1 Output
Q
nQ
2 Output
Q
Q
4 Output
nQ
Outputs go LOW in output sequence after EN is de-asserted.
The 4, 2 and 1 outputs go LOW in that order.
The number of IN clock cycles after EN is de-asserted
varies from 2 to 6 cycles (4 cycles shown).
Figure 1C. Disabled Timing
Rev B 7/1/15
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LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Input Current, IN, nIN
±50mA
VT Current, IVT
±100mA
Input Sink/Source, IREF_AC
±2mA
Package Thermal Impedance, JA
42.7C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Positive Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
117
131
mA
Table 4B. Power Supply DC Characteristics, VCC = 3.3V ±10%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC
Positive Supply Voltage
IEE
Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
2.97
3.3
3.63
V
125
139
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ±10% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Test Conditions
Minimum
VCC = 3.3V
Maximum
Units
2.2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
Input High Current
VCC = VIN = 3.63V or 2.625V
-125
20
µA
Input Low Current
VCC = 3.63V or 2.625V, VIN = 0V
-300
uA
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
6
Typical
Rev B 7/1/15
8S89202 DATA SHEET
Table 4D. Differential DC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
RIN
Input Resistance
IN, nIN
VIH
Input High Voltage
IN, nIN
0.15
VCC +0.3
V
VIL
Input Low Voltage
IN, nIN
0
VCC -0.15
V
VIN
Input Voltage Swing
0.15
VCC
V
VDIFF_IN
Differential Input Voltage Swing
0.3
VREF_AC
Bias Voltage
IN to VT, nIN to VT
Typical
Maximum
50
VCC -1.7
Units
V
VCC -1.3
VCC -0.9
V
Minimum
Typical
Maximum
Units
Table 4E. LVPECL DC Characteristics, VCC = 3.3V ± 10%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VCC -1.65
VCC -1.0
VCC -0.5
V
VOL
Output Low Voltage; NOTE 1
VCC -2.25
VCC -1.8
VCC -1.6
V
VOUT
Output Voltage Swing
0.7
0.8
1.1
V
VDIFF_OUT
Differential Output Voltage Swing
1.4
1.6
2.2
V
Minimum
Typical
Maximum
Units
NOTE 1: Outputs terminated with 50 to VCC – 2V.
Table 4F. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOH
Output High Voltage; NOTE 1
VCC -1.35
VCC -1.0
VCC -0.70
V
VOL
Output Low Voltage; NOTE 1
VCC -2.00
VCC -1.75
VCC -1.50
V
VOUT
Output Voltage Swing
0.6
0.8
1.0
V
VDIFF_OUT
Differential Output Voltage Swing
1.2
1.6
2.0
V
NOTE 1: Outputs terminated with 50 to VCC – 2V.
Rev B 7/1/15
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LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V ± 10% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
fOUT
Output Frequency
fIN
Input Frequency
tPD
Propagation Delay; NOTE 1
tsk(b)
Bank to Bank Skew; NOTE 2, 3
tsk(w)
tsk(o)
tsk(pp)
Part-to-Part Skew; NOTE 2, 5
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Typical
Maximum
Units
1.5
GHz
3
GHz
IN to Qx
660
845
1020
ps
nMR to Qx
600
772
905
ps
Same divide setting
6
26
ps
Bank to Bank Skew; NOTE 2, 3
Different divide setting
27
103
ps
Within-Bank Skew; NOTE 2, 4
Within same fanout bank
3
13
ps
250
ps
0.166
0.193
ps
156
218
ps
156.25MHz, Integration Range:
12kHz to 20MHz
20% to 80%
73
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8
Rev B 7/1/15
8S89202 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz
Input/Output Additive Phase Jitter, RMS @
156.25MHz (12kHz to 20MHz) = 166fs typical
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Rev B 7/1/15
The additive phase jitter for this device was measured using a Rohde
& Schwarz SMA100 input source and an Agilent E5052 Phase noise
analyzer.
9
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
Parameter Measurement Information
2V
2V
VCC
Qx
SCOPE
VCC
Qx
SCOPE
nQx
nQx
VEE
VEE
-0.5V ± 0.125V
-1.3V ± 0.33V
3.3V Output Load AC Test Circuit
2.5V Output Load AC Test Circuit
VCC
nIN
IN
nIN
V
Cross Points
IN
nQAx,
nQBx, nQC
V
IH
IN
QAx,
QBx, QC
V
IL
tPD
VEE
Propagation Delay
Input Levels
nQAx,
nQBx, nQC
80%
VIN, VOUT
80%
VDIFF_IN, VDIFF_OUT
VOUT
QAx,
QBx, QC
20%
20%
tR
tF
Differential Voltage Swing = 2 x Single-ended VIN
Output Rise/Fall Time
Single-Ended & Differential Input Swing
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
10
Rev B 7/1/15
8S89202 DATA SHEET
Parameter Measurement Information, continued
Par t 1
nQx
nQx
Qx
Qx
nQy
nQy
Par t 2
Qy
Qy
tsk(pp)
Within Bank Skew
Part-to-Part Skew
nQXx
nQXx
QXx
QXx
nQXy
nQXy
QXy
QXy
tsk(ω)
tsk(b)
Where X = Bank A, Bank B or Bank C
Bank to Bank Skew (same divide setting)
Rev B 7/1/15
Bank to Bank (different divide settings)
11
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Select Pins
LVPECL Outputs
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
2.5V LVPECL Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both VOH and VOL must meet the
VIN and VIH input requirements. Figures 2A to 2D show interface
examples for the IN/nIN with built-in 50 termination input driven by
the most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 2A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 2B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
Figure 2C. IN/nIN Input with Built-In 50
Driven by a CML Driver
Figure 2D. IN/nIN Input with Built-In 50 Driven by a
CML Driver with Built-In 50 Pullup
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
12
Rev B 7/1/15
8S89202 DATA SHEET
3.3V LVPECL Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both VOH and VOL must meet the
VIN and VIH input requirements. Figures 3A to 3D show interface
examples for the IN /nIN input with built-in 50 terminations driven by
the most common driver types. The input interfaces suggested here
are examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 3A. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Figure 3B. IN/nIN Input with Built-In 50
Driven by an LVPECL Driver
3.3V
3.3V
3.3V CML with
Built-In Pullup
Zo = 50Ω
C1
IN
50Ω
VT
Zo = 50Ω
C2
50Ω
nIN
V_REF_AC
Receiver with
Built-In 50Ω
Figure 3C. IN/nIN Input with Built-In 50
Driven by a CML Driver with Open Collector
Rev B 7/1/15
Figure 3D. IN/nIN Input with Built-In 50
Driven by a CML Driver with Built-In 50
Pullup
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LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 4B can be eliminated and the termination is
shown in Figure 4C.
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
R1
250Ω
R3
250Ω
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R2
50Ω
R4
62.5Ω
R3
18Ω
Figure 4A. 2.5V LVPECL Driver Termination Example
Figure 4B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 4C. 2.5V LVPECL Driver Termination Example
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
14
Rev B 7/1/15
8S89202 DATA SHEET
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential output is a low impedance follower output that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
R3
125
3.3V
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
Figure 5A. 3.3V LVPECL Output Termination
Rev B 7/1/15
R2
84
Figure 5B. 3.3V LVPECL Output Termination
15
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 6. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
16
Rev B 7/1/15
8S89202 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 8S89202.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 8S89202 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.63V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
The maximum current at 85°C is as follows:
IEE_MAX = 128mA
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 139mA = 504.57mW
•
Power (outputs)MAX = 27.8mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 27.8mW = 222.4mW
•
Power Dissipation for internal termination RT
Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.1V)2 / 80 = 15.12mW
Total Power_MAX = (3.63V, with all outputs switching) = 504.57mW + 222.4mW + 15.12mW = 742.09mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 42.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.742W * 42.7°C/W = 116.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on input swing, the number of loaded outputs, supply voltage, air flow and
the type of board (multi-layer).
Table 6. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
Rev B 7/1/15
0
1
2.5
42.7°C/W
37.3°C/W
33.5°C/W
17
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
VCC - 2V
Figure 7. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.5V
(VCC_MAX – VOH_MAX) = 0.5V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.5V)/50] * 0.5V = 15mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCO_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.8mW
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
18
Rev B 7/1/15
8S89202 DATA SHEET
Reliability Information
Table 7. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
42.7°C/W
37.3°C/W
33.5°C/W
Transistor Count
The transistor count for 8S89202: 689
Rev B 7/1/15
19
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
32 Lead VFQFN Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
(Ref.)
S eating Plan e
N &N
Even
(N -1)x e
(R ef.)
A1
Ind ex Area
A3
N
L
N
Anvil
Anvil
Singulation
Singula tion
e (Ty p.)
2 If N & N
1
are Even
2
OR
E2
(N -1)x e
(Re f.)
E2
2
To p View
b
A
(Ref.)
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
e
N &N
Odd
0. 08
C
D2
Bottom View w/Type C ID
2
1
2
1
4
Th er mal
Ba se
C
Bottom View w/Type A ID
CHAMFER
D2
2
RADIUS
N N-1
4
N N-1
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
Table 9. Package Dimensions
Symbol
N
A
A1
A3
b
ND & NE
D&E
D2 & E2
e
L
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Minimum
Nominal
32
0.80
0
0.25 Ref.
0.18
0.25
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
Maximum
1.00
0.05
Reference Document: JEDEC Publication 95, MO-220
0.30
8
5.00 Basic
3.0
0.30
3.3
0.50 Basic
0.40
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
0.50
20
Rev B 7/1/15
8S89202 DATA SHEET
Ordering Information
Table 8. Ordering Information
Part/Order Number
8S89202BKILF
8S89202BKILFT
8S89202BKILF/W
Marking
ICS89202BIL
ICS89202BIL
ICS89202BIL
Package
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
“Lead-Free” 32 Lead VFQFN
Shipping Packaging
Tray
Tape & Reel, pin 1 orientation: EIA-481-C
Tape & Reel, pin 1 orientation EIA-481-D
Temperature
-40C to 85C
-40C to 85C
-40C to 85C
Table 9. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
T
Quadrant 1 (EIA-481-C)
/W
Quadrant 2 (EIA-481-D)
Rev B 7/1/15
Illustration
21
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
8S89202 DATA SHEET
Revision History Sheet
Rev
Table
Page
B
T9
8
21
21
Description of Change
Date
Added Pin 1 Orientation in Tape and Reel Table.
Ordering Information - Added W part number.
LOW SKEW, 2:1 LVPECL MUX WITH 1:8 FANOUT AND INTERNAL
TERMINATION
22
7/1/15
Rev B 7/1/15
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