FemtoClock® NG
Universal Frequency Translator
Description
8T49N243
Datasheet
Features
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
375fs RMS typical jitter (including spurs): 12kHz to 20MHz
Operating Modes: synthesizer, jitter attenuator
Operates from a 10MHz to 50MHz fundamental-mode crystal or a
10MHz to 125MHz external oscillator
Accepts one LVPECL, LVDS, LVHSTL or LVCMOS input clock
Accepts frequencies ranging from 8kHz to 875MHz
Clock input monitoring
Generates two LVPECL / LVDS / HCSL or four LVCMOS device
outputs
Output frequencies ranging from 8kHz up to 1.0GHz
(differential)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
One integer divider ranging from ÷4 to ÷786,420
Three fractional output dividers (see Output Dividers)
Programmable loop bandwidth settings from 0.2Hz to 6.4kHz
Optional fast-lock function
Four general purpose I/O pins with optional support for status &
control:
Two output enable control inputs provide control over the
device outputs
Lock and Loss-of-Signal alarm outputs
Open-drain Interrupt pin
Register programmable through I2C
Full 2.5V or 3.3V supply modes, 1.8V support for LVCMOS
outputs, GPIO and control pins
-40°C to 85°C ambient operating temperature
Package: 40QFN, lead-free (RoHS 6)
The 8T49N243 has one fractional-feedback PLL that can be used as
a jitter attenuator and frequency translator. It is equipped with one
integer and one fractional output divider, allowing the generation of
up to two different output frequencies, ranging from 8kHz to 1GHz.
These frequencies are completely independent of each other, the
input reference frequencies and the crystal reference frequency. The
device places virtually no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error. The outputs may select among LVPECL, LVDS, HCSL or
LVCMOS output levels.
This makes it ideal to be used in any frequency synthesis
application, including 1G, 10G, 40G and 100G Synchronous
Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC
rates.
The 8T49N243 accepts one differential or single-ended input clock
and a fundamental-mode crystal input. The internal PLL can lock to
the input reference clock or just to the crystal to behave as a
frequency synthesizer. A second input reference (FBIN) is used as
the external feedback input for zero delay buffer functionality.
The device monitors both input references for Loss of Signal (LOS),
and generates an alarm when an input reference failure is detected.
The PLL has a register-selectable loop bandwidth from 0.2Hz to
6.4kHz. The device starts up with output Q0 set to 10MHz, and
output Q1 set to 20MHz. Loop bandwidth is set to 25Hz. Input clock,
CLK is set to 2.5MHz.
The device supports output enable inputs and Lock and LOS status
outputs.
The device is programmable through an I2C interface.
Typical Applications
OTN or SONET / SDH equipment
Gigabit and Terabit IP switches / routers including Synchronous
Ethernet
Video broadcast
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8T49N243 Datasheet
Block Diagram
Figure 1: Block Diagram
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8T49N243 Datasheet
Pin Assignments
Figure 2: Pin Assignments for 6mm x 6mm 40-Lead Package
Transistor count: 454,200
Pin Description Table
Table 1: Pin Descriptions
Type[a]
Number
Name
1
VCCA
Power
Analog function supply for core analog functions. 2.5V or 3.3V supported.
2
VCCA
Power
Analog function supply for analog functions associated with the PLL. 2.5V or
3.3V supported.
3
GPIO[0]
I/O
4
VCCO0
Power
5
Q0
O
Universal
Clock output. Please refer to the Output Drivers for more details.
6
nQ0
O
Universal
Clock output. Please refer to the Output Drivers for more details.
7
GPIO[1]
I/O
Pullup
8
nQ1
O
Universal
Clock output. Please refer to the Output Drivers for more details.
9
Q1
O
Universal
Clock output. Please refer to the Output Drivers for more details.
10
VCCO1
Power
11
SDATA
I/O
©2016 Integrated Device Technology, Inc.
Pullup
Description
General-purpose input-output. LVTTL / LVCMOS Input levels.
High-speed output supply for output pair Q0, nQ0. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
General-purpose input-output. LVTTL / LVCMOS Input levels.
High-speed output supply for output pair Q1, nQ1. 2.5V or 3.3V supported for
differential output types. LVCMOS outputs also support 1.8V.
Pullup
I2C interface bi-directional data.
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8T49N243 Datasheet
Table 1: Pin Descriptions
Type[a]
Number
Name
12
SCLK
I/O
13
VCC
Power
Core digital function supply. 2.5V or 3.3V supported.
14
VEE
Power
Negative supply voltage. All VEE pins and ePAD must be connected before any
positive supply voltage is applied.
15
VCC
Power
Core digital function supply. 2.5V or 3.3V supported.
16
CLK
I
Pulldown
Non-inverting differential clock input.
17
nCLK
I
Pullup /
Pulldown
Inverting differential clock input.
VCC / 2 when left floating (set by internal pull-up / pulldown resistors)
18
FBIN
I
Pulldown
Non-inverting differential feedback clock input. Connect to FCLK, or the output
of an external feedback divider, depending on application.
19
nFBIN
I
Pullup /
Pulldown
Inverting differential feedback clock input. Connect to nFCLK, or the output of
an external feedback divider, depending on application.
VCC / 2 when left floating (set by internal pull-up / pulldown resistors).
20
S_A1
I
Pulldown
I2C Address bit A1.
21
VCCO2
Power
22
FCLK
O
LVDS
Levels
Differential clock output pair. LVDS levels. Connect to FBIN for the
pre-configured frequency.
23
nFCLK
O
LVDS
Levels
Differential clock output pair. LVDS levels. Connect to nFBIN for the
pre-configured frequency.
24
GPIO[2]
I/O
Pullup
General-purpose input-output. LVTTL / LVCMOS Input levels.
25
nc
Unused
Do not connect.
26
nc
Unused
Do not connect.
27
nc
Unused
Do not connect.
28
GPIO[3]
I/O
Pullup
29
nINT
O
Open-drain
with pull-up
30
VCCA
Power
31
nRST
I
32
VCCA
Power
33
OSCI
I
Crystal input. Accepts a 10MHz 50MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal. For proper device
functionality, a crystal or external oscillator must be connected to this pin.
34
OSCO
O
Crystal Output. This pin must be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
©2016 Integrated Device Technology, Inc.
Pullup
Description
I2C interface bi-directional clock.
High-speed output supply voltage for output pair FCLK, nFCLK. 2.5V or 3.3V
supported for differential output types. LVCMOS outputs also support 1.8V.
General-purpose input-output. LVTTL / LVCMOS Input levels.
Interrupt output.
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
Pullup
Master Reset input. LVTTL / LVCMOS interface levels:
0 = All registers and state machines are reset to their default values
Analog function supply for core analog functions. 2.5V or 3.3V supported.
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8T49N243 Datasheet
Table 1: Pin Descriptions
Number
Name
35
nWP
Type[a]
I
Description
Pullup
Write Protect input. LVTTL / LVCMOS interface levels.
0 = Write operations on the serial port will complete normally, but will have no
effect except on interrupt registers.
36
VCCCS
Power
Output supply for control & status pins:
GPIO[3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST
1.8V, 2.5V or 3.3V supported
37
CAP
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
38
CAP_REF
Analog
PLL External Capacitance. A 0.1µF capacitance value across CAP and
CAP_REF pins is recommended.
39
VCCA
Power
Analog function supply for analog functions associated with PLL. 2.5V or 3.3V
supported.
40
S_A0
I
ePAD
Exposed
Pad
Power
Pulldown
I2C Address Bit A0.
Negative supply voltage. All VEE pins and ePAD must be connected before any
positive supply voltage is applied.
a. Pullup and Pulldown refer to internal input resistors. See Table 26, Pin Characteristics, for typical values.
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8T49N243 Datasheet
Principles of Operation
The 8T49N243 can be locked to the input clock and generate a wide range of synchronized output clocks.
It could be used for example in either the transmit or receive path of synchronous Ethernet equipment.
The 8T49N243 accepts one differential or single-ended input clock ranging from 8kHz up to 875MHz. It generates up to two output clocks
ranging from 8kHz up to 1.0GHz.
The PLL path within the 8T49N243 supports two states: Lock and Free-run. The Lock status may be monitored on register bits and pins. In the
locked state, the PLL locks to a valid clock input and its output clocks have a frequency accuracy equal to the frequency accuracy of the input
clock. In the Free-run state, the PLL outputs a clock with the same frequency accuracy as the external crystal.
Upon power up, the PLL will enter Free-run state, in this state it generates output clocks with the same frequency accuracy as the external
crystal. The 8T49N243 continuously monitors the clock input for activity (signal transitions). If no input reference is provided, the device will
remain locked to the crystal in Free-run state and will generate output frequencies as a synthesizer.
When an input clock has been validated, the PLL will transition to the Lock state.
The device supports conversion of any input frequencies to two different independent output frequencies.
The 8T49N243 has a programmable loop bandwidth from 0.2Hz to 6.4kHz.
In default configuration, the device looks for a 2.5MHz input clock. The device starts up with output Q0 set to 10MHz and output Q1 set to
20MHz. Loop bandwidth is set to 25Hz.
The device monitors both input references and generates an alarm when an input clock failure is detected on either CLK or FBIN inputs.
The device is programmable through an I2C interface and may also autonomously read its register settings from an internal One-Time
Programmable (OTP) memory.
Crystal Input
The crystal input on the 8T49N243 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency range of
10MHz 50MHz.
The oscillator input also supports being driven by a single-ended crystal oscillator or reference clock.
The long term drift will depend on the quality of the crystal or oscillator attached to this port.
This device provides the ability to double the crystal frequency input into the PLL for improved close-in phase noise performance. Refer to
Figure 3.
Figure 3: Doubler Block Diagram
Bypass Path
The crystal input or either reference input (CLK or FBIN) may be used directly as a clock source for the FCLK output dividers. This may only be
done for input frequencies of 250MHz or less.
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8T49N243 Datasheet
Input Clock Selection
The 8T49N243 accepts an input clock with frequencies ranging from 8kHz up to 875MHz. The clock input can accept LVPECL, LVDS,
LVHSTL, HCSL or LVCMOS inputs using 1.8V, 2.5V or 3.3V logic levels.
The clock input does not support transmission of spread-spectrum clocking sources. Since this family is intended for high-performance
applications, it will assume input reference sources to have stabilities of +100ppm or better, except where gapped clock inputs are used.
Input Clock Monitor
The clock input is monitored for Loss of Signal (LOS). If no activity has been detected on the clock input within a user-selectable time period
then the clock input is considered to be failed and an internal Loss-of-Signal status flag is set. The user-selectable time period has sufficient
range to allow a gapped clock missing many consecutive edges to be considered a valid input.
User-selection of the clock monitor time-period is based on a counter driven by a monitor clock. The monitor clock is fixed at the frequency of
the PLL’s VCO divided by 8. With a VCO range of 3GHz - 4GHz, the monitor clock has a frequency range of 375MHz to 500MHz.
The monitor logic for the input reference will count the number of monitor clock edges indicated in the appropriate Monitor Control register. If
an edge is received on the input reference being monitored, then the count resets and begins again. If the target edge count is reached before
an input reference edge is received, then an internal soft alarm is raised and the count re-starts. During the soft alarm period, the PLL tracking
will not be adjusted. If an input reference edge is received before the count expires for the second time, then the soft alarm status is cleared
and the PLL will resume adjustments. If the count expires again without any input reference edge being received, then a Loss-of-Signal alarm
is declared.
It is expected that for normal (non-gapped) clock operation, users will set the monitor clock count for each input reference to be slightly longer
than the nominal period of that input reference. A margin of 2-3 monitor clock periods should give a reasonably quick reaction time and yet
prevent false alarms.
For gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest expected clock gap
period. The monitor count registers support 17-bit count values, which will support at least a gap length of two clock periods for any supported
input reference frequency, with longer gaps being supported for faster input reference frequencies. Since gapped clocks usually occur on input
reference frequencies above 100MHz, gap lengths of thousands of periods can be supported.
Using this configuration for a gapped clock, the PLL will continue to adjust while the normally expected gap is present, but will freeze once the
expected gap length has been exceeded and alarm after twice the normal gap length has passed.
Once a LOS on either CLK or FBIN is detected, the appropriate internal LOS alarm will be asserted and it will remain asserted until that input
clock returns and is validated. Validation occurs once 8 rising edges have been received on that input reference. If another error condition on
the same input clock is detected during the validation time then the alarm remains asserted and the validation period starts over.
Each LOS flag may also be reflected on one of the GPIO[3:0] outputs. Changes in status of any reference can also generate an interrupt if not
masked.
Input to Output Clock Frequency
The 8T49N243 is designed to accept any frequency within its input range and generate two different output frequencies that are independent
from the input frequencies and from each other. The internal architecture of the device ensures that most translations will result in the exact
output frequency specified. Please contact IDT for configuration software or other assistance in determining if a desired configuration will be
supported exactly.
Synthesizer Mode Operation
The device may act as a frequency synthesizer with the PLL generating its operating frequency from just the crystal input. By setting the
SYN_MODE register bit and setting the STATE[1:0] field to Free-run, no input clock references are required to generate the desired output
frequencies.
When operating as a synthesizer, the precision of the output frequency will be < 1ppb for any supported configuration.
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8T49N243 Datasheet
Loop Filter and Bandwidth
The 8T49N243 uses one external capacitor of fixed value to support its loop bandwidth. When operating in synthesizer mode a fixed loop
bandwidth of approximately 200kHz is provided.
When not operating as a synthesizer, the 8T49N243 will support a range of loop bandwidths: 0.2Hz, 0.4Hz, 0.8Hz, 1.6Hz, 3.2Hz, 6.4Hz, 12Hz,
25Hz, 50Hz, 100Hz, 200Hz, 400Hz, 800Hz, 1.6kHz or 6.4kHz.
The device supports two different loop bandwidth settings: acquisition and locked. These loop bandwidths are selected from the list of options
described above. If enabled, the acquisition bandwidth is used while lock is being acquired to allow the PLL to “fast-lock”. Once locked the PLL
will use the locked bandwidth setting. If the acquisition bandwidth setting is not used, the PLL will use the locked bandwidth setting at all times.
Output Dividers
The 8T49N243 supports one integer output divider and one fractional output divider. The integer output divider block consists of two divider
stages in a series to achieve the desired total output divider ratio. The first stage divider may be set to divide by 4, 5 or 6. The second stage of
the divider may be bypassed (i.e. divide-by-1) or programmed to any even divider ratio from 2 to 131,070. The total divide ratios, settings and
possible output frequencies are shown in Table 2.
An output synchronization via the PLL_SYN bit is necessary after programming the output dividers to ensure that the outputs are
synchronized.
Table 2: Output Divide Ratios
1st-Stage Divide
2nd-Stage Divide
Total Divide
Minimum FOUT (MHz)
Maximum FOUT (MHz)
4
1
4
750
1000
5
1
5
600
800
6
1
6
500
666.7
4
2
8
375
500
5
2
10
300
400
6
2
12
250
333.3
4
4
16
187.5
250
5
4
20
150
200
6
4
24
125
166.7
...
4
131,070
524,280
0.0057
0.0076
5
131,070
655,350
0.0046
0.0061
6
131,070
786,420
0.0038
0.0051
Fractional Output Divider Programming (Q1 and FCLK)
For the FracN output divider Q1 the output divide ratio is given by:
Output Divide Ratio = (N.F)x2
N = Integer Part: 4, 5, ...(218-1)
F = Fractional Part: [0, 1, 2, ...(2 28-1)]/(228)
For integer operation of these output dividers, N = 3 is also supported for the full output frequency range.
The minimum output divide ratio defined above is valid for all CLK_SEL modes.
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8T49N243 Datasheet
Output Divider Frequency Sources
Output dividers associated with the Q[1:0] outputs take their input frequency directly from the PLL.
Output dividers associated with the FCLK outputs can take their input frequencies from the PLL, CLK or FBIN input reference frequency or the
crystal frequency.
Output Drivers
The Q[1:0] clock outputs are provided with register-controlled output drivers. By selecting the output drive type in the appropriate register,
either output can support LVCMOS, LVPECL, HCSL or LVDS logic levels.
The operating voltage ranges of each output is determined by its independent output power pin (V CCO) and thus each can have different
output voltage levels. Output voltage levels of 2.5V or 3.3V are supported for differential operation and LVCMOS operation. In addition,
LVCMOS output operation supports 1.8V VCCO.
Each output may be enabled or disabled by register bits and/or GPIO pins.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels, then both the Q and nQ outputs will toggle at the selected output frequency. All
the previously described configuration and control apply equally to both outputs. Frequency, voltage levels and enable / disable status apply to
both the Q and nQ pins. When configured as LVCMOS, the Q & nQ outputs can be selected to be phase-aligned with each other or inverted
relative to one another. Selection of phase-alignment may have negative effects on the phase noise performance of any part of the device due
to increased simultaneous switching noise within the device.
Power-Saving Modes
To allow the device to consume the least power possible for a given application, the following functions can be disabled via register
programming:
Any unused output, including all output divider logic, can be individually powered-off.
Any unused input, including the clock monitoring logic can be individually powered-off.
The digital PLL can be powered-off when running in synthesizer mode.
Clock gating on logic that is not being used.
Status / Control Signals and Interrupts
The status and control signals for the device, may be operated at 1.8V, 2.5V or 3.3V as determined by the voltage applied to the V CCCS pins.
All signals will share the same voltage levels.
Signals involved include: nWP, nINT, nRST, GPIO[3:0], S_A0, S_A1, SCLK and SDATA. The voltage used here is independent of the voltage
chosen for the digital and analog core voltages and the output voltages selected for the clock outputs.
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8T49N243 Datasheet
General-Purpose I/Os & Interrupts
The 8T49N243 provides four General Purpose Input / Output (GPIO) pins for miscellaneous status & control functions. Each GPIO may be
configured as either an input or an output. Each GPIO may be directly controlled from register bits or be used as a predefined function as
shown in Table 3. Note that the default state prior to configuration being loaded from internal OTP will be to set each GPIO to input direction to
function as an Output Enable.
Table 3: GPIO Configuration [a]
Configured as Input
Configured as Output
GPIO Pin
Fixed Function
General Purpose
Fixed Function
General Purpose
3
–
GPI[3] (default)
LOL
GPO[3]
2
–
GPI[2] (default)
LOS[0]
GPO[2]
1
OSEL[1]
GPI[1] (default)
LOS[1]
GPO[1]
0
OSEL[0] (default)
GPI[0]
–
GPO[0]
a. GPI[x]: General Purpose Input. Logic state on GPIO[x] pin is directly reflected in GPI[x] register.
LOL: Loss-of-Lock Status Flag for Digital PLL. Logic-high indicates digital PLL not locked.
GPO[x]: General Purpose Output. Logic state is determined by value written in register GPO[x].
OSEL[n]: Output Enable Control Signals for outputs Qx, nQx. Refer to Output Enable Operation section.
LOS[x]: Loss-of-Signal Status Flag for input 4eference (0 = CLK, 1 = FBIN). Logic-high indicates input reference failure.
If used in the Fixed Function mode of operation, the GPIO bits will reflect the real-time status of their respective status bits as shown in
Table 3.
The LOL alarm will support two modes of operation:
De-asserts once PLL is locked, or
De-asserts after PLL is locked and all internal synchronization operations that may destabilize output clocks are completed.
Interrupt Functionality
Interrupt functionality includes an Interrupt Status Flag for each of PLL Loss-of-Lock Status (LOL) and Loss-of-Signal Status for each input
(LOS[1:0]). Those status flags are set whenever there is an alarm on their respective functions. The status flag will remain set until the alarm
has been cleared and a ‘1’ has been written to the status flag’s register location or if a reset occurs. Each status flag will also have an interrupt
enable bit that will determine if that status flag is allowed to cause the Device Interrupt Status to be affected (enabled) or not (disabled). All
interrupt enable bits will be in the disabled state after reset. The Device Interrupt Status Flag and nINT output pin are asserted if any of the
enabled interrupt status flags are set.
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8T49N243 Datasheet
Output Enable Operation
When GPIO[1:0] are used as output enable control signals (both GPIO0 and GPIO1 must be configured as OSEL[0] and OSEL[1],
respectively), the function of the pins is to select one of four register-based maps that indicate which outputs should be enabled or disabled.
Figure 4: Output Enable Map Operation
Q0
Q1 FCLK
0
0
EN
EN
EN
0
1
DIS
EN
EN
1
0
EN
DIS
EN
1
1
DIS DIS DIS
4
Device Hardware Configuration
The8T49N243 supports an internal One-Time Programmable (OTP) memory that is pre-programmed at the factory with one complete device
configuration. This pre-programmed configuration will be loaded into the device’s registers on power-up or reset.
These default register settings can be over-written using the serial programming interface once reset is complete. Any configuration written via
the serial programming interface needs to be re-written after any power cycle or reset. Please contact IDT if a different factory-programmed
configuration is desired.
Device Start-up & Reset Behavior
The 8T49N243 has an internal Power-up Reset (POR) circuit and a master reset input pin nRST. If either is asserted, the device will be in the
Reset State.
For highly programmable devices, it’s common practice to reset the device immediately after the initial power-on sequence. IDT recommends
connecting the nRST input pin to a programmable logic source for optimal functionality. It is recommended that a minimum pulse width of 10ns
be used to drive the nRST input.
While in the reset state (nRST input asserted or POR active), the device will operate as follows:
• All registers will return to & be held in their default states as indicated in the applicable register description.
• All internal state machines will be in their reset conditions.
• The serial interface will not respond to read or write cycles.
• The GPIO signals will be configured as output enable inputs.
• All clock outputs will be disabled.
• All interrupt status and interrupt enable bits will be cleared, negating the nINT signal.
Upon the later of the internal POR circuit expiring or the nRST input negating, the device will exit reset and begin self-configuration.
The device will load its configuration using the data stored in the internal One-Time Programmable (OTP) memory.
Once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the PLL to the
crystal and begin operation. Once the PLL is locked, all the outputs derived from it will be synchronized and output phase adjustments can
then be applied if desired.
Serial Control Port Description
Serial Control Port Configuration Description
The device has a serial control port capable of responding as a slave in an I 2C compatible configuration, to allow access to any of the internal
registers for device programming or examination of internal status. All registers are configured to have default values. See the specifics for
each register for details.
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8T49N243 Datasheet
I2C Mode Operation
The I2C interface is designed to fully support v1.2 of the I2C Specification for normal and fast mode operation. The device acts as a slave
device on the I2C bus at 100kHz or 400kHz using the address defined in the Serial Interface Control register (0006h), as modified by the S_A0
& S_A1 input pin settings. The interface accepts byte-oriented block write and block read operations. Two address bytes specify the register
address of the byte position of the first register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the
highest byte (most significant bit first). Read and write block transfers can be stopped after any complete byte transfer. During a write
operation, data will not be moved into the registers until the STOP bit is received, at which point, all data received in the block write will be
written simultaneously.
For full electrical I2C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have
a size of 51k typical.
Figure 5: I2C Slave Read and Write Cycle Sequencing
Current Read
S
Dev Addr + R
A
Data 0
A
Data 1
A
A
Data n
P
Sequential Read
S
Dev Addr + W
A
Offset Addr MSB
A
Offset Addr LSB
A
A
Offset Addr MSB
A
Offset Addr LSB
A
Sr
Dev Addr + R
A
Data 0
Data 1
A
A
Data 1
A
A
Data n
P
Sequential Write
S
Dev Addr + W
from master to slave
from slave to master
Data 0
A
A
Data n
A
P
S = start
Sr = repeated start
A = acknowledge
A = non acknowledge
P = stop
The8T49N243 will not support the following functions:
I2C General Call
Slave clock stretching
I2C Start Byte protocol
CBUS compatibility
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8T49N243 Datasheet
Register Descriptions
Table 4: Register Blocks
Register Ranges Offset (Hex)
Register Block Description
0000 - 0001
Reserved
0002 - 0005
Device ID Control Registers
0006 - 0007
Serial Interface Control Registers
0008 - 002F
Digital PLL Control Registers
0030 - 0038
GPIO Control Registers
0039 - 003E
Output Driver Control Registers
003F - 004A
Output Divider Control Registers (Integer Portion)
004B - 0056
Reserved
0057 - 0062
Output Divider Control Registers (Fractional Portion)
0063 - 0067
Output Divider Source Control Registers
0068- 006B
Analog PLL Control Registers
006C - 0070
Power-Down & Lock Alarm Control Registers
0071 - 0078
Input Monitor Control Registers
0079
Interrupt Enable Register
007A - 007B
Factory Setting Registers
007C - 01FF
Reserved
0200 - 0201
Interrupt Status Registers
0202 - 020B
Reserved
020C
General-Purpose Input Status Register
020D - 0212
Global Interrupt and Boot Status Register
0213 - 03FF
Reserved
©2016 Integrated Device Technology, Inc.
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8T49N243 Datasheet
Table 5: Device ID Control Register Bit Field Locations and Descriptions
Device ID Register Control Block Field Locations
Address (Hex)
D7
D6
0002
D5
D4
D3
D2
REV_ID[3:0]
D1
D0
DEV_ID[15:12]
0003
DEV_ID[11:4]
0004
DEV_ID[3:0]
0005
DASH_CODE [10:7]
DASH_CODE [6:0]
1
Device ID Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
REV_ID[3:0]
R/W
0h
Device revision.
DEV_ID[15:0]
R/W
0606h
Device ID code.
DASH CODE [10:0]
R/W
0b
Device Dash code.
Decimal value assigned by IDT to identify the configuration loaded at the factory.
May be over-written by users at any time.
Table 6: Serial Interface Control Register Bit Field Locations and Descriptions
Serial Interface Control Block Field Locations
Address (Hex)
D7
0006
0
D6
D5
D4
D3
D2
UFTADD[6:2]
0007
D1
D0
UFTADD[1]
UFTADD[0]
Rsvd
1
Device ID Control Register Block Field Descriptions
Bit Field Name
Field Type
Default
Value
UFTADD[6:2]
R/W
11011b
UFTADD[1]
R/O
0b
I2C base address bit 1. This address bit reflects the status of the S_A1 external input
pin. See Table 1.
UFTADD[0]
R/O
0b
I2C base address bit 0. This address bit reflects the status of the S_A0 external input
pin. See Table 1.
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Description
Configurable portion of I2C base (bits 6:2) address for this device.
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 7: Digital PLL Input Control Register Bit Field Locations and Descriptions
Digital PLL Input Control Register Block Field Locations
Address (Hex)
D7
0008
D6
D5
REFSEL[2:0]
0009
D4
D3
D2
D1
D0
1
0
1
1
1
Rsvd
000A
Rsvd
1
000B
Rsvd
Rsvd
Rsvd
Rsvd
STATE[1:0]
PRE0[20:16]
000C
PRE0[15:8]
000D
PRE0[7:0]
000E
Rsvd
Rsvd
PRE1[20:16]
000F
PRE1[15:8]
0010
PRE1[7:0]
Digital PLL Input Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
REFSEL[2:0]
R/W
000b
Input reference selection for Digital PLL:
000 = Automatic selection
001 through 111 = Reserved, do not use
STATE[1:0]
R/W
00b
Digital PLL State Machine Control:
00 = Run automatically
01 = Force FREERUN state - set this if in Synthesizer mode
10 = Force NORMAL state
11 = Reserved
PRE0[20:0]
R/W
000014h
Pre-divider ratio for input reference 0 (CLK) when used by Digital PLL.
PRE1[20:0]
R/W
000014h
Pre-divider ratio for input reference 1 (FBIN) when used by Digital PLL.
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Description
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 8: Digital PLL Feedback Control Register Bit Field Locations and Descriptions
Digital PLL Feedback Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
0011
M1_0[23:16]
0012
M1_0[15:8]
0013
M1_0[7:0]
0014
M1_1[23:16]
0015
M1_1[15:8]
0016
M1_1[7:0]
0017
LCKBW[3:0]
0018
LCKDAMP[2:0]
0019
Rsvd
ACQDAMP[2:0]
Rsvd
001B
Rsvd
001C
PLLGAIN[1:0]
Rsvd
Rsvd
Rsvd
001D
Rsvd
001E
Rsvd
001F
FFh
0020
FFh
0021
FFh
0022
FFh
Rsvd
Rsvd
Rsvd
0024
Rsvd
Rsvd
FASTLCK
LOCK[7:0]
0025
Rsvd
DSM_INT[8]
0026
DSM_INT[7:0]
0027
Rsvd
Rsvd
DSMFRAC[20:16]
0029
DSMFRAC[15:8]
002A
DSMFRAC[7:0]
002B
Rsvd
002C
01h
002D
Rsvd
002E
Rsvd
002F
D0
Rsvd
Rsvd
0028
D1
ACQBW[3:0]
001A
0023
D2
DSM_ORD[1:0]
©2016 Integrated Device Technology, Inc.
DCXOGAIN[1:0]
16
Rsvd
DITHGAIN[2:0]
November 8, 2016
8T49N243 Datasheet
Digital PLL Feedback Configuration Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
M1_0[23:0]
R/W
000014h
M1 Feedback divider ratio for input reference 0 (CLK) when used by Digital PLL.
M1_1[23:0]
R/W
000014h
M1 Feedback divider ratio for input reference 1 (FBIN) when used by Digital PLL.
LCKBW[3:0]
R/W
0111b
Digital PLL Loop Bandwidth while locked:
0000 = 0.2Hz
0001 = 0.4Hz
0010 = 0.8Hz
0011 = 1.6Hz
0100 = 3.2Hz
0101 = 6.4Hz
0110 = 12Hz
0111 = 25Hz
1000 = 50Hz
1001 = 100Hz
1010 = 200Hz
1011 = 400Hz
1100 = 800Hz
1101 = 1.6kHz
1110 = 6.4kHz
1111 = Reserved
ACQBW[3:0]
R/W
©2016 Integrated Device Technology, Inc.
0111b
Digital PLL Loop Bandwidth while in acquisition (not-locked):
0000 = 0.2Hz
0001 = 0.4Hz
0010 = 0.8Hz
0011 = 1.6Hz
0100 = 3.2Hz
0101 = 6.4Hz
0110 = 12Hz
0111 = 25Hz
1000 = 50Hz
1001 = 100Hz
1010 = 200Hz
1011 = 400Hz
1100 = 800Hz
1101 = 1.6kHz
1110 = 6.4kHz
1111 = Reserved
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8T49N243 Datasheet
Digital PLL Feedback Configuration Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
LCKDAMP[2:0]
R/W
011b
Description
Damping factor for Digital PLL while locked:
000 = Reserved
001 = 1
010 = 2
011 = 5
100 = 10
101 = 20
110 = Reserved
111 = Reserved
ACQDAMP[2:0]
R/W
011b
Damping factor for Digital PLL while in acquisition (not locked):
000 = Reserved
001 = 1
010 = 2
011 = 5
100 = 10
101 = 20
110 = Reserved
111 = Reserved
PLLGAIN[1:0]
R/W
01b
Digital Loop Filter Gain settings for Digital PLL:
00 = 0.5
01 = 1
10 = 1.5
11 = 2
FASTLCK
R/W
1b
LOCK[7:0]
R/W
3Fh
DSM_INT[8:0]
R/W
02Ch
DSMFRAC[20:0]
R/W
181949h
©2016 Integrated Device Technology, Inc.
Enables Fast Lock operation for Digital PLL:
0 = Normal locking using LCKBW & LCKDAMP fields in all cases
1 = Fast Lock mode using ACQBW & ACQDAMP when not phase locked and
LCKBW & LCKDAMP once phase locked
Lock window size for Digital PLL. Unsigned 2’s complement binary number in steps
of 2.5ns, giving a total range of 640ns. Do not program to 0.
Integer portion of the Delta-Sigma Modulator value.
Fractional portion of Delta-Sigma Modulator value. Divide this number by 2 21 to
determine the actual fraction.
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November 8, 2016
8T49N243 Datasheet
Digital PLL Feedback Configuration Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
DSM_ORD[1:0]
R/W
11b
Description
Delta-Sigma Modulator Order for Digital PLL:
00 = Delta-Sigma Modulator disabled
01 = 1st order modulation
10 = 2nd order modulation
11 = 3rd order modulation
DCXOGAIN[1:0]
R/W
01b
Multiplier applied to instantaneous frequency error before it is applied to the digitally
controlled oscillator in Digital PLL:
00 = 0.5
01 = 1
10 = 2
11 = 4
DITHGAIN[2:0]
R/W
000b
Dither Gain setting for Digital PLL:
000 = no dither
001 = Least Significant Bit (LSB) only
010 = 2 LSBs
011 = 4 LSBs
100 = 8 LSBs
101 = 16 LSBs
110 = 32 LSBs
111 = 64 LSBs
Rsvd
R/W
©2016 Integrated Device Technology, Inc.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
The values observed on any GPIO pins that are used as general purpose inputs are visible in the GPI[3:0] register that is located at location
0x0219 near a number of other read-only registers.
Table 9: GPIO Control Register Bit Field Locations and Descriptions
GPIO Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
0030
Rsvd
GPIO_DIR[3:0]
0031
Rsvd
GPI3SEL[2]
GPI2SEL[2]
GPI1SEL[2]
GPI0SEL[2]
0032
Rsvd
GPI3SEL[1]
GPI2SEL[1]
GPI1SEL[1]
GPI0SEL[1]
0033
Rsvd
GPI3SEL[0]
GPI2SEL[0]
GPI1SEL[0]
GPI0SEL[0]
0034
Rsvd
GPO3SEL[2]
GPO2SEL[2]
GPO1SEL[2]
GPO0SEL[2]
0035
Rsvd
GPO3SEL[1]
GPO2SEL[1]
GPO1SEL[1]
GPO0SEL[1]
0036
Rsvd
GPO3SEL[0]
GPO2SEL[0]
GPO1SEL[0]
GPO0SEL[0]
0037
Rsvd
0038
Rsvd
GPO[3:0]
GPIO Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
GPIO_DIR[3:0]
R/W
0000b
Description
Direction control for General-Purpose I/O pins GPIO[3:0]:
0 = input mode
1 = output mode
GPI0SEL[2:0]
R/W
001b
Function of GPIO[0] pin when set to input mode by GPIO_DIR[0] register bit:
000 = General Purpose Input (value on GPIO[0] pin directly reflected in GPI[0] register bit)
001 = Output Enable control bit 0: OSEL[0], (Refer to Figure 4 for more details.)
010 = reserved
011 = reserved
100 through 111 = reserved
GPI1SEL[2:0]
R/W
000b
Function of GPIO[1] pin when set to input mode by GPIO_DIR[1] register bit:
000 = General Purpose Input (value on GPIO[1] pin directly reflected in GPI[1] register bit)
001 = Output Enable control bit 1: OSEL[1], (Refer to Figure 4 for more details.)
010 through 111 = reserved
GPI2SEL[2:0]
R/W
000b
Function of GPIO[2] pin when set to input mode by GPIO_DIR[2] register bit:
000 = General Purpose Input (value on GPIO[2] pin directly reflected in GPI[2] register bit)
001 = reserved
010 = reserved
011 = reserved
100 = reserved
101 through 111 = reserved
©2016 Integrated Device Technology, Inc.
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8T49N243 Datasheet
GPIO Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
GPI3SEL[2:0]
R/W
000b
Description
Function of GPIO[3] pin when set to input mode by GPIO_DIR[3] register bit:
000 = General Purpose Input (value on GPIO[3] pin directly reflected in GPI[3] register bit)
001 = reserved
010 = reserved
011 = reserved
100 through 111 = reserved
GPO0SEL[2:0]
R/W
000b
Function of GPIO[0] pin when set to output mode by GPIO_DIR[0] register bit:
000 = General Purpose Output (value in GPO[0] register bit driven on GPIO[0] pin
001 = reserved
010 = reserved
011 = reserved
100 = reserved
101 = reserved
110 through 111 = reserved
GPO1SEL[2:0]
R/W
000b
Function of GPIO[1] pin when set to output mode by GPIO_DIR[1] register bit:
000 = General Purpose Output (value in GPO[1] register bit driven on GPIO[1] pin
001 = Loss-of-Signal Status Flag for Input Reference 1 (FBIN) reflected on GPIO[1] pin
010 = reserved
011 = reserved
100 = reserved
101 = reserved
110 = reserved
111 = reserved
GPO2SEL[2:0]
R/W
000b
Function of GPIO[2] pin when set to output mode by GPIO_DIR[2] register bit:
000 = General Purpose Output (value in GPO[2] register bit driven on GPIO[2] pin
001 = Loss-of-Signal Status Flag for input reference 0 (CLK) reflected on GPIO[2] pin
010 = reserved
011 = reserved
100 = reserved
101 through 111 = reserved
GPO3SEL[2:0]
R/W
000b
Function of GPIO[3] pin when set to output mode by GPIO_DIR[3] register bit:
000 = General Purpose Output (value in GPO[3] register bit driven on GPIO[3] pin
001 = Loss-of-Lock Status Flag for Digital PLL reflected on GPIO[3] pin
010 = reserved
011 = reserved
100 through 111 = reserved
GPO[3:0]
R/W
0000b
Output values reflect on pin GPIO[3:0] when General-Purpose Output mode selected.
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 10: Output Driver Control Register Bit Field Locations and Descriptions
Output Driver Control Register Block Field Locations
Address (Hex)
D7
D6
D5
0039
Rsvd
003A
Rsvd
D4
D3
D2
Rsvd
1
Rsvd
003B
Rsvd
003C
Rsvd
003D
003E
Rsvd
Rsvd
1
OUTMODE1[2:0]
Rsvd
SE_MODE1
D1
D0
OUTEN[1:0]
POL_Q[1:0]
1
OUTMODE0[2:0]
Rsvd
Rsvd
SE_MODE0
Output Driver Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
OUTEN[1:0]
R/W
11b
Output enable control for clock outputs Q[1:0], nQ[1:0]:
0 = Qn is in a high-impedance state
1 = Qn is enabled as indicated in appropriate OUTMODEn[2:0] register
field
POL_Q[1:0]
R/W
00b
Polarity of clock outputs Q[1:0], nQ[1:0]:
0 = Qn is normal polarity
1 = Qn is inverted polarity
OUTMODEm[2:0]
R/W
011b
SE_MODEm
R/W
1b
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Description
Output Driver Mode of Operation for clock outputs Q[1:0], nQ[1:0]:
000 = High-impedance
001 = LVPECL
010 = LVDS
011 = LVCMOS
100 = HCSL
101 - 111 = reserved
Behavior of output pair Qm, nQm when LVCMOS operation is selected:
(Must be 0 if LVDS or LVPECL output style is selected)
0 = Qm and nQm are both the same frequency but inverted in phase
1 = Qm and nQm are both the same frequency and phase
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 11: Output Divider Control Register (Integer Portion) Bit Field Locations and Descriptions
Output Divider Control Register (Integer Portion) Block Field Locations
Address (Hex)
D7
D6
003F
D5
D4
D3
D2
D1
Rsvd
NS1_Q0[1:0]
0040
NS2_Q0[15:8]
0041
NS2_Q0[7:0]
0042
Rsvd
N_Q1[17:16]
0043
N_Q1[15:8]
0044
N_Q1[7:0]
0045
D0
Rsvd
N_FCLK[17:16]
0046
N_FCLK[15:8]
0047
N_FCLK[7:0]
0048
Rsvd
0049
Rsvd
004A
Rsvd
Output Divider Control Register (Integer Portion) Block Field Descriptions
Bit Field Name
Field Type
Default Value
NS1_Q0[1:0]
R/W
01b
NS2_Q0[15:0]
R/W
001Dh
2nd Stage Output Divider Ratio for output clock Q0, nQ0.
Actual divider ratio is 2x the value written here.
A value of 0 in this register will bypass the second stage of the divider.
N_Q1[17:0]
R/W
00057h
Integer Portion of Output Divider Ratio for output clock Q1, nQ1:
Values of 0, 1 or 2 cannot be written to this register.
Actual divider ratio is 2x the value written here.
N_FCLK[17:0]
R/W
002B8h
Integer Portion of Output Divider Ratio for output clock FCLK, nFCLK:
Values of 0, 1 or 2 cannot be written to this register.
Actual divider ratio is 2x the value written here.
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Description
1st Stage Output Divider Ratio for output clock Q0, nQ0:
00 = /5
01 = /6
10 = /4
11 = Reserved
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 12: Output Divider Control Register (Fractional Portion) Bit Field Locations and Descriptions
Output Divider Control Register (Fractional Portion) Block Field Locations
Address (Hex)
D7
D6
0057
D5
D4
D3
Rsvd
D1
D0
NFRAC_Q1[27:24]
0058
NFRAC_Q1[23:16]
0059
NFRAC_Q1[15:8]
005A
NFRAC_Q1[7:0]
005B
D2
Rsvd
NFRAC_FCLK[27:24]
005C
NFRAC_FCLK[23:16]
005D
NFRAC_FCLK[15:8]
005E
NFRAC_FCLK[7:0]
005F
Rsvd
0060
Rsvd
0061
Rsvd
0062
Rsvd
Output Divider Control Register (Fractional Portion) Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
NFRAC_Q1[27:0]
R/W
0000000h
Fractional Portion of Output Divider Ratio for output Q1, nQ1.
Actual fractional portion is 2x the value written here.
Fraction = (NFRAC_Q1 * 2) * 2-28
NFRAC_FCLK[27:0]
R/W
0000000h
Fractional Portion of Output Divider Ratio for output FCLK, nFCLK.
Actual fractional portion is 2x the value written here.
Fraction = (NFRAC_FCLK * 2) * 2 -28
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 13: Output Clock Source Control Register Bit Field Locations and Descriptions
Output Clock Source Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
0063
PLL_SYN
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
0064
Rsvd
0065
Rsvd
D1
D0
CLK_SELFCLK[1:0]
0066
Rsvd
Rsvd
Rsvd
Rsvd
0067
Rsvd
Rsvd
Rsvd
Rsvd
Output Clock Source Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
PLL_SYN
R/W
0b
Output Synchronization Control for outputs derived from PLL.
Setting this bit from 0->1 will cause the output divider(s) for the affected outputs to
be held in reset.
Setting this bit from 1->0 will release all the output divider(s) for the affected outputs
to run from the same point in time with the coarse output phase adjustment reset to
0.
CLK_SELFCLK[1:0]
R/W
00b
Clock Source selection for output pair FCLK, nFCLK: Do not select input reference
0 or 1 if that input is faster than 250MHz:
00 = PLL
01 = Input Reference 0 (CLK)
10 = Input Reference 1 (FBIN)
11 = Crystal input
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Reserved. Always write 0 to this bit location. Read values are not defined.
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November 8, 2016
8T49N243 Datasheet
Please contact IDT through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular
user configuration.
Table 14: Analog PLL Control Register Bit Field Locations and Descriptions
Analog PLL Control Register Block Field Locations
Address (Hex)
D7
D6
0068
0069
D5
D4
CPSET[2:0]
Rsvd
D3
D2
RS[1:0]
Rsvd
TDC_DIS
D1
CP[1:0]
SYN_MODE
Rsvd
006A
VCOMAN[2:0]
DBIT[4:0]
006B
001b
Rsvd
D0
WPOST
DLCNT
DBITM
Analog PLL Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
CPSET[2:0]
R/W
111b
RS[1:0]
R/W
01b
Description
Charge Pump Current Setting for Analog PLL:
000 = 110µA
001 = 220µA
010 = 330µA
011 = 440µA
100 = 550µA
101 = 660µA
110 = 770µA
111 = 880µA
Internal Loop Filter Series Resistor Setting for Analog PLL:
00 = 330
01 = 640
10 = 1.2k
11 = 1.79k
CP[1:0]
R/W
11b
Internal Loop Filter Parallel Capacitor Setting for Analog PLL:
00 = 40pF
01 = 80pF
10 = 140pF
11 = 200pF
WPOST
R/W
0b
Internal Loop Filter 2nd-Pole Setting for Analog PLL:
0 = Rpost = 497 , Cpost = 40pF
1 = Rpost = 1.58k , Cpost = 40pF
TDC_DIS
R/W
©2016 Integrated Device Technology, Inc.
0b
TDC Disable Control for PLL:
0 = TDC Enabled
1 = TDC Disabled
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November 8, 2016
8T49N243 Datasheet
Analog PLL Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
SYN_MODE
R/W
0b
Description
Frequency Synthesizer Mode Control for PLL:
0 = PLL jitter attenuates and translates one or more input references
1 = PLL synthesizes output frequencies using only the crystal as a reference
Note that the STATE[1:0] field in the Digital PLL Control Register must be set to
Force Free-run state.
DLCNT
R/W
1b
Digital Lock Count Setting for Analog PLL:
0 = Counter is a 20-bit accumulator
1 = Counter is a 16-bit accumulator
DBITM
R/W
0b
Digital Lock Manual Override Setting for Analog PLL:
0 = Automatic mode
1 = Manual mode
VCOMAN[2:0]
R/W
001b
Manual Lock Mode VCO Selection Setting for Analog PLL:
000 = VCO0
001 = VCO1
010 = VCO2
011 = VCO3
100 = VCO4
101 = VCO5
110 - 111 = Reserved
DBIT[4:0]
R/W
01011b
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Manual Mode Digital Lock Control Setting for VCO in Analog PLL.
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 15: Power Down Control Register Bit Field Locations and Descriptions
Power Down Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
006C
Rsvd
LCKMODE
DBL_DIS
006D
Rsvd
Rsvd
CLK_DIS
Rsvd
Q1_DIS
Q0_DIS
DPLL_DIS
DSM_DIS
CALRST
006E
Rsvd
006F
Rsvd
0070
1
Rsvd
Power Down Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
LCKMODE
R/W
0b
Controls the behavior of the LOL alarm deassertion:
0 = LOL alarm deasserts once PLL is locked
1 = LOL alarm deasserts once PLL is locked and output clocks are stable
DBL_DIS
R/W
0b
Controls whether crystal input frequency is doubled before being used in PLL:
0 = 2x Actual crystal frequency used
Description
1 = Actual crystal frequency used
CLK_DIS
R/W
0b
Disable Control for differential clock Input:
0 = Input is enabled
1 = Input is disabled
Qm_DIS
R/W
0b
Disable Control for Output Qm, nQm (m = 0, 1):
0 = Output Qm, nQm functions normally
1 = All logic associated with Output Qm, nQm is disabled & driver in High-Impedance
state
DPLL_DIS
R/W
0b
Disable Control for Digital PLL:
0 = Digital PLL enabled
1 = Digital PLL disabled
DSM_DIS
R/W
0b
Disable Control for Delta-Sigma Modulator for Analog PLL:
0 = DSM enabled
1 = DSM disabled
CALRST
R/W
0b
Reset Calibration Logic for Analog PLL:
0 = Calibration Logic for Analog PLL enabled
1 = Calibration Logic for Analog PLL disabled
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 16: Input Monitor Control Register Bit Field Locations and Descriptions
Input Monitor Control Register Block Field Locations
Address (Hex)
D7
D6
D5
0071
D4
D3
D2
D1
D0
Rsvd
LOS_0[16]
0072
LOS_0[15:8]
0073
LOS_0[7:0]
0074
Rsvd
LOS_1[16]
0075
LOS_1[15:8]
0076
LOS_1[7:0]
0077
Rsvd
0078
Rsvd
Input Monitor Control Register Block Field Descriptions
Bit Field Name
Field
Type
Default Value
LOS_m[16:0]
R/W
000B1h
Rsvd
R/W
-
Description
Number of input monitoring clock periods before input reference m (m = 0 (CLK),
1 (FBIN)) is considered to be missed (soft alarm). Minimum setting is 3.
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 17: Interrupt Enable Control Register Bit Field Locations and Descriptions
Interrupt Enable Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
0079
Rsvd
LOL_EN
Rsvd
Rsvd
D3
D2
Rsvd
D1
D0
LOS1_EN
LOS0_EN
Interrupt Enable Control Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
LOL_EN
R/W
0b
Interrupt Enable Control for Loss-of-Lock Interrupt Status Bit:
0 = LOL_INT register bit will not affect status of nINT output signal
1 = LOL_INT register bit will affect status of nINT output signal
LOSm_EN
R/W
0b
Interrupt Enable Control for Loss-of-Signal Interrupt Status Bit for input reference
(m = 0 (CLK), 1 (FBIN)):
0 = LOSm_INT register bit will not affect status of nINT output signal
1 = LOSm_INT register bit will affect status of nINT output signal
Rsvd
R/W
-
©2016 Integrated Device Technology, Inc.
Description
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Table 18: Factory Setting Register Bit Field Locations
Factory Setting Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
007A
D3
D2
D1
D0
Rsvd
Rsvd
Rsvd
Rsvd
27h
007B
Rsvd
Rsvd
This register contains “sticky” bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit
will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until
explicitly cleared by a write of a ‘1’ to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C).
Table 19: Interrupt Status Register Bit Field Locations and Descriptions
Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
0200
Rsvd
LOL_INT
Rsvd
Rsvd
0201
D3
D2
Rsvd
D1
D0
LOS1_INT
LOS0_INT
Rsvd
Interrupt Status Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
Description
LOL_INT
R/W1C
0b
Interrupt Status Bit for Loss-of-Lock:
0 = No Loss-of-Lock alarm flag on PLL has occurred since the last time this register bit
was cleared
1 = At least one Loss-of-Lock alarm flag on PLL has occurred since the last time this
register bit was cleared
LOSm_INT
R/W1C
0b
Interrupt Status Bit for Loss-of-Signal on input reference (m = 0 (CLK), 1 (FBIN)):
0 = No Loss-of-Signal alarm flag on input reference m has occurred since the last time
this register bit was cleared
1 = At least one Loss-of-Signal alarm flag on input reference m has occurred since the
last time this register bit was cleared
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
Table 20: General Purpose Input Status Register Bit Field Locations and Descriptions
Global Interrupt Status Register Block Field Locations
Address (Hex)
D7
D6
020C
D5
D4
Rsvd
D3
D2
D1
D0
GPI[3]
GPI[2]
GPI[1]
GPI[0]
General Purpose Input Status Register Block Field Descriptions
Description
Bit Field Name
Field Type
Default Value
GPI[3:0]
R/O
-
Shows current values on GPIO[3:0] pins that are configured as general-purpose
inputs.
Rsvd
R/W
-
Reserved. Always write 0 to this bit location. Read values are not defined.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 21: Global Interrupt Status Register Bit Field Locations and Descriptions
Global Interrupt Status Register Block Field Locations
Address (Hex)
D7
020D
D6
D5
Rsvd
D3
D2
Rsvd
020E
Rsvd
INT
Rsvd
Rsvd
Rsvd
D0
Rsvd
Rsvd
0210
D1
Rsvd
Rsvd
020F
0211
D4
Rsvd
Rsvd
0212
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Global Interrupt Status Register Block Field Descriptions
Bit Field Name
Field Type
Default Value
INT
R/O
-
Description
Device Interrupt Status:
0 = No interrupt status bits that are enabled are asserted (nINT pin released)
1 = At least one interrupt status bit that is enabled is asserted (nINT pin asserted low)
Rsvd
R/W
©2016 Integrated Device Technology, Inc.
-
Reserved. Always write 0 to this bit location. Read values are not defined.
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8T49N243 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 22: Absolute Ratings
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
OSCI
Other Input
0V to 2V
-0.5V to VCC + 0.5V
Outputs, VO (Q[1:0], nQ[1:0], FCLK, nFCLK)
-0.5V to VCCOX[a] + 0.5V
Outputs, V O (GPIO, SCLK, SDATA, nINT)
-0.5V to VCCCS + 0.5V
Outputs, IO (Q[1:0], nQ[1:0], FCLK, nFCLK)
Continuous Current
Surge Current
40mA
65mA
Outputs, IO (GPIO[3:0], SCLK, SDATA, nINT)
Continuous Current
Surge Current
8mA
13mA
Junction Temperature, TJ
125 C
Storage Temperature, TSTG
-65 C to 150 C
a. VCCOX denotes: VCCO0, VCCO1, VCCO2.
Supply Voltage Characteristics
Table 23: Power Supply DC Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core supply voltage
3.135
3.3
3.465
V
VCCA
Analog supply voltage
3.135
3.3
VCC
V
VCCCS
Control and status supply voltage
1.71
VCC
V
ICC
Core supply current[a]
39
50
mA
ICCCS
Control and status supply current [b]
3
6
mA
91
121
mA
257
340
mA
current[a]
ICCA
Analog supply
IEE
Power supply current [c]
a.
b.
c.
d.
Q[1:0], nQ[1:0] configured for
LVPECL logic levels;
outputs unloaded[d]
ICC, ICCA and ICCCS are included in I EE when output clocks configured for LVPECL logic levels.
GPIO [3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST pins are floating.
Internal dynamic switching current at maximum fOUT is included.
Outputs enabled.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 24: Power Supply DC Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VCC
Core supply voltage
2.375
2.5
2.625
V
VCCA
Analog supply voltage
2.375
2.5
VCC
V
VCCCS
Control and status supply voltage
1.71
VCC
V
ICC
Core supply current[a]
39
50
mA
3
5
mA
87
118
mA
246
325
mA
ICCCS
Control and status supply Current
ICCA
Analog supply current[a]
IEE
Power supply current [c]
a.
b.
c.
d.
[b]
Q[1:0], nQ[1:0] configured for
LVPECL logic levels;
outputs unloaded [d]
ICC, ICCA and ICCCS are included in I EE when Output Clocks configured for LVPECL logic levels.
GPIO [3:0], SDATA, SCLK, S_A1, S_A0, nINT, nWP, nRST pins are floating.
Internal dynamic switching current at maximum fOUT is included.
Outputs enabled.
Table 25: Maximum Output Supply Current, V CC = VCCCS = 3.3V ±5% or 2.5V ±5%, V EE = 0V,
TA = -40°C to 85°C
Symbol
Parameter
ICCO0[b]
Q0, nQ0
Output
supply
current
ICCO1[b]
ICCO2[b]
Test
Conditions
VCCOx
[a]
= 3.3V ±5%
VCCOx
[a]
VCCOx[a] =
1.8V±5%
= 2.5V ±5%
LVPECL
LVDS
HCSL
LVCMOS
LVPECL
LVDS
HCSL
LVCMOS
LVCMOS
Units
Outputs
unloaded[c]
41
50
41
44
35
42
36
35
30
mA
Q1, nQ1
Output
supply
current
Outputs
unloaded[c]
55
64
55
55
48
57
47
52
43
mA
FCLK,
nFCLK
Output
supply
current
Outputs
unloaded[c]
N/A
66
N/A
N/A
N/A
58
N/A
N/A
N/A
mA
a. VCCOx denotes VCCO0, VCCO1, VCCO2.
b. Internal dynamic switching current at maximum fOUT is included.
c. Outputs enabled.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
DC Electrical Characteristics
Table 26: DC Input Characteristics, VCC = VCCOX = 3.3V±5% or 2.5V±5%[a]
Symbol
Parameter
CIN
Input Capacitance[b]
RPULLUP
Input
pull-up resistor
RPULLDOWN
Input
pull-down resistor
CPD
Power dissipation
capacitance
(per output pair)
Output
Impedance
Minimum
Typical
Maximum
Units
3.5
pF
GPIO[3:0],
nRST, nWP,
SDATA, SCLK
51
k
S_A0, S_A1
51
k
LVCMOS: Q0
V CCOX = 3.465V
11.5
pF
LVCMOS: Q1,
FCLK
VCCOX = 3.465V
13
pF
LVCMOS: Q0
VCCOX = 2.625V
10.5
pF
LVCMOS: Q1,
FCLK
VCCOX = 2.625V
16
pF
LVCMOS: Q0
VCCOX = 1.89V
11
pF
LVCMOS: Q1,
FCLK
VCCOX = 1.89V
13
pF
LVDS, HCSL or
LVPECL: Q0
VCCOX = 3.465V or 2.625V
2.5
pF
LVDS, HCSL or
LVPECL: Q1,
FCLK
VCCOX = 3.465V or 2.625V
4.5
pF
VCCCS = 3.3V
26
VCCCS = 2.5V
30
VCCCS = 1.8V
42
VCCOX = 3.3V
18
VCCOX = 2.5V
22
VCCOX = 1.8V
30
GPIO[3:0]
ROUT
Test Conditions
LVCMOS:
Q[1:0], nQ[1:0],
FCLK
a. VCCOX denotes: VCCO0, VCCO1, VCCO2.
b. This specification does not apply to the OSCI or OSCO pins.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 27: LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, V EE = 0V, TA = -40°C to 85°C
Symbol
VIH
VIL
IIH
IIL
Parameter
VCCCS = 2.5V
1.7
VCCCS +0.3
V
VCCCS = 1.8V
1.4
VCCCS +0.3
V
VCCCS = 3.3V
-0.3
0.8
V
VCCCS = 2.5V
-0.3
0.6
V
VCCCS = 1.8V
-0.3
0.4
V
VCCCS = VIN = 3.465V, 2.625V, 1.89V
150
A
nRST, nWP,
SDATA, SCLK
VCCCS = VIN = 3.465V, 2.625V, 1.89V
5
A
GPIO[3:0]
VCCCS = VIN = 3.465V, 2.625V, 1.89V
1
mA
S_A1, S_A0
VCCCS = 3.465V, 2.625V, 1.89V, VIN = 0V
-5
A
nRST, nWP,
SDATA, SCLK
VCCCS = 3.465V, 2.625V, 1.89V, VIN = 0V
-150
A
GPIO[3:0]
VCCCS = 3.465V, 2.625V, 1.89V, VIN = 0V
-1
mA
VCCCS = 3.3V ±5%, IOH = -5µA
2.6
V
GPIO[3:0]
VCCCS = 3.3V ±5%, IOH = -50µA
2.6
V
SDATA,[a] SCLK,[a]
nINT[a]
VCCCS = 2.5V ±5%, IOH = -5µA
1.8
V
GPIO[3:0]
VCCCS = 2.5V ±5%, IOH = -50µA
1.8
V
VCCCS = 1.8V ±5%, IOH = -5µA
1.3
V
GPIO[3:0]
VCCCS = 1.8V ±5%, IOH = -50µA
1.3
V
SDATA,[a] SCLK,[a]
nINT[a]
VCCCS = 3.3V ±5%, 2.5V±5%, or 1.8V±5%
IOL = 5mA
0.5
V
GPIO[3:0]
VCCCS = 3.3V ±5%, 2.5V±5%, or 1.8V±5%
IOL = 5mA
0.5
V
nWP, nRST,
GPIO[3:0], SDATA,
SCLK, S_A1, S_A0
S_A1, S_A0
[a]
SDATA,[a]
nINT
VOL
Output
low
voltage
Units
V
SDATA,
nINT[a]
VOH
Maximum
VCCCS +0.3
Input
low
voltage
Output
high
voltage
Typical
2.1
nWP, nRST,
GPIO[3:0], SDATA,
SCLK, S_A1, S_A0
Input
low
current
Minimum
VCCCS = 3.3V
Input
high
voltage
Input
high
current
Test Conditions
[a]
SCLK,[a]
SCLK,[a]
a. Use of external pull-up resistors is recommended.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 28: Differential Input DC Characteristics, V CC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
150
A
IIH
Input
high current
CLK, nCLK;
FBIN, nFBIN
VCC = VIN = 3.465V or 2.625V
IIL
Input
low current
CLK, FBIN
VCC = 3.465V or 2.625V, VIN = 0V
-5
A
nCLK, nFBIN
VCC = 3.465V or 2.625V, VIN = 0V
-150
A
VPP
Peak-to-peak voltage [a]
0.15
1.3
V
VCMR
Common mode input voltage[a], [b]
VEE
VCC -1.2
V
a. VIL should not be less than -0.3V. VIH should not be higher than VCC.
b. Common mode voltage is defined as the cross-point.
Table 29: LVPECL DC Characteristics, V CC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCCOx[a] = 3.3V±5%
Test
Conditions
Minimum
Typical
VCCOx[a] = 2.5V±5%
Maximum
Minimum
Typical
Maximum
Units
VOH
Output
high voltage [b]
VCCOX - 1.3
VCCOX - 0.8
VCCOX - 1.4
VCCOX - 0.9
V
VOL
Output
low voltage[b]
VCCOX - 1.95
VCCOX - 1.75
VCCOX - 1.95
VCCOX - 1.75
V
a. VCCOx denotes VCCO0, VCCO1, VCCO2.
b. Outputs terminated with 50 to VCCOx 2V.
Table 30: LVDS DC Characteristics, V CC = 3.3V ±5% or 2.5V ±5%, V CCOX = 3.3V ±5% or 2.5V ±5%, V EE = 0V,
TA = -40°C to 85°C[a], [b]
Symbol
VOD
VOD
VOS
VOS
Parameter
Test Conditions
Minimum
Differential output voltage
Typical
200
VOD magnitude change
Offset voltage
1.1
VOS magnitude change
Maximum
Units
400
mV
50
mV
1.375
V
50
mV
a. VCCOx denotes VCCO0, VCCO1, VCCO2.
b. Terminated with 100 across Qx and nQx.
Table 31: LVCMOS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCCOx[a] = 3.3V±5%
Test
Conditions
Minimum
2.6
VOH
Output
high voltage
IOH = -8mA
VOL
Output
low voltage
IOL = 8mA
Typical
VCCOx[a] = 2.5V±5%
Maximum
Minimum
Typical
Maximum
1.8
0.5
VCCOx[a] = 1.8V ±5%
Minimum
Typical
Maximum
1.1
0.5
Units
V
0.5
V
a. VCCOx denotes VCCO0, VCCO1, VCCO2.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 32: Input Frequency Characteristics, VCC = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C
Symbol
fIN
Parameter
Input
frequency[a]
OSCI, OSCO
Test Conditions
fSCLK
Maximum
Units
10
50
MHz
Over-driving crystal input
doubler logic enabled [b]
10
62.5
MHz
Over-driving crystal input
doubler logic disabled[b]
10
125
MHz
0.008
875
MHz
0.008
8
MHz
100
400
kHz
Phase detector frequency[c]
Serial port
clock SCLK
Typical
Using a crystal
(see Table 33 for Crystal
Characteristics)
CLK, nCLK;
FBIN, nFBIN
fPD
Minimum
2
I C Operation
(slave mode)
a. For the input reference frequency, the divider values must be set for the VCO to operate within its supported range.
b. For optimal noise performance, the use of a quartz crystal is recommended. Refer to Overdriving the XTAL Interface in the Applications
Information section.
c. Pre-dividers must be used to divide the input reference frequency down to a f PD valid frequency range.
Table 33: Crystal Characteristics
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Units
50
MHz
Fundamental
Frequency
10
Equivalent Series Resistance (ESR)
15
Load Capacitance (CL)
12
Frequency stability (total)
©2016 Integrated Device Technology, Inc.
Maximum
-100
37
30
pF
100
ppm
November 8, 2016
8T49N243 Datasheet
AC Electrical Characteristics
Table 34: AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%
(1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C[a], [b]
Symbol
fVCO
fOUT
Parameter
Test Conditions
Maximum
Units
3000
4000
MHz
Integer divide ratio
0.008
1000
MHz
Q0, Q1, FCLK outputs
non-integer divide
0.008
400
MHz
0.008
250
MHz
VCO operating frequency
Output
frequency
LVPECL, LVDS, HCSL
LVCMOS
LVPECL
LVDS
tR / tF
Output
rise and fall times
HCSL
LVCMOS[c], [d]
LVPECL
320
520
ps
20% to 80%, VCCOx = 3.3V
160
320
ps
20% to 80%, VCCOx = 2.5V
200
400
ps
20% to 80%
280
470
ps
20% to 80%, VCCOx = 3.3V
240
310
ps
20% to 80%, VCCOx = 2.5V
260
330
ps
20% to 80%, VCCOx = 1.8V
350
550
ps
5
V/ns
Measured on differential
waveform, ±150mV from
center, V CCOx = 2.5V
0.5
4
V/ns
Measured on differential
waveform, ±150mV from
center, VCCOx = 3.3V
0.5
5
V/ns
Measured on differential
waveform, ±150mV from
center, V CCOx = 2.5V,
fOUT 156.25MHz
1.5
5
V/ns
Measured on differential
waveform, ±150mV from
center, VCCOx = 3.3V,
fOUT 156.25MHz
2.5
6.5
V/ns
LVPECL,
LVDS, HCSL
fOUT
666.667MHz
45
50
55
%
LVPECL,
LVDS, HCSL
fOUT > 666.667MHz
40
50
60
%
40
50
60
%
Output
|slew rate
Output
duty cycle[e]
20% to 80%
1
HCSL
odc
LVCMOS
SPO
SPO
Static phase offset[f]
Default configuration
Static phase offset variation [f]
Default configuration
©2016 Integrated Device Technology, Inc.
Typical
Measured on differential
waveform, ±150mV from
center
LVDS
SR
Minimum
38
431
-200
ps
200
ps
November 8, 2016
8T49N243 Datasheet
Table 34: AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%
(1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C[a], [b] (Cont.)
Symbol
Parameter
Test Conditions
Q1, nQ1
-124
dBc/Hz
Q0, nQ0
-148
dBc/Hz
Q1, nQ1
-141
dBc/Hz
Q0, nQ0
-157
dBc/Hz
Q1, nQ1
-151
dBc/Hz
Q0, nQ0
-165
dBc/Hz
Q1, nQ1
-158
dBc/Hz
Q0, nQ0
-165
dBc/Hz
Q1, nQ1
-161
dBc/Hz
>800kHz
Default configuration
-64.5
dBc
Internal
OTP startup
From V CC >80% to
first output clock edge
110
10kHz
100kHz
SSB(1M)
1MHz
SSB(5M)
5MHz
Spurious limit at offset
tstartup
Startup time[g]
Units
dBc/Hz
SSB(10k)
[f]
Maximum
-131
1kHz
Single sideband
phase noise[f]
Typical
Q0, nQ0
SSB(1k)
SSB(100k)
Minimum
150
ms
a. VCCOx denotes VCCO0, VCCO1, VCCO2.
b. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
c. Appropriate SE_MODE bit must be configured to select phase-aligned or phase-inverted operation.
d. All Q and nQ outputs in phase-inverted operation.
e. Characterized in PLL mode. Duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device.
f. Characterized with default configuration.
g. This parameter is guaranteed by design.
©2016 Integrated Device Technology, Inc.
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November 8, 2016
8T49N243 Datasheet
Table 35: HCSL AC Characteristics, V CC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%,
TA = -40°C to 85°C[a], [b]
Symbol
Parameter
Test Conditions
margin[c], [d]
VRB
Ring-back voltage
tSTABLE
Time before VRB is allowed[c], [d]
Minimum
-100
Maximum
Units
100
mV
500
[e], [f]
VMAX
Absolute max. output voltage
VMIN
Absolute min. output voltage [e], [g]
-300
VCROSS
Absolute crossing voltage[h], [i]
200
VCROSS
Typical
ps
1150
Total variation of VCROSS over all
edges[h], [j]
mV
mV
500
mV
140
mV
a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
b. VCCOx denotes VCCO0, VCCO1, VCCO2.
c. Measurement taken from differential waveform.
d. TSTABLE is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is allowed
to drop back into the VRB ±100mV differential range.
e.
f.
g.
h.
i.
Measurement taken from single ended waveform.
Defined as the maximum instantaneous voltage including overshoot.
Defined as the minimum instantaneous voltage including undershoot.
Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
j. Defined as the total variation of all crossing voltages of rising Qx and falling nQx, This is the maximum allowed variance in V CROSS for any
particular system.
Table 36: Typical RMS Phase Jitter, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5%
(1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C[a]
Symbol
tjit( )
Parameter
RMS phase jitter [b] (Random)
Test Conditions
Typical
Units
Q0
Default configuration
375
fs
Q1
Default configuration
382
fs
a. VCCOx denotes VCCO0, VCCO1, VCCO2.
b. It is recommended to use IDT’s Timing Commander software to program the device for optimal jitter performance.
©2016 Integrated Device Technology, Inc.
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8T49N243 Datasheet
Typical Phase Noise (Q0, default configuration)
Figure 6: Typical Phase Noise Plot
Offset Frequency (Hz)
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November 8, 2016
8T49N243 Datasheet
Typical Phase Noise (Q1, default configuration)
Figure 7: Typical Phase Noise Plot
Offset Frequency (Hz)
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November 8, 2016
8T49N243 Datasheet
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
CLK/nCLK Input
For applications not requiring the use of one or more reference clock inputs, both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k resistor can be tied from CLK to ground. It is recommended that CLK, nCLK not be driven with active signals
when not selected.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both OSCI and OSCO can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from OSCI to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k
resistor can be used.
Outputs:
LVPECL Outputs
Any unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVDS Outputs
Any unused LVDS output pair can be either left floating or terminated with 100
attached.
across. If they are left floating there should be no trace
LVCMOS Outputs
Any LVCMOS output can be left floating if unused. There should be no trace attached.
HCSL Outputs
All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
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8T49N243 Datasheet
Overdriving the XTAL Interface
The OSCI input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The OSCO
pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than
0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal
interference with the power rail and to reduce internal noise. Figure 8 shows an example of the interface diagram for a high speed 3.3V
LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the
transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of
two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100 . This
can also be accomplished by removing R1 and changing R2 to 50 . The values of the resistors can be increased to reduce the loading for a
slower and weaker LVCMOS driver. Figure 9 shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL
termination with one side of the driver feeding the OSCI input. It is recommended that all components in the schematics be placed in the
layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are
characterized and guaranteed by using a quartz crystal as the input.
Figure 8: General Diagram for LVCMOS Driver to XTAL Input Interface
37'3
:''
6
6S
67
'
>S!
37' *
>S!6S6W
6
0:'137C(VMZIV
Figure 9: General Diagram for LVPECL Driver to XTAL Input Interface
37'3
'
>S!
37' *
>S!
0:4)'0C(VMZIV
6
6
6
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8T49N243 Datasheet
Wiring the Differential Input to Accept Single-Ended Levels
Figure 10 shows how a differential input can be wired to accept single ended levels. The reference voltage V REF = VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to
the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V REF in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the
driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate
the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most
50 applications, R3 and R4 can be 100 . The values of the resistors can be increased to reduce the loading for slower and weaker
LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the
differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower
differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL
cannot be less than -0.3V and V IH cannot be more than V CC + 0.3V. Suggest edge rate faster than 1V/ns. Though some of the recommended
components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet
specifications are characterized and guaranteed by using a differential signal.
Figure 10: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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8T49N243 Datasheet
3.3V Differential Clock Input Interface
CLK/nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input
requirements. Figure 11 to Figure 15 show interface examples for the CLK, nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 11, the input
termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination
recommendation.
Figure 11: CLK/ nCLK Input Driven by an IDT
Figure 12: CLK/ nCLK Input Driven by a
3.3V LVPECL Driver
Open Emitter LVHSTL Driver
3.3V
1.8V
Zo = 50
CLK
Zo = 50
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50
R2
50
Figure 13: CLK/ nCLK Input Driven by a
3.3V HCSL Driver
3.3V
Figure 14: CLK/ nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 15: CLK/ nCLK Input Driven by a
3.3V LVDS Driver
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8T49N243 Datasheet
2.5V Differential Clock Input Interface
CLK/nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V SWING and VOH must meet the VPP and VCMR input
requirements. Figure 16 to Figure 20 show interface examples for the CLK/nCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 16, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination recommendation.
Figure 16: CLK/ nCLK Input Driven by an IDT
Open Emitter LVHSTL Driver
Figure 17: CLK/ nCLK Input Driven by a
2.5V LVPECL Driver
2.5V
1.8V
Zo = 50
CLK
Zo = 50
nCLK
LVHSTL
IDT Open Emitter
LVHSTL Driver
R1
50
R2
50
Differential
Input
Figure 18: CLK/ nCLK Input Driven by a
2.5V HCSL Driver
Figure 19: CLK/ nCLK Input Driven by a
2.5V LVPECL Driver
Figure 20: CLK/ nCLK Input Driven by a
2.5V LVDS Driver
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8T49N243 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (Z T) is between 90 and 132 . The actual value should
be selected to match the differential impedance (Z 0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel
resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the
components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant
devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 21 can
be used with either type of output structure. Figure 22, which can also be used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are
LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.
Figure 21: Standard LVDS Termination
LVDS
Driver
ZO
ZT
LVDS
Receiver
ZT
Figure 22: Optional LVDS Termination
LVDS
Driver
ZO
Z
2
ZT
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Z
2
LVDS
Receiver
November 8, 2016
8T49N243 Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended
only as guidelines.
The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal distortion. Figure 23 and Figure 24 show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to
guarantee compatibility across all printed circuit and clock component process variations.
Figure 23: 3.3V LVPECL Output Termination
Figure 24: 3.3V LVPECL Output Termination
3.3V
R3
125
3.3V
R4
125
Zo = 50
3.3V
+
_
Input
Zo = 50
R1
84
R2
84
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8T49N243 Datasheet
Termination for 2.5V LVPECL Outputs
Figure 25 and Figure 27 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to
VCCO 2V. For VCCO = 2.5V, the VCCO 2V is very close to ground level. The R3 in Figure 27 can be eliminated and the termination is shown
in Figure 26.
Figure 25: 2.5V LVPECL Driver Termination Example
2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50
+
50
–
2.5V LVPECL Driver
R2
62.5
R4
62.5
Figure 26: 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50
+
50
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 27: 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50
+
50
–
2.5V LVPECL Driver
R1
50
R2
50
R3
18
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8T49N243 Datasheet
HCSL Recommended Termination
Figure 28 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This termination
is the standard for PCI Express and HCSL output types. All traces should be 50 impedance single-ended or 100 differential.
Figure 28: Recommended Source Termination (where the driver and receiver will be on separate PCBs)
0.5" Max
0- 0.2"
1-14"
0.5 - 3.5"
L1
L2
L4
L5
L1
L2
L4
L5
0-0.2"
L3
L3
Figure 29 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point connection
contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line reflections will be
minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections. The optional resistor can
range from 0 to 33 . All traces should be 50 impedance single-ended or 100 differential.
Figure 29: Recommended Termination (where a point-to-point connection can be used)
0.5" Max
L1
L1
0 to 33
0 to 33
0-18"
0-0.2"
L2
L3
L2
L3
49.9 +/- 5%
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8T49N243 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the
Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,
as shown in Figure 30. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the
exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB
between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder
joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be
connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific and
dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or
testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array
of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended
that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking
inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land.
Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations
are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s
Thermally/ Electrically Enhance Lead frame Base Package, Amkor Technology.
Figure 30: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Schematic and Layout Information
Schematics for the 8T49N243 can be found on IDT.com. Please search for the 8T49N243 device and click on the link for evaluation board. The
evaluation board user guide includes schematic and layout information.
Crystal Recommendation
This device was validated using FOX 277LF series through-hole crystals including Part # 277LF-40-18 (40MHz). If a surface mount crystal is
desired, we recommend FOX Part #603-40-48 (40MHz).
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8T49N243 Datasheet
Power Dissipation and Thermal Considerations
The 8T49N243 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is
highly programmable with a broad range of features and functionality, the power consumption will vary as these features and functions are
enabled.
The 8T49N243 device is designed and characterized to operate within the ambient industrial temperature range of -40°C to 85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.
The power calculation examples below are generated using maximum ambient temperature and supply voltage. For many applications, the
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your
own specific configuration.
Power Domains
The 8T49N243 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all
power supply pins must still be connected to a valid supply voltage). Figure 31 below indicates the individual domains and the associated
power pins.
Figure 31: Power Domains
Power Consumption Calculation
Determining total power consumption involves several steps:
1.
Determine the power consumption using maximum current values for core and analog voltage supplies from Table 23 and Table 24.
2.
Determine the nominal power consumption of each enabled output path which consists of:
3.
a.
A base amount of power that is independent of operating frequency, as shown in Table 38 through Table 46 (depending on the
chosen output protocol).
b.
A variable amount of power that is related to the output frequency. This can be determined by multiplying the output frequency by
the FQ_Factor shown in Table 38 through Table 46.
All of the above totals are summed.
Thermal Considerations
Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the
device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors
that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow or via conduction
into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 37 below.
Please contact IDT for assistance in calculating results under other scenarios.
Table 37: Thermal Resistance
JA
for 40-Lead VFQFN, Forced Convection[a]
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
26.3°C/W
23.2°C/W
21.7°C/W
a. NOTE: Assumes 5x5 grid of thermal vias under ePAD area for thermal conduction.
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8T49N243 Datasheet
Current Consumption Data and Equations
Table 42: 2.5V LVPECL Output Calculation Table
Table 38: 3.3V LVPECL Output Calculation Table
Output
FQ_Factor (mA/MHz)
Base_Current (mA)
Output
FQ_Factor (mA/MHz)
Base_Current (mA)
Q0
0.00660
32.9
Q0
0.00483
27.6
Q1
0.01088
44.4
Q1
0.00865
38.3
Table 39: 3.3V HCSL Output Calculation Table
Table 43: 2.5V HCSL Output Calculation Table
Output
FQ_Factor (mA/MHz)
Base_Current (mA)
Output
FQ_Factor (mA/MHz)
Base_Current (mA)
Q0
0.00647
33.5
Q0
0.00425
27.7
Q1
0.01050
44.7
Q1
0.00827
38.5
Table 40: 3.3V LVDS Output Calculation Table
Table 44: 2.5V LVDS Output Calculation Table
Output
FQ_Factor (mA/MHz)
Base_Current (mA)
Output
FQ_Factor (mA/MHz)
Base_Current (mA)
Q0
0.00716
41.9
Q0
0.00483
36.0
0.01145
52.8
0.00906
46.3
Q1
FCLK
Q1
FCLK
Table 41: 3.3V LVCMOS Output Calculation Table
Table 45: 2.5V LVCMOS Output Calculation Table
Output
Base_Current (mA)
Output
Base_Current (mA)
Q0
31.3
Q0
25.8
Q1
42.1
Q1
36.0
Table 46: 1.8V LVCMOS Output Calculation Table
©2016 Integrated Device Technology, Inc.
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Output
Base_Current (mA)
Q0
22.8
Q1
33.1
November 8, 2016
8T49N243 Datasheet
Applying the values to the following equation will yield output current by frequency:
Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base_Current
where:
Qx Current is the specific output current according to output type and frequency
FQ_Factor is used for calculating current increase due to output frequency
Base_Current is the base current for each output path independent of output frequency
The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following
equation:
TJ = T A + (
JA
* Pdtotal)
where:
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
JA
is the thermal resistance value from Table 37, dependent on ambient airflow (°C/W)
Pdtotal is the total power dissipation of the 8T49N243 under usage conditions, including power dissipated due to loading (W).
Note that the power dissipation per output pair due to loading is assumed to be 27.95mW for LVPECL outputs and 44.5mW for HCSL outputs.
When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and
trace length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 26) and output frequency:
PdOUT = CPD * FOUT * VCCO2
where:
PdOUT is the power dissipation of the output (W)
CPD is the power dissipation capacitance (F)
FOUT is the output frequency of the selected output (MHz)
VCCO is the voltage supplied to the appropriate output (V)
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8T49N243 Datasheet
Power Calculations Example
Table 47: Default Configuration (3.3V Core Voltage)
Output
Output Type
Frequency (MHz)
VCCO
Q0
LVCMOS
10
3.3V
Q1
LVCMOS
20
3.3V
FCLK
LVDS
2.5
3.3V
Core supply current + control and status supply current = ICC + ICCCS = 56mA (max)
Analog Supply Current, ICCA = 121mA (max)
Output supply current:
Q0 current = 31.3mA
Q1 current = 42.1mA
Q2 current = 2.5 * 0.01145 + 52.8 = 52.8mA
Total output supply current = 126.2mA
Total device current: 56mA + 121mA + 126.2mA = 303.2mA
Total device power = 3.465V * 303.2mA = 1050.6mW
Power dissipated through output loading:
LVCMOS = 4.5mW
11.5pF * 10MHz * (3.465V)2 * 1 output pair = 1.38mW
13pF * 20MHz * (3.465)2 * 1 output pair = 3.12mW
LVDS = already accounted for in device power
Total Power = 1050.6mW + 4.5mW = 1055.1mW= 1.06W
With an ambient temperature of 85°C, and no air flow, the junction temperature is:
TJ = 85°C + 26.3°C/W *1.06W = 112.9°C
This is below the limit of 125°C.
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8T49N243 Datasheet
Package Dimensions
Figure 32: 40-Lead VFQFN NL Package Outline
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8T49N243 Datasheet
Figure 33: 40 Lead VFQFN NL Package Outline, continued
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8T49N243 Datasheet
Marking Diagram
1. Line 1 and 2: part number.
2. Line 3:
“#”: stepping
“YYWW”: the last two digits of the year and week that the part was assembled
“$”: mark code
IDT8T49N24
3NLGI
#YYWW$
LOT C00
Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8T49N243NLGI
IDT8T49N243NLGI
40 Lead VFQFN, Lead-Free
Tray
-40 C to +85 C
8T49N243NLGI8
IDT8T49N243NLGI
40 Lead VFQFN, Lead-Free
Tape & Reel
-40 C to +85 C
Revision History
Revision Date
November 8, 2016
Description of Change
This is the first release of the 8T49N243 Final datasheet.
Corporate Headquarters
Sales
Tech Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
www.idt.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
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