FemtoClock® NG Octal Universal
Frequency Translator
8T49N281
Datasheet
Description
Features
The 8T49N281 has a fractional-feedback PLL that can be used as a
jitter attenuator or frequency translator. It is equipped with six integer
and two fractional output dividers, allowing the generation of up to 8
different output frequencies, ranging from 8kHz to 1GHz. Three of
these frequencies are completely independent of each other and the
inputs. The other five are related frequencies. The eight outputs may
select among LVPECL, LVDS or LVCMOS output levels.
•
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
•
Two differential outputs meet jitter limits for 100G Ethernet and
STM-256/OC-768
•
•
•
•
•
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS). It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
Initial holdover accuracy of ±50ppb
Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
Operates from a 10MHz to 40MHz fundamental-mode crystal
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I2C interface. It also supports
2
I C master capability to allow the register configuration to be read
from an external EEPROM.
Clock input monitoring, including support for gapped clocks
•
•
•
•
The PLL has a register-selectable loop bandwidth from 0.5Hz to
512Hz.
Auto and manual input clock selection with hitless switching
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
•
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
Accepts frequencies ranging from 8kHz up to 875MHz
•
Generates eight LVPECL /LVDS or sixteen LVCMOS output
clocks
•
•
The 8T49N281 supports holdover with an initial accuracy of ±50ppB
from the point where the loss of all applicable input reference(s) has
been detected. It maintains a historical average operating point that
may be returned to in holdover at a limited phase slope.
All outputs 666.667MHz
40
50
60
%
fOUT 666.667MHz
45
50
55
%
40
50
60
%
40
50
60
%
fOUT > 666.667MHz
LVCMOS
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8T49N281 Datasheet
Symbol
Parameter
Test Conditions
Minimum
Initial Frequency Offset
Switchover or Entering / Leaving
Holdover State; NOTE 8, 13
-50
Output Phase Change in Fully
Hitless Switching
Switchover or Entering / Leaving
Holdover State; NOTE 10, 13
5
ns
1kHz
122.88MHz Output
-120
dBc/Hz
10kHz
122.88MHz Output
-128
dBc/Hz
100kHz
122.88MHz Output
-136
dBc/Hz
1MHz
122.88MHz Output
-147
dBc/Hz
10MHz
122.88MHz Output
-153
dBc/Hz
>30MHz
122.88MHz Output
-154
dBc/Hz
>800kHz
122.88MHz output; NOTE 11
-83
dBc
from VCC >80% to First Output
Clock Edge
110
150
ms
from VCC >80% to First Output
Clock Edge (0 retries). I2C
Frequency = 100kHz
150
200
ms
from VCC >80% to First Output
Clock Edge (0 retries). I2C
Frequency = 400kHz
130
150
ms
from VCC >80% to First Output
Clock Edge (31 retries). I2C
Frequency = 100kHz
925
1200
ms
from VCC >80% to First Output
Clock Edge (31 retries). I2C
Frequency = 400kHz
360
500
ms
SSB(1k)
SSB(10k)
SSB(100k)
SSB(1M)
Single Sideband
Phase Noise;
NOTE 9
SSB(10M)
SSB(30M)
Spurious Limit at
Offset
Internal OTP
Startup;
NOTE 13
tstartup
Startup Time
External
EEPROM
Startup;
NOTE 12, 13
Typical
Maximum
Units
50
ppb
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: This parameter is guaranteed by characterization. Not tested in production.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measured at the output differential cross points.
NOTE 4: Measured at VCCOx/2 of the rising edge. All Qx and nQx outputs phase-aligned.
NOTE 5: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions running off the same clock
source.
NOTE 6: Appropriate SE_MODE bit must be set to enable phase-aligned operation.
NOTE 7: Characterized in synthesizer mode. Duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the
device.
NOTE 8: Tested in fast-lock operation after >20 minutes of locked operation to ensure holdover averaging logic is stable.
NOTE 9: Characterized with 8T49N281B-901 units (synthesizer mode).
NOTE 10: Device programmed with SWMODEn = 0 (absorbs phase differences).
NOTE 11: Tested with all outputs operating at 122.88MHz.
NOTE 12: Assuming a clear I2C bus.
NOTE 13: This parameter is guaranteed by design.
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8T49N281 Datasheet
Table 12A. Typical RMS Phase Jitter (Synthesizer Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or
1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C
Symbol
Test Conditions
LVPECL
LVDS
LVCMOSNOTE 6
Units
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz; NOTE
1
265
286
279
fs
fOUT = 156.25MHz,
Integration Range: 12kHz - 20MHz; NOTE
2
268
276
280
fs
fOUT = 622.08MHz,
Integration Range: 12kHz - 20MHz; NOTE
3
259
225
N/A
(NOTE 5)
fs
Q2, Q3 Integer;
NOTE 1
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
299
310
313
fs
Q2, Q3
Fractional;
NOTE 4
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
277
285
279
fs
Q4, Q5, Q6, Q7;
NOTE 1
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
284
298
293
fs
Parameter
Q0, Q1
tjit()
RMS Phase
Jitter
(Random)
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively.
NOTE: All outputs configured for the specific output type, as shown in the table.
NOTE 1: Characterized with 8T49N281B-901.
NOTE 2: Characterized with 8T49N281B-902.
NOTE 3: Characterized with 8T49N281B-903.
NOTE 4: Characterized with 8T49N281B-900.
NOTE 5: This frequency is not supported for LVCMOS operation.
NOTE 6: Qx and nQx are 180° out of phase.
Table 12B. Typical RMS Phase Jitter (Jitter Attenuator Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5%
or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C
Symbol
Test Conditions
LVPECL
LVDS
LVCMOSNOTE 6
Units
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz; NOTE
1
266
287
279
fs
fOUT = 156.25MHz,
Integration Range: 12kHz - 20MHz; NOTE
2
270
263
280
fs
fOUT = 622.08MHz,
Integration Range: 12kHz - 20MHz; NOTE
3
209
186
N/A
(NOTE 5)
fs
Q2, Q3 Integer;
NOTE 1
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
300
311
313
fs
Q2, Q3
Fractional;
NOTE 4
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
277
284
280
fs
Q4, Q5, Q6, Q7;
NOTE 1
fOUT = 122.88MHz,
Integration Range: 12kHz - 20MHz
284
298
293
fs
Parameter
Q0, Q1
tjit()
RMS Phase
Jitter
(Random)
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Measured using a Rohde & Schwarz SMA100A as the input source.
NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively.
NOTE: All outputs configured for the specific output type, as shown in the table.
NOTE 1: Characterized with 8T49N281B-905.
NOTE 2: Characterized with 8T49N281B-906.
NOTE 3: Characterized with 8T49N281B-907.
NOTE 4: Characterized with 8T49N281B-904.
NOTE 5: This frequency is not supported for LVCMOS operation.
NOTE 6: Qx and nQx are 180° out of phase.
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8T49N281 Datasheet
Table 13A. PCI Express Jitter Specifications, VCC = VCCOx = 3.3V ±5%, TA = -40°C to 85°C
Typical
Maximum
PCIe Industry
Specification
Units
ƒ = 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
8
30
86
ps
Phase Jitter
RMS;
NOTE 2, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
High Band: 1.5MHz - Nyquist (clock
frequency/2)
0.5
2
3.10
ps
Phase Jitter
tREFCLK_LF_RMS
RMS;
(PCIe Gen 2)
NOTE 2, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
Low Band: 10kHz - 1.5MHz
0.04
0.2
3.0
ps
ƒ = 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
0.1
0.4
0.8
ps
Symbol
Parameter
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4, 5
tREFCLK_HF_RM
S (PCIe Gen 2)
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4, 5
Test Conditions
Minimum
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
NOTE 5: Outputs configured for LVPECL mode. Fox 277LF-40-18 crystal used with doubler logic enabled.
Table 13B. PCI Express Jitter Specifications, VCC = VCCOx = 2.5V ±5%, TA = -40°C to 85°C
Typical
Maximum
PCIe Industry
Specification
Units
ƒ = 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
12
65
86
ps
Phase Jitter
RMS;
NOTE 2, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
High Band: 1.5MHz - Nyquist (clock
frequency/2)
0.8
3.10
3.10
ps
tREFCLK_LF_RMS
(PCIe Gen 2)
Phase Jitter
RMS;
NOTE 2, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
Low Band: 10kHz - 1.5MHz
0.05
0.4
3.0
ps
tREFCLK_RMS
(PCIe Gen 3)
Phase Jitter
RMS;
NOTE 3, 4, 5
ƒ = 100MHz, 40MHz Crystal Input,
Evaluation Band: 0Hz - Nyquist (clock
frequency/2)
0.2
0.8
0.8
ps
Symbol
Parameter
tj
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4, 5
tREFCLK_HF_RMS
(PCIe Gen 2)
Test Conditions
Minimum
NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
NOTE 5: Outputs configured for LVPECL mode. Fox 277LF-40-18 crystal used with doubler logic enabled.
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8T49N281 Datasheet
Noise Power (dBc/Hz)
Typical Phase Noise at 156.25MHz
Offset Frequency (Hz)
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8T49N281 Datasheet
Applications Information
Overdriving the XTAL Interface
The OSCI input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
OSCO pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 5A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 5B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the OSCI input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
OSCO
VCC
R1
100
Ro
C1
Zo = 50Ω
RS
OSCI
0.1μF
Zo = Ro + Rs
R2
100
LVCMOS_Driver
Figure 5A. General Diagram for LVCMOS Driver to XTAL Input Interface
OSCO
C2
Zo = 50Ω
OSCI
0.1μF
Zo = 50Ω
LVPECL_Driver
R1
50
R2
50
R3
50
Figure 5B. General Diagram for LVPECL Driver to XTAL Input Interface
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8T49N281 Datasheet
Wiring the Differential Input to Accept Single-Ended Levels
Figure 6 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 6. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
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8T49N281 Datasheet
3.3V Differential Clock Input Interface
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 7A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
CLKx/nCLKx accepts LVDS, LVHSTL, LVPECL, HCSL and other
differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figure 7A to Figure 7E show interface
examples for the CLKx/nCLKx input driven by the most common
driver types. The input interfaces suggested here are examples only.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
IDT
LVHSTL Driver
R1
50Ω
R2
50Ω
Figure 7A. CLKx/nCLKx Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 7D. CLKx/nCLKx Input Driven by a
3.3V LVPECL Driver
Figure 7B. CLKx/nCLKx Input Driven by a
3.3V LVPECL Driver
Figure 7E. CLKx/nCLKx Input Driven by a
3.3V LVDS Driver
3.3V
3.3V
*R3
CLK
nCLK
HCSL
*R4
Differential
Input
Figure 7C. CLKx/nCLKx Input Driven by a
3.3V HCSL Driver
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8T49N281 Datasheet
2.5V Differential Clock Input Interface
CLKx/nCLKx accepts LVDS, LVHSTL, LVPECL and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figure 8A to Figure 8D show interface examples for
the CLKx/nCLKx input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 8A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
2.5V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
LVHSTL
IDT Open Emitter
LVHSTL Driver
R1
50Ω
R2
50Ω
Differential
Input
Figure 8A. CLKx/nCLKx Input Driven by an IDT
Open Emitter LVHSTL Driver
Figure 8C. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 8B. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 8D. CLKx/nCLKx Input Driven by a
2.5V LVDS Driver
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8T49N281 Datasheet
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLKx/nCLKx Input
LVPECL Outputs
For applications not requiring the use one or more reference clock
inputs, both CLKx and nCLKx can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
CLKx to ground. It is recommended that CLKx, nCLKx not be driven
with active signals when not enabled for use.
Any unused LVPECL output pairs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or terminated.
LVDS Outputs
Any unused LVDS output pairs can be either left floating or
terminated with 100 across. If they are left floating there should be
no trace attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
LVCMOS Outputs
Any LVCMOS output can be left floating if unused. There should be
no trace attached.
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 9A can be used
with either type of output structure. Figure 9B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
ZT
LVDS
Receiver
Figure 9A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 9B. Optional Termination
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8T49N281 Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
designed to drive 50 transmission lines. Matched impedance
techniques should be used to maximize operating frequency and
minimize signal distortion. Figure 10A and Figure 10B show two
different layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended that
the board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
The differential outputs generate ECL/LVPECL compatible outputs.
Therefore, terminating resistors (DC current path to ground) or
current sources must be used for functionality. These outputs are
R3
125Ω
3.3V
R4
125Ω
3.3V
3.3V
Zo = 50Ω
+
_
Input
Zo = 50Ω
R1
84Ω
Figure 10A. 3.3V LVPECL Output Termination
©2019 Integrated Device Technology, Inc.
R2
84Ω
Figure 10B. 3.3V LVPECL Output Termination
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8T49N281 Datasheet
Termination for 2.5V LVPECL Outputs
level. The R3 in Figure 11C can be eliminated and the termination is
shown in Figure 11B.
Figure 11A and Figure 11C show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground
2.5V
VCCO = 2.5V
2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50Ω
+
50Ω
+
50Ω
–
50Ω
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 11A. 2.5V LVPECL Driver Termination Example
Figure 11C. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 11B. 2.5V LVPECL Driver Termination Example
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8T49N281 Datasheet
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 12. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Lead frame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 12. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
Schematic and Layout Information
Schematics for 8T49N281I can be found on IDT.com. Please search
for the 8T49N281 device and click on the link for evaluation board
schematics.
Crystal Recommendation
This device was validated using FOX 277LF series through-hole
crystals including part #277LF-40-18 (40MHz) and 277LF-38.88-2
(38.88MHz). If a surface mount crystal is desired, we recommend
FOX Part #603-40-48 (40MHz) or 603-38.88-7 (38.88MHz).
I2C Serial EEPROM Recommendation
The 8T49N281 was designed to operate with most standard I2C
serial EEPROMs of 256 bytes or larger. Atmel AT24C04C was used
during device characterization and is recommended for use. Please
contact IDT for review of any other I2C EEPROM’s compatibility with
the 8T49N281.
©2019 Integrated Device Technology, Inc.
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8T49N281 Datasheet
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The block diagram below shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs
are modeled as well as the phase interpolator in the receiver. These
transfer functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht s = H3 s H1 s – H2 s
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y s = X s H3 s H1 s – H2 s
PCIe Gen 2A Magnitude of Transfer Function
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
PCI Express Common Clock Architecture
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist (e.g
for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is
reported in peak-peak.
PCIe Gen 2B Magnitude of Transfer Function
For PCI Express Gen 3, one transfer function is defined and the
evaluation is performed over the entire spectrum. The transfer
function parameters are different from Gen 1 and the jitter result is
reported in RMS.
PCIe Gen 1 Magnitude of Transfer Function
For PCI Express Gen 2, two transfer functions are defined with 2
evaluation ranges and the final jitter number is reported in rms. The
two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz
(Low Band) and 1.5MHz – Nyquist (High Band). The plots show the
individual transfer functions as well as the overall transfer function Ht.
©2019 Integrated Device Technology, Inc.
PCIe Gen 3 Magnitude of Transfer Function
For a more thorough overview of PCI Express jitter analysis
methodology, please refer to IDT Application Note PCI Express
Reference Clock Requirements.
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January 17, 2019
8T49N281 Datasheet
Power Dissipation and Thermal Considerations
The 8T49N281 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is
highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions
is enabled.
The 8T49N281 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The
ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,
such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable
junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.
The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the
power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your
own specific configuration.
Power Domains
The 8T49N281 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all
power supply pins must still be connected to a valid supply voltage). Figure 13 below indicates the individual domains and the associated power
pins.
Output Divider / Buffer Q0 (VCCO0 )
CLK Input &
Divider Block
(Core VCC)
Analog & Digital PLL
(V CCA and Core VCC)
Output Divider / Buffer Q1 (VCCO1 )
Output Divider / Buffer Q2 (VCCO2 )
Output Divider / Buffer Q3 (VCCO3 )
Output Divider / Buffer Q4 (VCCO4 )
Output Divider / Buffer Q5 (VCCO5 )
Output Divider / Buffer Q6 (VCCO6 )
Output Divider / Buffer Q7 (VCCO7 )
Figure 13. 8T49N281 Power Domains
For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use
a second structure and Q[4:7] use a 3rd structure. Power consumption data will vary slightly depending on the structure used as shown in the
appropriate tables below.
Power Consumption Calculation
Determining total power consumption involves several steps:
1.
Determine the power consumption using maximum current values for core and analog voltage supplies from Table 7A and Table 7B.
2.
Determine the nominal power consumption of each enabled output path.
3.
a.
This consists of a base amount of power that is independent of operating frequency, as shown in Table 15A through Table 15G
(depending on the chosen output protocol).
b.
Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output
frequency by the FQ_Factor shown in Table 15A through Table 15G.
All of the above totals are then summed.
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8T49N281 Datasheet
Thermal Considerations
Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device
under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can
affect this. The thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via conduction into the
PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 14 below. Please contact
IDT for assistance in calculating results under other scenarios.
Table 14. Thermal Resistance JA for 56-Lead VFQFN, Forced Convection
JA by Velocity
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
16.0°C/W
12.14°C/W
11.02°C/W
Current Consumption Data and Equations
Table 15A. 3.3V LVPECL Output Calculation Table
LVPECL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
Base_Current (mA)
0.00624
40.3
0.01445
63.6
0.00609
42.2
Table 15D. 2.5V LVDS Output Calculation Table
LVDS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
Base_Current (mA)
0.00409
33.0
0.01179
56.4
0.00369
35.4
LVCMOS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
Base_Current (mA)
0.00664
49.6
0.01479
73.0
0.00646
51.5
©2019 Integrated Device Technology, Inc.
0.00412
41.9
0.01217
65.3
0.00425
43.6
Base_Current (mA)
37.5
61.1
40.1
Table 15F. 2.5V LVCMOS Output Calculation Table
Table 15C. 3.3V LVDS Output Calculation Table
LVDS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Base_Current (mA)
Table 15E. 3.3V LVCMOS Output Calculation Table
Table 15B. 2.5V LVPECL Output Calculation Table
LVPECL
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FQ_Factor (mA/MHz)
LVCMOS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
54
Base_Current (mA)
31.0
54.6
33.2
January 17, 2019
8T49N281 Datasheet
Table 15G. 1.8V LVCMOS Output Calculation Table
LVCMOS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Base_Current (mA)
26.8
50.4
29.0
Applying the values to the following equation will yield output current by frequency:
Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base_Current
where:
Qx Current is the specific output current according to output type and frequency
FQ_Factor is used for calculating current increase due to output frequency
Base_Current is the base current for each output path independent of output frequency
The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following
equation:
TJ = TA + (JA * Pdtotal)
where:
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
JA is the thermal resistance value from Table 14, dependent on ambient airflow (°C/W)
Pdtotal is the total power dissipation of the 8T49N281 under usage conditions, including power dissipated due to loading (W)
Note that for LVPECL outputs the power dissipation through the load is assumed to be 27.95mW. When selecting LVCMOS outputs, power
dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power
dissipation through loading will be calculated using CPD (found in Table 2) and output frequency:
PdOUT = CPD * FOUT * VCCO2
where:
PdOUT is the power dissipation of the output (W)
CPD is the power dissipation capacitance (pF)
FOUT is the output frequency of the selected output (MHz)
VCCO is the voltage supplied to the appropriate output (V)
©2019 Integrated Device Technology, Inc.
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8T49N281 Datasheet
Example Calculations
Example 1. Common Customer Configuration (3.3V Core Voltage)
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Output Type
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVCMOS
LVCMOS
VCCO
Frequency (MHz)
625
625
212.5
212.5
25
25
125
125
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
• Core Supply Current, ICC = 90mA (max)
• Analog Supply Current, ICCA = 187mA (max)
Q0 Current = 0.00624x625 + 40.3 = 44.2mA
Q1 Current = 0.00624x625 + 40.3 = 44.2mA
Q2 Current = 0.01445x212.5 + 63.6 = 66.67mA
Q3 Current = 0.01445x212.5 + 63.6 = 66.67mA
Q4 Current = 0.00646x25 + 51.5 = 51.66mA
Q5 Current = 0.00646x25 + 51.5 = 51.66mA
Q6 Current = 40.1mA
Q7 Current = 40.1mA
• Total Output Current = 405.26mA (max)
Total Device Current = 90mA + 187mA + 405.26mA = 682.26mA
Total Device Power = 3.465V * 682.26mA = 2364mW
• Power dissipated through output loading:
LVPECL = 27.95mW * 4 = 111.8mW
LVDS = already accounted for in device power
LVCMOS = 14.5pF * 125MHz * 3.465V2 * 2 output pairs = 43.5mW
• Total Power = 2364mW + 111.8mW + 43.5mW = 2519.3mW or 2.52W
With an ambient temperature of 85°C and no airflow, the junction temperature is:
TJ = 85°C + 16.0°C/W * 2.52W = 125.3°C
This junction temperature is above the maximum allowable. In instances where maximum junction temperature is exceeded adjustments need
to be made to either airflow or ambient temperature. In this case, adjusting airflow to 1m/s (JA = 12.14°C/W) will reduce junction temperature
to 115.6°C. If no airflow adjustments can be made, the maximum ambient operating temperature must be reduced by a minimum of 0.3°C.
©2019 Integrated Device Technology, Inc.
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8T49N281 Datasheet
Example 2. Low Power Customer Configuration (2.5V Core Voltage)
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Output Type
LVDS
LVDS
LVDS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVDS
VCCO
Frequency (MHz)
156.25
156.25
161.133
33.333
25
25
25
156.25
2.5
2.5
2.5
1.8
1.8
1.8
1.8
2.5
• Core Supply Current, ICC = 85mA (max)
• Analog Supply Current, ICCA = 182mA (max)
Q0 Current = 0.00412x156.25 + 41.9 = 42.54mA
Q1 Current = 0.00412x156.25 + 41.9 = 42.54mA
Q2 Current = 0.01217x161.133 + 65.3 = 67.26mA
Q3 Current = 50.4mA
Q4 Current = 29mA
Q5 Current = 29mA
Q6 Current = 29mA
Q7 Current = 0.00425x156.25 + 43.6 = 44.26mA
• Total Output Current = 196.6mA (VCCO = 2.5V), 137.4mA (VCCO = 1.8V)
Total Device Power = 2.625V *(85mA + 182mA + 196.6mA) + 1.89V * 137.4mA = 1476.6mW
• Power dissipated through output loading:
LVPECL = n/a
LVDS = already accounted for in device power
LVCMOS_33.3MHz = 17pF * 33.3MHz * 1.89V2 * 1 output pair = 2.02mW
LVCMOS_25MHz = 12.5pF * 25MHz * 1.89V2 * 3 output pairs = 3.35mW
Total Power = 1476.6mW + 2.02mW + 3.35mW = 1481.97mW or 1.48W
With an ambient temperature of 85°C, the junction temperature is:
TJ = 85°C + 16.0°C/W *1.48W = 108.7°C
This junction temperature is below the maximum allowable.
Reliability Information
Table 16. JA vs. Air Flow Table for a 56-Lead VFQFN
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2
16.0°C/W
12.14°C/W
11.02°C/W
NOTE: Theta JA (JA)values calculated using a 4-layer JEDEC PCB (114.3mm x 101.6mm), with 2oz. (70m) copper plating on all 4 layers.
Transistor Count
The transistor count for 8T49N281 is: 959,346
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8T49N281 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/nlnlg-56-package-outline-80-x-80-mm-body-epad-660mm-sq-050-mm-pitch-vfqfp-n
Marking Diagram
1. Line 1 and Line 2 indicate the part number. “001” will vary due to configuration.
2. “Line 3 indicates the following:
▪ #” denotes sequential lot number.
▪ “YYWW” is the last two digits of the year and week that the part was assembled.
▪ “$” denotes the mark code.
Ordering Information
Table 17. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8T49N281C-dddNLGI
IDT8T49N281C-dddNLGI
“Lead-Free” 56-Lead VFQFN
Tray
-40C to +85C
8T49N281C-dddNLGI8
IDT8T49N281C-dddNLGI
“Lead-Free” 56-Lead VFQFN
Tape & Reel, Pin 1
Orientation: EIA-481-C
-40C to +85C
8T49N281C-dddNLGI#
IDT8T49N281C-dddNLGI
“Lead-Free” 56-Lead VFQFN
Tape & Reel, Pin 1
Orientation: EIA-481-D
-40C to +85C
NOTE: For the specific -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document.
Table 18. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
Correct Pin 1 ORIENTATION
NLGI8
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
Correct Pin 1 ORIENTATION
NLGI#
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
©2019 Integrated Device Technology, Inc.
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8T49N281 Datasheet
ERRATA
Errata # 1: EEPROM CRC Check Failure
•
Errata: if the UFT++ attempts to load its initial configuration from an external EEPROM and the CRC check fails, the serial port will not
complete write operations and will only respond to reads with values of 0 until device is reset via nRST pin.
- if no EEPROM access is attempted, no EEPROM is found or the EEPROM read succeeds there are no issues
- The CRC failure condition can be detected by reading the Global Interrupt Status Register at address 21Fh. If the nEEP_CRC bit is low,
then the device's serial port is now in the failed state.
- if the device is also programmed to load its registers from the internal One-Time Programmable memory, those register settings will be
correctly loaded and used.
•
Work-Around: by reading the nEEP_CRC bit, this condition can be detected. Once detected, the user may attempt to retry the EEPROM
load operation by asserting then releasing the nRST input pin. If the retry attempt continues to fail, then no further recovery is possible. Note
that a persistent EEPROM CRC failure indicates a corrupted configuration is present and the device could not be correctly configured anyway.
•
Fix Plan: None
Errata # 2: GPIOs Can't Use Input Mode if VCCO = 1.8V
•
Errata: When the VCCO pin adjacent to a GPIO pin is set to 1.8V and the core VCC of the chip is at 3.3V, the GPIO pin will not behave
as an input, either a General-Purpose Input or an Output Enable. Mappings are according to the following relationships:
GPIO0 / VCCO3
GPIO1 / VCCO3
GPIO2 / VCCO4
GPIO3 / VCCO7
•
Work-Around: Ensure that voltage used on VCCO pins is no less than VCC - 1.6V.
•
Fix Plan: None
©2019 Integrated Device Technology, Inc.
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8T49N281 Datasheet
Revision History
Revision Date
January 17, 2019
Description of Change
• Corrected the I2C read sequence diagrams in Figure 3 and Figure 4 to match I2C specification and device
actual performance. Note: Only the drawings were incorrect – the part’s behavior did not change and
continues to meet the I2C specification.
• Added a Marking Diagram
January 28, 2016
Per PCN# W1512-01, Effective Date 03/18/2016 - changed Part/Order Number from 8T49N281B-dddNLGI to
8T49N281C-dddNLGI, and Marking from IDT8T49N281B-dddNLGI to IDT8T49N281C-dddNLGI.
Updated Datasheet header/footer.
September 30, 2015
Updated Pin Descriptions for pins 3, 4, 52, 53.
Output Phase Control on Switchover - added sentence to second and third paragraphs.
Added notes to Table 4.
AC Characteristics Table - updated Note 5.
Updated Power Domains figure.
July 8, 2015
Device Start-up & Reset Behavior - added second paragraph.
May 4, 2015
Thermal Resistance Table - corrected table numbering from15 and auto-numbered rest of tables.
Deleted prefix/suffix from part number through-out the datasheet.
April 24, 2015
AC Characteristics Table - added missing minimum Output Frequency spec for Q2, Q3 (LVPECL, LVDS) and
LVCMOS.
Termination for 3.3V LVPECL Outputs - updated Figure 10A.
Crystal Recommendation - included additional crystal recommendation.
July 17, 2014
DSM_INT[8:0] field: added text “Do not set higher than FFh. This implies that for crystal frequencies lower
then 16MHz, the doubler circuit must be enabled.”
May 30, 2014
Bypath Path Section, 1st paragraph; added to last sentence “and the CLK1 Input reference will be presented
to the Q5 output dividers”.
Input Clock Section, 8th paragraph; replaced last sentence with “It is recommended that all input references
be given different priority settings in the Clock Input Priority control register.”
Output Phase Alignment, No. 3; Replaced text.
LVCMOS Operation; replaced last sentence.
Replaced “Femto NG” with “FemtoClock NG” (4 places).
UFTADD[6:2]; replaced description.
UFTADD[1]: changed 1st sentence to “I2C Base Address bit 1. This bit is fixed as 0.”
UFTADD[0]; replaced description.
Replaced XTAL_IN and XTAL_OUT with OSCI and OSCO respectively.
Replaced Package Outline.
Ordering Information; added pin orientation information.
Added Table 19.
©2019 Integrated Device Technology, Inc.
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8T49N281 Datasheet
Revision Date
Description of Change
April 30, 2014
Added NOTE 1 to CIN.
General-Purpose I/Os & Interrupts section; added last paragraph.
I2C Mode Operation, first paragraph; replaced “using the address defined in the Status Control register” with
“using the address defined in the Serial Interface Control register (0006h)”.
I2C Master Mode, 3rd bullet; replaced '0xE0' with 'E0h'.
I2C Master Mode, 4th bullet; replaced '0x05' with '05h'.
I2C Boot-up Initialization Mode, second paragraph; replaced “The BOOTFAIL bit in the Status Control register
will also be set in this event.” with “The BOOTFAIL bit (021Eh) in the Global Interrupt Status register will
also be set in this event”.
Description; replaced '0xE0' with 'E0h'.
EEPROM Offset (Hex) column; deleted ‘0x’ of 0x## (15 instances).
Table Header; deleted ‘(Binary)’ from ‘Default Value”.
Replaced values formatting for Default Value column.
Description; replaced '0x0219' with '0219h'.
Outputs, VO (GPIO, SDATA, SCLK, nINT); changed GPIO to GPIO[3;0].
Added Note; NOTE: VCCOX denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7.
Table Header; Changed VCCOX to VCC.
ERRATA; 1st bullet/sub 2; replaced '0x21F' with '21Fh'.
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without
notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed
in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any
particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
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Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc All rights reserved.
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