8T49N282C-998NLGI

FemtoClock® NG Octal Universal Frequency Translator Description Features The 8T49N282 has two independent, fractional-feedback PLLs that can be used as jitter attenuators and frequency translators. It is equipped with six integer and two fractional output dividers, allowing the generation of up to eight different output frequencies, ranging from 8kHz to 1GHz. Four of these frequencies are completely independent of each other and the inputs. The other four are related frequencies. The eight outputs may select among LVPECL, LVDS or LVCMOS output levels. • • • • • • This functionality makes it ideal to be used in any frequency translation application, including 1G, 10G, 40G and 100G Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates. The device may also behave as a frequency synthesizer. The 8T49N282 accepts up to four differential or single-ended input clocks and a crystal input. Each of the two internal PLLs can lock to different input clocks which may be of independent frequencies. The other two input clocks are intended for redundant backup of the primary clocks and must be related in frequency to their primary. • • • The device supports hitless reference switching between input clocks. The device monitors all input clocks for Loss of Signal (LOS), and generates an alarm when an input clock failure is detected. Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped clocks. • The 8T49N282 supports holdover for each PLL. The holdover has an initial accuracy of ±50ppB from the point where the loss of all applicable input reference(s) has been detected. It maintains a historical average operating point for each PLL that may be returned to in holdover at a limited phase slope. • • • The device places no constraints on input to output frequency conversion, supporting all FEC rates, including the new revision of ITU-T Recommendation G.709 (2009), most with 0ppm conversion error. • • Each PLL has a register-selectable loop bandwidth from 0.5Hz to 512Hz. • • Each output supports individual phase delay settings to allow output-output alignment. The device supports Output Enable inputs and Lock, Holdover and LOS status outputs. The device is programmable through an I2C interface. It also supports I2C master capability to allow the register configuration to be read from an external EEPROM. The user may select whether the programming interface uses I2C protocols or SPI protocols, however in SPI mode, read from the external EEPROM is not supported. • Typical Applications • • • • • • • OTN or SONET / SDH equipment Line cards (up to OC-192, and supporting FEC ratios) OTN de-mapping (Gapped Clock and DCO mode) Gigabit and Terabit IP switches / routers including support of Synchronous Ethernet Wireless base station baseband Data communications ©2019 Integrated Device Technology, Inc. 1 8T49N282 Datasheet Supports SDH/SONET and Synchronous Ethernet clocks including all FEC rate conversions Two differential outputs meet jitter limits for 100G Ethernet and STM-256/OC-768 • 95nF, otherwise set to 1: 0 = 1 ppm accuracy 1 = 16 ppm accuracy DBITM_1 R/W 0b Digital Lock Manual Override Setting for Analog PLL1: 0 = Automatic Mode 1 = Manual Mode VCOMAN_1 R/W 1b Manual Lock Mode VCO Selection Setting for Analog PLL1: 0 = VCO2 1 = VCO1 DBIT1_1[4:0] R/W 01011b Manual Mode Digital Lock Control Setting for VCO1 in Analog PLL1: DBIT2_1[4:0] R/W 00000b Manual Mode Digital Lock Control Setting for VCO2 in Analog PLL1. SYN_MODE1 R/W 0b Rsvd R/W - ©2019 Integrated Device Technology, Inc. Frequency Synthesizer Mode Control for PLL1: 0 = PLL1 jitter attenuates and translates one or more input references. 1 = PLL1 synthesizes output frequencies using only the crystal as a reference. Note that the STATE1[1:0] field in the Digital PLL1 Control Register must be set to Force Freerun state. Reserved. Always write 0 to this bit location. Read values are not defined. 39 January 28, 2019 8T49N282 Datasheet Table 7P. Power Down Control Register Bit Field Locations and Descriptions Power Down Control Register Block Field Locations Address (Hex) D7 D6 D5 00B4 D3 D2 D1 D0 Rsvd 00B5 Rsvd 00B6 00B7 D4 CLK3_DIS Rsvd Q7_DIS CLK2_DIS PLL1_DIS Q6_DIS 00B8 DBL_DIS Q5_DIS CLK0_DIS Rsvd Q4_DIS Rsvd CLK1_DIS Q3_DIS Q2_DIS Q1_DIS Q0_DIS DPLL1_DIS DPLL0_DIS CALRST1 CALRST0 Power Down Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description DBL_DIS R/W 0b Controls whether Crystal Input Frequency is doubled before being used in PLL0 or PLL1: 0 = 2x Actual Crystal Frequency Used 1 = Actual Crystal Frequency Used CLKm_DIS R/W 0b Disable Control for Input Reference m: 0 = Input Reference m is Enabled 1 = Input Reference m is Disabled PLL1_DIS R/W 0b Disable Control for Analog PLL1: 0 = PLL1 Enabled 1 = Analog PLL1 Disabled Qm_DIS R/W 0b Disable Control for Output Qm, nQm: 0 = Output Qm, nQm functions normally 1 = All logic associated with Output Qm, nQm is Disabled & Driver in High-Impedance state DPLLm_DIS R/W 0b Disable Control for Digital PLLm: 0 = Digital PLLm Enabled 1 = Digital PLLm Disabled CALRSTm R/W 0b Reset Calibration Logic for Analog PLLm: 0 = Calibration Logic for Analog PLLm Enabled 1 = Calibration Logic for Analog PLLm Disabled Rsvd R/W - ©2019 Integrated Device Technology, Inc. Reserved. Always write 0 to this bit location. Read values are not defined. 40 January 28, 2019 8T49N282 Datasheet Table 7Q. Input Monitor Control Register Bit Field Locations and Descriptions Input Monitor Control Register Block Field Locations Address (Hex) D7 D6 D5 00B9 D4 D3 D2 D1 D0 Rsvd LOS_0[16] 00BA LOS_0[15:8] 00BB LOS_0[7:0] 00BC Rsvd LOS_1[16] 00BD LOS_1[15:8] 00BE LOS_1[7:0] 00BF Rsvd 00C0 LOS_2[16] LOS_2[15:8] 00C1 LOS_2[7:0] 00C2 Rsvd LOS_3[16] 00C3 LOS_3[15:8] 00C4 LOS_3[7:0] 00C5 Rsvd 00C6 Rsvd Input Monitor Control Register Block Field Descriptions Bit Field Name Field Type Default Value Description LOS_m[16:0] R/W 1FFFFh Number of Input Monitoring clock periods before Input Reference m is considered to be missed (soft alarm). Minimum setting is 3. Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. Table 7R. Interrupt Enable Control Register Bit Field Locations and Descriptions Interrupt Enable Control Register Block Field Locations Address (Hex) D7 D6 D5 D4 00C7 LOL1_EN LOL0_EN HOLD1_EN HOLD0_EN 00C8 D3 D2 D1 D0 LOS3_EN LOS2_EN LOS1_EN LOS0_EN Rsvd Interrupt Enable Control Register Block Field Descriptions Bit Field Name Field Type Default Value LOLm_EN R/W 0b Interrupt Enable Control for Loss-of-Lock Interrupt Status Bit for PLLm: 0 = LOLm_INT register bit will not affect status of nINT output signal 1 = LOLm_INT register bit will affect status of nINT output signal HOLDm_EN R/W 0b Interrupt Enable Control for Holdover Interrupt Status Bit for PLLm: 0 = HOLDm_INT register bit will not affect status of nINT output signal 1 = HOLDm_INT register bit will affect status of nINT output signal LOSm_EN R/W 0b Interrupt Enable Control for Loss-of-Signal Interrupt Status Bit for Input Reference m: 0 = LOSm_INT register bit will not affect status of nINT output signal 1 = LOSm_INT register bit will affect status of nINT output signal Rsvd R/W - ©2019 Integrated Device Technology, Inc. Description Reserved. Always write 0 to this bit location. Read values are not defined. 41 January 28, 2019 8T49N282 Datasheet Table 7S. Interrupt Status Register Bit Field Locations and Descriptions This register contains’ sticky’ bits for tracking the status of the various alarms. Whenever an alarm occurs, the appropriate Interrupt Status bit will be set. The Interrupt Status bit will remain asserted even after the original alarm goes away. The Interrupt Status bits remain asserted until explicitly cleared by a write of a ‘1’ to the bit over the serial port. This type of functionality is referred to as Read / Write-1-to-Clear (R/W1C). Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0200 LOL1_INT LOL0_INT HOLD1_INT HOLD0_INT LOS3_INT LOS2_INT LOS1_INT LOS0_INT 0201 Rsvd 0202 Rsvd 0203 Rsvd Interrupt Status Register Block Field Descriptions Bit Field Name LOLm_INT HOLDm_INT Field Type Default Value R/W1C R/W1C Description 0b Interrupt Status Bit for Loss-of-Lock on PLLm: 0 = No Loss-of-Lock alarm flag on PLLm has occurred since the last time this register bit was cleared. 1 = At least one Loss-of-Lock alarm flag on PLLm has occurred since the last time this register bit was cleared. 0b Interrupt Status Bit for Holdover on PLLm: 0 = No Holdover alarm flag on PLLm has occurred since the last time this register bit was cleared. 1 = At least one Holdover alarm flag on PLLm has occurred since the last time this register bit was cleared. Interrupt Status Bit for Loss-of-Signal on Input Reference m: 0 = No Loss-of-Signal alarm flag on Input Reference m has occurred since the last time this register bit was cleared. 1 = At least one Loss-of-Signal alarm flag on Input Reference m has occurred since the last time this register bit was cleared. LOSm_INT R/W1C 0b Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. Table 7T. Output Phase Adjustment Status Register Bit Field Locations and Descriptions Output Phase Adjustment Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0204 PA_BUSY7 PA_BUSY6 PA_BUSY5 PA_BUSY4 PA_BUSY3 PA_BUSY2 PA_BUSY1 PA_BUSY0 Output Phase Adjustment Status Register Block Field Descriptions Bit Field Name PA_BUSYm Field Type Default Value R/O ©2019 Integrated Device Technology, Inc. - Description Phase Adjustment Event Status for output Qm, nQm: 0 = No phase adjustment is currently in progress on output Qm, nQm 1 = Phase adjustment still in progress on output Qm, nQm. Do not initiate any new phase adjustment at this time. 42 January 28, 2019 8T49N282 Datasheet Table 7U. Digital PLL0 Status Register Bit Field Locations and Descriptions Digital PLL0 Status Register Block Field Locations Address (Hex) D4 D3 0205 D7 Rsvd D6 D5 EXTLOS0 Rsvd 0206 Rsvd Rsvd Rsvd 0207 D2 D1 D0 CURR_REF0[2:0] Rsvd Rsvd Rsvd 0208 Rsvd Rsvd 0209 Rsvd 020A Rsvd Rsvd 020B Rsvd 020C Rsvd 020D Rsvd 020E Rsvd Digital PLL0 Status Register Block Field Descriptions Bit Field Name Field Type Default Value Description CURR_REF0[2:0] R/O - Currently Selected Reference Status for Digital PLL0: 000 - 011 = No reference currently selected 100 = Input Reference 0 (CLK0, nCLK0) selected 101 = Input Reference 1 (CLK1, nCLK1) selected 110 = Input Reference 2 (CLK2, nCLK2) selected 111 = Input Reference 3 (CLK3, nCLK3) selected EXTLOS0 R/O - External Loopback signal lost for PLL0: 0 = PLL0 has a valid feedback reference signal 1 = PLL0 has lost the external feedback reference signal and is no longer locked Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. ©2019 Integrated Device Technology, Inc. 43 January 28, 2019 8T49N282 Datasheet Table 7V. Digital PLL1 Status Register Bit Field Locations and Descriptions Digital PLL1 Status Register Block Field Locations Address (Hex) D4 D3 020F D7 Rsvd D6 D5 EXTLOS1 Rsvd 0210 Rsvd Rsvd Rsvd 0211 D2 D1 D0 CURR_REF1[2:0] Rsvd Rsvd Rsvd 0212 Rsvd Rsvd 0213 Rsvd 0214 Rsvd Rsvd 0215 Rsvd 0216 Rsvd 0217 Rsvd 0218 Rsvd Digital PLL1 Status Register Block Field Descriptions Bit Field Name Field Type Default Value Description CURR_REF1[2:0] R/O - Currently Selected Reference Status for Digital PLL1: 000 - 011 = No reference currently selected 100 = Input Reference 0 (CLK0, nCLK0) selected 101 = Input Reference 1 (CLK1, nCLK1) selected 110 = Input Reference 2 (CLK2, nCLK2) selected 111 = Input Reference 3 (CLK3, nCLK3) selected EXTLOS1 R/O - External Loopback signal lost for PLL1 0 = PLL1 has a valid feedback reference signal 1 = PLL1 has lost the external feedback reference signal and is no longer locked Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. Table 7W. General Purpose Input Status Register Bit Field Locations and Descriptions Global Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 D4 D3 D2 D1 D0 0219 GPI[7] GPI[6] GPI[5] GPI[4] GPI[3] GPI[2] GPI[1] GPI[0] General Purpose Input Status Register Block Field Descriptions Bit Field Name Field Type Default Value GPI[7:0] R/O - ©2019 Integrated Device Technology, Inc. Description Shows current values on GPIO[7:0] pins that are configured as General-Purpose Inputs. 44 January 28, 2019 8T49N282 Datasheet Table 7X. Global Interrupt Status Register Bit Field Locations and Descriptions Global Interrupt Status Register Block Field Locations Address (Hex) D7 D6 D5 021A D4 D3 D2 Rsvd 021B D0 INT Rsvd 021C Rsvd Rsvd 021D Rsvd Rsvd 021E 021F D1 Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd nEEP_CRC Rsvd Rsvd BOOTFAIL Rsvd EEPDONE Global Interrupt Status Register Block Field Descriptions Bit Field Name Field Type Default Value Description INT R/O - Device Interrupt Status: 0 = No Interrupt Status bits that are enabled are asserted (nINT pin released) 1 = At least one Interrupt Status bit that is enabled is asserted (nINT pin asserted low) BOOTFAIL R/O - Reading of Serial EEPROM failed. Once set this bit is only cleared by reset. nEEP_CRC R/O - EEPROM CRC Error (Active Low): 0 = EEPROM was detected and read, but CRC check failed - please reset the device via the nRST pin to retry (serial port is locked) 1 = No EEPROM CRC Error EEPDONE R/O - Serial EEPROM Read cycle has completed. Once set this bit is only cleared by reset. Rsvd R/W - Reserved. Always write 0 to this bit location. Read values are not defined. ©2019 Integrated Device Technology, Inc. 45 January 28, 2019 8T49N282 Datasheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 3.63V Inputs, VI OSCI Other Input 0V to 2V -0.5V to VCC + 0.5V Outputs, VO (Q[0:7], nQ[0:7]) -0.5V to VCCOX + 0.5V Outputs, VO (GPIO[0:7], SDATA, SCLK, nINT) -0.5V to VCC + 0.5V Outputs, IO (Q[0:7], nQ[0:7]) Continuous Current Surge Current  40mA 65mA Outputs, IO (GPIO[0:7], SDATA, SCLK, nINT)) Continuous Current Surge Current  8mA 13mA Junction Temperature, TJ 125C Storage Temperature, TSTG -65C to 150C NOTE: VCCOX denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. Supply Voltage Characteristics Table 8A. Power Supply Characteristics, VCC = 3.3V ±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Core Supply Current; NOTE 1 ICCA Analog Supply Current; NOTE 1 IEE Power Supply Current; NOTE 2 Minimum Typical Maximum Units 3.135 3.3 3.465 V VCC – 0.13 3.3 VCC V 82 100 mA PLL0 and PLL1 Enabled 207 265 mA Analog PLL1, Digital PLL1, and Calibration Logic for Analog PLL1 Disabled 121 187 mA Q[0:7] Configured for LVPECL Logic Levels; Outputs Unloaded 575 735 mA Test Conditions NOTE 1: ICC and ICCA are included in IEE when Q[0:7] configured for LVPECL logic levels. NOTE 2: Internal dynamic switching current at maximum fOUT is included. ©2019 Integrated Device Technology, Inc. 46 January 28, 2019 8T49N282 Datasheet Table 8B. Power Supply Characteristics, VCC = 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Core Supply Current; NOTE 1 ICCA Analog Supply Current; NOTE 1 IEE Power Supply Current; NOTE 2 Minimum Typical Maximum Units 2.375 2.5 2.625 V VCC – 0.13 2.5 VCC V 79 95 mA PLL0 and PLL1 enabled 201 260 mA Analog PLL1, Digital PLL1, and Calibration Logic for Analog PLL1 Disabled 116 182 mA Q[0:7] Configured for LVPECL Logic Levels; Outputs Unloaded 544 695 mA NOTE 1: ICC and ICCA are included in IEE when Q[0:7] configured for LVPECL logic levels. NOTE 2: Internal dynamic switching current at maximum fOUT is included. Table 8C. Maximum Output Supply Current, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C VCCOx = 3.3V ±5% VCCOx = 2.5V ±5% VCCOx = 1.8V ±5% Symbol Parameter Test Conditions LVPECL LVDS LVCMOS LVPECL LVDS LVCMOS LVCMOS Units ICCO0 Q0, nQ0 Output  Supply Current Outputs Unloaded 50 60 55 40 50 45 35 mA ICCO1 Q1, nQ1 Output  Supply Current Outputs Unloaded 50 60 55 40 50 45 35 mA ICCO2 Q2, nQ2 Output  Supply Current Outputs Unloaded 80 90 80 70 80 70 60 mA ICCO3 Q3, nQ3 Output  Supply Current Outputs Unloaded 80 90 80 70 80 70 60 mA ICCO4 Q4, nQ4 Output  Supply Current Outputs Unloaded 55 65 55 45 55 45 40 mA ICCO5 Q5, nQ5 Output  Supply Current Outputs Unloaded 55 65 55 45 55 45 40 mA ICCO6 Q6, nQ6 Output  Supply Current Outputs Unloaded 55 65 55 45 55 45 40 mA 55 45 40 mA Q7, nQ7 Output  Outputs Unloaded 55 65 55 45 Supply Current NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Internal dynamic switching current at maximum fOUT is included. ICCO7 ©2019 Integrated Device Technology, Inc. 47 January 28, 2019 8T49N282 Datasheet DC Electrical Characteristics Table 9A. LVCMOS/LVTTL DC Characteristics, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL VOH Input High Current Input Low Current Output High Voltage Output Low Voltage Test Conditions Minimum VCC = 3.3V Typical Maximum Units 2 VCC +0.3 V VCC = 2.5V 1.7 VCC +0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V nI2C_SPI, PLL_BYP, S_A0/nCS, S_A1/SDI VCC = VIN = 3.465V or 2.625V 150 μA nRST, SDATA/SDO, nWP, SCLK/SCLK VCC = VIN = 3.465V or 2.625V 5 μA GPIO[7:0] VCC = VIN = 3.465V or 2.625V 1 mA nI2C_SPI, PLL_BYP, S_A0/nCS, S_A1/SDI VCC = 3.465V or 2.625V, VIN = 0V -5 μA nRST, SDATA/SDO, nWP, SCLK/SCLK VCC = 3.465V or 2.625V, VIN = 0V -150 μA GPIO[7:0] VCC = 3.465V or 2.625V, VIN = 0V -1 mA nINT, SDATA/SDO, SCLK/SCLK; NOTE 1 VCC = 3.3V ±5%, IOH = -5μA 2.6 V GPIO[7:0] VCC = 3.3V ±5%, IOH = -50μA 2.6 V nINT, SDATA/SDO, SCLK/SCLK; NOTE 1 VCC = 2.5V ±5%, IOH = -5μA 1.8 V GPIO[7:0] VCC = 2.5V ±5%, IOH = -50μA 1.8 V nINT, SDATA/SDO, SCLK/SCLK; NOTE 1 VCC = 3.3V ±5% or 2.5V ±5%, IOL = 5mA 0.5 V GPIO[7:0] VCC = 3.3V ±5% or 2.5V ±5%, IOL = 5mA NOTE 1: Use of external pull-up resistors is recommended. 0.5 V VOL Table 9B. Differential Input DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current 150 μA IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 VEE VCC -1.2 V CLKx, nCLKx VCC = VIN = 3.465V or 2.625V CLKx VCC = 3.465V or 2.625V, VIN = 0V -5 μA nCLKx VCC = 3.465V or 2.625V, VIN = 0V -150 μA NOTE: CLKx denotes CLK0, CLK1, CLK2, CLK3. nCLKx denotes nCLK0, nCLK1, nCLK2, nCLK3. NOTE 1: VIL should not be less than -0.3V. VIH should not be higher than VCC. NOTE 2: Common mode voltage is defined as the cross-point. ©2019 Integrated Device Technology, Inc. 48 January 28, 2019 8T49N282 Datasheet Table 9C. LVPECL DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C VCCOx = 3.3V±5% Symbol Parameter Test Conditions VOH Output  High Voltage;  Qx, nQx NOTE 1 VOL Output  Low Voltage;  Qx, nQx NOTE 1 Minimum Typical VCCOx = 2.5V±5% Maximum Minimum VCCOx - 1.3 VCCOx - 0.8 VCCOx - 1.95 VCCOx - 1.75 Typical Maximum Units VCCOx - 1.35 VCCOx - 0.9 V VCCOx - 1.95 VCCOx - 1.75 V NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE 1: Outputs terminated with 50 to VCCOx – 2V. Table 9D. LVDS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VOD Differential Output Voltage Qx, nQx VOD VOD Magnitude Change Qx, nQx VOS Offset Voltage Qx, nQx VOS VOS Magnitude Change Qx, nQx Minimum Typical 195 1.1 Maximum Units 454 mV 50 mV 1.375 V 50 mV NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. NOTE: Terminated 100 across Qx and nQx. Table 9E. LVCMOS DC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VCCOx = 3.3V±5% Test Conditions Minimum 2.6 VOH Output  High Voltage Qx, nQx IOH = -8mA VOL Output  Low Voltage Qx, nQx IOL = 8mA Typical Maximum VCCOx = 2.5V±5% Minimum Typical VCCOx = 1.8V ±5% Maximum Minimum 1.8 Typical Maximum 1.1 0.5 Units V 0.5 0.5 V NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Qx denotes Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7. nQx denotes nQ0, nQ1, nQ2, nQ3, nQ4, nQ5, nQ6, nQ7. Table 10. Input Frequency Characteristics, VCC = 3.3V±5% or 2.5V±5%, TA = -40°C to 85°C Symbol Parameter Test Conditions fIN Input Frequency; NOTE 1 fSCLK Serial Port I2C Operation Clock SCLK (slave mode) SPI Operation Minimum Typical Maximum Units OSCI, OSCO 10 40 MHz CLKx, nCLKx 0.008 875 MHz 100 400 kHz 4.25 MHz NOTE: CLKx denotes CLK0, CLK1, CLK2, CLK3. nCLKx denotes nCLK0, nCLK1, nCLK2, nCLK3. NOTE 1: For the input reference frequency, the divider values must be set for the VCO to operate within its supported range. ©2019 Integrated Device Technology, Inc. 49 January 28, 2019 8T49N282 Datasheet Table 11. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units 40 MHz Fundamental Frequency 10 Equivalent Series Resistance (ESR) 15  Load Capacitance (CL) 12 pF Frequency Stability (total) -100 100 ppm AC Electrical Characteristics Table 12. AC Characteristics, VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C Symbol Parameter fVCO VCO Operating Frequency fOUT Output Frequency Test Conditions LVPECL / LVDS Maximum Units 3000 4000 MHz Q0, Q1, Q4, Q5, Q6, Q7 outputs 0.008 1000 MHz Q2, Q3 outputs Integer Divide Ratio & No Added Phase Delay 0.008 666.67 MHz Q2, Q3 outputs Non-integer divide and/or added phase delay 0.008 400 MHz LVCMOS tR / tF SR Output Rise and Fall Times 250 MHz 20% to 80% 145 340 600 ps LVDS 20% to 80% 100 250 500 ps 20% to 80%, VCCOx = 3.3V 180 350 600 ps 0.008 20% to 80%, VCCOx = 2.5V 200 350 550 ps 20% to 80%, VCCOx = 1.8V 200 410 650 ps LVPECL measured on differential waveform, ±150mV from center 1 5 V/ns LVDS measured on differential waveform, ±150mV from center 0.5 4 V/ns LVCMOS LVPECL tsk(b) Typical LVPECL Output Slew Rate Bank Skew Minimum LVDS LVCMOS Q0, nQ0, Q1, nQ1 NOTE 1, 2, 3, 5 75 ps Q4, nQ4, Q5, nQ5 NOTE 1, 2, 3, 5 75 ps Q6, nQ6, Q7, nQ7 NOTE 1, 2, 3, 5 75 ps Q0, nQ0, Q1, nQ1 NOTE 1, 2, 3, 5 75 ps Q4, nQ4, Q5, nQ5 NOTE 1, 2, 3, 5 75 ps Q6/,nQ6, Q7,nQ7 NOTE 1, 2, 3, 5 75 ps Q0, nQ0, Q1, nQ1 NOTE 1, 2, 4, 5, 6 80 ps Q4, nQ4, Q5, nQ5 NOTE 1, 2, 4, 5, 6 115 ps Q6, nQ6, Q7, nQ7 NOTE 1, 2, 4, 5, 6 115 ps ©2019 Integrated Device Technology, Inc. 50 January 28, 2019 8T49N282 Datasheet Symbol odc Parameter Output Duty Cycle;  NOTE 7 LVPECL LVDS Test Conditions Minimum Typical Maximum Units fOUT  666.667MHz 45 50 55 % fOUT > 666.667MHz 40 50 60 % fOUT  666.667MHz 45 50 55 % fOUT > 666.667MHz 40 50 60 % 40 50 60 % 50 ppb LVCMOS Initial Frequency Offset Switchover or entering / leaving Holdover state; NOTE 8, 13 Output Phase Change in Fully Hitless Switching Switchover or entering / leaving Holdover state; NOTE 10, 13 5 ns -50 SSB(1k) 1kHz 122.88MHz output -115 dBc/Hz SSB(10k) 10kHz 122.88MHz output -129 dBc/Hz 100kHz 122.88MHz output -134 dBc/Hz 1MHz 122.88MHz output -147 dBc/Hz 10MHz 122.88MHz output -153 dBc/Hz >30MHz 122.88MHz output -154 dBc/Hz >800kHz 122.88MHz output; NOTE 11 -85 dBc Internal OTP Startup; NOTE 13 from VCC >80% to first output clock edge 110 150 ms from VCC >80% to first output clock edge (0 retries). I2C frequency = 100kHz 150 200 ms from VCC >80% to first output clock edge (0 retries). I2C frequency = 400kHz 130 150 ms from VCC >80% to first output clock edge (31 retries). I2C frequency = 100kHz 925 1200 ms from VCC >80% to first output clock edge (31 retries). I2C frequency = 400kHz 360 500 ms SSB(100k) SSB(1M) Single Sideband  Phase Noise; NOTE 9 SSB(10M) SSB(30M) Spurious Limit at offset tstartup Startup time External EEPROM Startup; NOTE 12, 13 NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: This parameter is guaranteed by characterization. Not tested in production. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Measured at the output differential crosspoints. NOTE 4: Measured at VCCOx/2 of the rising edge. All Qx and nQx outputs phase-aligned. NOTE 5: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions running off the same clock source. NOTE 6: Appropriate SE_MODE bit must be set to enable phase-aligned operation. NOTE 7: Characterized in synthesizer mode. Duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the device. NOTE 8: Tested in fast-lock operation after >20 minutes of locked operation to ensure holdover averaging logic is stable. NOTE 9: Characterized with 8T49N282B-901units (synthesizer mode). NOTE 10: Device programmed with SWMODEn = 0 (absorbs phase differences). NOTE 11: Tested with all outputs operating at 122.88MHz. NOTE 12: Assuming a clear I2C bus. NOTE 13: This parameter is guaranteed by design.  ©2019 Integrated Device Technology, Inc. 51 January 28, 2019 8T49N282 Datasheet Table 13A. Typical RMS Phase Jitter (Synthesizer Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C Symbol Test Conditions LVPECL LVDS LVCMOSNOTE 6 Units fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz; NOTE 1 281 286 273 fs fOUT = 156.25MHz, Integration Range: 12kHz - 20MHz; NOTE 2 261 250 259 fs fOUT = 622.08MHz, Integration Range: 12kHz - 20MHz; NOTE 3 220 209 N/A (NOTE 5) fs Q2, Q3 Integer; NOTE 1 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 297 319 306 fs Q2, Q3 Fractional; NOTE 4 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 288 263 254 fs Q4, Q5, Q6, Q7;  NOTE 1 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 293 332 296 fs Parameter Q0, Q1 tjit() RMS Phase Jitter (Random) NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively. NOTE: All outputs configured for the specific output type, as shown in the table. NOTE 1: Characterized with 8T49N282B-901. NOTE 2: Characterized with 8T49N282B-902. NOTE 3: Characterized with 8T49N282B-903. NOTE 4: Characterized with 8T49N282B-900. NOTE 5: This frequency is not supported for LVCMOS operation. NOTE 6: Qx and nQx are 180° out of phase. Table 13B. Typical RMS Phase Jitter (Jitter Attenuator Mode), VCC = 3.3V ±5% or 2.5V ±5%, VCCOx = 3.3V ±5%, 2.5V ±5% or 1.8V ±5% (1.8V only supported for LVCMOS outputs), TA = -40°C to 85°C Symbol Test Conditions LVPECL LVDS LVCMOSNOTE 6 Units fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz; NOTE 1 283 287 282 fs fOUT = 156.25MHz, Integration Range: 12kHz - 20MHz; NOTE 2 260 261 272 fs fOUT = 622.08MHz, Integration Range: 12kHz - 20MHz; NOTE 3 256 255 N/A (NOTE 5) fs Q2, Q3 Integer; NOTE 1 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 311 315 317 fs Q2, Q3 Fractional; NOTE 4 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 259 266 262 fs Q4, Q5, Q6, Q7; NOTE 1 fOUT = 122.88MHz, Integration Range: 12kHz - 20MHz 298 308 302 fs Parameter Q0, Q1 tjit() RMS Phase Jitter (Random) NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Measured using a Rohde & Schwarz SMA100A as the input source. NOTE: Fox part numbers: 277LF-40-18 and 277LF-38.88-2 used for 40MHz and 38.88MHz crystals, respectively. NOTE: All outputs configured for the specific output type, as shown in the table. NOTE 1: Characterized with 8T49N282B-905. NOTE 2: Characterized with 8T49N282B-906. NOTE 3: Characterized with 8T49N282B-907. NOTE 4: Characterized with 8T49N282B-904. NOTE 5: This frequency is not supported for LVCMOS operation. NOTE 6: Qx and nQx are 180° out of phase. ©2019 Integrated Device Technology, Inc. 52 January 28, 2019 8T49N282 Datasheet Table 14A. PCI Express Jitter Specifications, VCC = VCCOx = 3.3V ±5%, TA = -40°C to 85°C Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 8 30 86 ps Phase Jitter RMS;  NOTE 2, 4, 5 ƒ = 100MHz, 40MHz Crystal Input, High Band: 1.5MHz - Nyquist (clock frequency/2) 0.5 2 3.10 ps tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS;  NOTE 2, 4, 5 ƒ = 100MHz, 40MHz Crystal Input, Low Band: 10kHz - 1.5MHz 0.04 0.2 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS;  NOTE 3, 4, 5 ƒ = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.1 0.4 0.8 ps Symbol Parameter tj (PCIe Gen 1) Phase Jitter Peak-to-Peak;  NOTE 1, 4, 5 tREFCLK_HF_RMS (PCIe Gen 2) Test Conditions Minimum NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.  NOTE 4: This parameter is guaranteed by characterization. Not tested in production. NOTE 5: Outputs configured for LVPECL mode. Fox 277LF-40-18 crystal used with doubler logic enabled. Table 14B. PCI Express Jitter Specifications, VCC = VCCOx = 2.5V ±5%, TA = -40°C to 85°C Typical Maximum PCIe Industry Specification Units ƒ = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 12 65 86 ps Phase Jitter RMS;  NOTE 2, 4, 5 ƒ = 100MHz, 40MHz Crystal Input, High Band: 1.5MHz - Nyquist (clock frequency/2) 0.8 3.10 3.10 ps tREFCLK_LF_RMS (PCIe Gen 2) Phase Jitter RMS;  NOTE 2, 4, 5 ƒ = 100MHz, 40MHz Crystal Input, Low Band: 10kHz - 1.5MHz 0.05 0.4 3.0 ps tREFCLK_RMS (PCIe Gen 3) Phase Jitter RMS;  NOTE 3, 4, 5 ƒ = 100MHz, 40MHz Crystal Input, Evaluation Band: 0Hz - Nyquist (clock frequency/2) 0.2 0.8 0.8 ps Symbol Parameter tj (PCIe Gen 1) Phase Jitter Peak-to-Peak;  NOTE 1, 4, 5 tREFCLK_HF_RMS (PCIe Gen 2) Test Conditions Minimum NOTE: VCCOx denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS (High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band). NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.  NOTE 4: This parameter is guaranteed by characterization. Not tested in production. NOTE 5: Outputs configured for LVPECL mode. Fox 277LF-40-18 crystal used with doubler logic enabled. ©2019 Integrated Device Technology, Inc. 53 January 28, 2019 8T49N282 Datasheet Noise Power (dBc/Hz) Typical Phase Noise at 156.25MHz Offset Frequency (Hz) ©2019 Integrated Device Technology, Inc. 54 January 28, 2019 8T49N282 Datasheet Applications Information Overdriving the XTAL Interface The OSCI input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The OSCO pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. Figure 8A shows an example of the interface diagram for a high speed 3.3V LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a slower and weaker LVCMOS driver. Figure 8B shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL termination with one side of the driver feeding the OSCI input. It is recommended that all components in the schematics be placed in the layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. OSCO VCC R1 100 Ro C1 Zo = 50Ω RS OSCI 0.1μF Zo = Ro + Rs R2 100 LVCMOS_Driver Figure 8A. General Diagram for LVCMOS Driver to XTAL Input Interface OSCO C2 Zo = 50Ω OSCI 0.1μF Zo = 50Ω LVPECL_Driver R1 50 R2 50 R3 50 Figure 8B. General Diagram for LVPECL Driver to XTAL Input Interface ©2019 Integrated Device Technology, Inc. 55 January 28, 2019 8T49N282 Datasheet Wiring the Differential Input to Accept Single-Ended Levels Figure 9 shows how a differential input can be wired to accept single ended levels. The reference voltage V1= VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V1in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 1.25V. Similarly, if the input clock swing is 1.8V and VCC = 3.3V, R1 and R2 value should be adjusted to set V1 at 0.9V. It is recommended to always use R1 and R2 to provide a known V1 voltage. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 9. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ©2019 Integrated Device Technology, Inc. 56 January 28, 2019 8T49N282 Datasheet 3.3V Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 10A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figure 10A to Figure 10E show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK Differential Input LVHSTL IDT LVHSTL Driver R1 50Ω R2 50Ω Figure 10D. CLKx/nCLKx Input Driven by a  3.3V LVPECL Driver Figure 10A. CLKx/nCLKx Input Driven by an  IDT Open Emitter LVHSTL Driver Figure 10E. CLKx/nCLKx Input Driven by a  3.3V LVDS Driver Figure 10B. CLKx/nCLKx Input Driven by a  3.3V LVPECL Driver 3.3V 3.3V *R3 CLK nCLK HCSL *R4 Differential Input Figure 10C. CLKx/nCLKx Input Driven by a  3.3V HCSL Driver ©2019 Integrated Device Technology, Inc. 57 January 28, 2019 8T49N282 Datasheet 2.5V Differential Clock Input Interface CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figure 11A to Figure 11D show interface examples for the CLKx/nCLKx input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 11A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 2.5V 1.8V Zo = 50Ω CLK Zo = 50Ω nCLK LVHSTL IDT Open Emitter LVHSTL Driver R1 50Ω R2 50Ω Differential Input Figure 11C. CLKx/nCLKx Input Driven by a  2.5V LVPECL Driver Figure 11A. CLKx/nCLKx Input Driven by an  IDT Open Emitter LVHSTL Driver Figure 11D. CLKx/nCLKx Input Driven by a  2.5V LVDS Driver Figure 11B. CLKx/nCLKx Input Driven by a  2.5V LVPECL Driver ©2019 Integrated Device Technology, Inc. 58 January 28, 2019 8T49N282 Datasheet Recommendations for Unused Input and Output Pins Inputs: Outputs: CLKx/nCLKx Input LVPECL Outputs For applications not requiring the use of one or more reference clock inputs, both CLKx and nCLKx can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLKx to ground. It is recommended that CLKx, nCLKx not be driven with active signals when not enabled for use by either PLL. Any unused LVPECL output pair can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVDS Outputs Any unused LVDS output pair can be either left floating or terminated with 100 across. If they are left floating there should be no trace attached. LVCMOS Control Pins All control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS Outputs Any LVCMOS output can be left floating if unused. There should be no trace attached. LVDS Driver Termination For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 12A can be used with either type of output structure. Figure 12B, which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output. Figure 12A. Standard LVDS Termination Figure 12B. Optional LVDS Termination ©2019 Integrated Device Technology, Inc. 59 January 28, 2019 8T49N282 Datasheet Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figure 13A and Figure 13B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are R3 125Ω 3.3V R4 125Ω 3.3V 3.3V Zo = 50Ω + _ Input Zo = 50Ω R1 84Ω Figure 13A. 3.3V LVPECL Output Termination ©2019 Integrated Device Technology, Inc. R2 84Ω Figure 13B. 3.3V LVPECL Output Termination 60 January 28, 2019 8T49N282 Datasheet Termination for 2.5V LVPECL Outputs level. The R3 in Figure 14C can be eliminated and the termination is shown in Figure 14B. Figure 14A and Figure 14C show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground 2.5V VCCO = 2.5V 2.5V 2.5V VCCO = 2.5V R1 250 R3 250 50Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 14A. 2.5V LVPECL Driver Termination Example Figure 14C. 2.5V LVPECL Driver Termination Example 2.5V VCCO = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50 R2 50 Figure 14B. 2.5V LVPECL Driver Termination Example ©2019 Integrated Device Technology, Inc. 61 January 28, 2019 8T49N282 Datasheet VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 15. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Lead frame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 15. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) Schematic and Layout Information Schematics for 8T49N282 can be found on IDT.com. Please search for the 8T49N282 device and click on the link for evaluation board schematics. Crystal Recommendation This device was validated using FOX 277LF series through-hole crystals including part #277LF-40-18 (40MHz) and 277LF-38.88-2 (38.88MHz). If a surface mount crystal is desired, we recommend FOX Part #603-40-48 (40MHz) or 603-38.88-7 (38.88MHz). I2C Serial EEPROM Recommendation The 8T49N282 was designed to operate with most standard I2C serial EEPROMs of 256 bytes or larger. Atmel AT24C04C was used during device characterization and is recommended for use. Please contact IDT for review of any other I2C EEPROM’s compatibility with the 8T49N282. ©2019 Integrated Device Technology, Inc. 62 January 28, 2019 8T49N282 Datasheet PCI Express Application Note PCI Express jitter analysis methodology models the system response to reference clock jitter. The block diagram below shows the most frequently used Common Clock Architecture in which a copy of the reference clock is provided to both ends of the PCI Express Link. In the jitter analysis, the transmit (Tx) and receive (Rx) serdes PLLs are modeled as well as the phase interpolator in the receiver. These transfer functions are called H1, H2, and H3 respectively. The overall system transfer function at the receiver is: Ht  s  = H3  s    H1  s  – H2  s   The jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum X(s) and is: Y  s  = X  s   H3  s    H1  s  – H2  s   PCIe Gen 2A Magnitude of Transfer Function In order to generate time domain jitter numbers, an inverse Fourier Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)]. PCI Express Common Clock Architecture For PCI Express Gen 1, one transfer function is defined and the evaluation is performed over the entire spectrum: DC to Nyquist (e.g for a 100MHz reference clock: 0Hz – 50MHz) and the jitter result is reported in peak-peak. PCIe Gen 2B Magnitude of Transfer Function For PCI Express Gen 3, one transfer function is defined and the evaluation is performed over the entire spectrum. The transfer function parameters are different from Gen 1 and the jitter result is reported in RMS. PCIe Gen 1 Magnitude of Transfer Function For PCI Express Gen 2, two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. The two evaluation ranges for PCI Express Gen 2 are 10kHz – 1.5MHz (Low Band) and 1.5MHz – Nyquist (High Band). The plots show the individual transfer functions as well as the overall transfer function Ht. ©2019 Integrated Device Technology, Inc. PCIe Gen 3 Magnitude of Transfer Function For a more thorough overview of PCI Express jitter analysis methodology, please refer to IDT Application Note PCI Express Reference Clock Requirements. 63 January 28, 2019 8T49N282 Datasheet Power Dissipation and Thermal Considerations The 8T49N282 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions is enabled. The 8T49N282 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your own specific configuration. Power Domains The 8T49N282 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). Figure 16 below indicates the individual domains and the associated power pins.         Output Divider / Buffer Q0 (V CCO0)    Output Divider / Buffer Q1 (V CCO1)  Analog & Digital PLL0  (VCCA and Core VCC)    Output Divider / Buffer Q2 (V CCO2)    CLK Input &  Divider Block  (Core VCC)  Output Divider / Buffer Q3 (V CCO3)      Output Divider / Buffer Q4 (V CCO4)  Output Divider / Buffer Q5 (V CCO5)  Analog & Digital PLL1  (VCCA and Core VCC)  Output Divider / Buffer Q6 (V CCO6)  Output Divider / Buffer Q7 (V CCO7)  Figure 16. 8T49N282 Power Domains For the output paths shown above, there are three different structures that are used. Q0 and Q1 use one output path structure, Q2 and Q3 use a second structure and Q4 – Q7 use a 3rd structure. Power consumption data will vary slightly depending on the structure used as shown in the appropriate tables below. Power Consumption Calculation Determining total power consumption involves several steps: 1. 2. 3. Determine the power consumption using maximum current values for core and analog voltage supplies from Tables 8A and 8B. Determine the nominal power consumption of each enabled output path. a. This consists of a base amount of power that is independent of operating frequency, as shown in Tables 17A through 17G (depending on the chosen output protocol). b. Then there is a variable amount of power that is related to the output frequency. This can be determined by multiplying the output frequency by the FQ_Factor shown in Tables 17A through 17G. All of the above totals are then summed. ©2019 Integrated Device Technology, Inc. 64 January 28, 2019 8T49N282 Datasheet Thermal Considerations Once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature for the device under the environmental conditions it will operate in. Thermal conduction paths, air flow rate and ambient air temperature are factors that can affect this. The thermal conduction path refers to whether heat is to be conducted away via a heatsink, via airflow or via conduction into the PCB through the device pads (including the ePAD). Thermal conduction data is provided for typical scenarios in Table 15 below. Please contact IDT for assistance in calculating results under other scenarios. Table 15. Thermal Resistance JA for 72-Lead VFQFN, Forced Convection JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 16.1°C/W 12.4°C/W 11.1°C/W Current Consumption Data and Equations Table 16A. 3.3V LVPECL Output Calculation Table LVPECL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base_Current (mA) 0.00624 40.3 0.01445 63.6 0.00609 42.2 Table 16D. 2.5V LVDS Output Calculation Table LVDS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 16B. 2.5V LVPECL Output Calculation Table LVPECL Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base_Current (mA) 0.00409 33.0 0.01179 56.4 0.00369 35.4 FQ_Factor (mA/MHz) Base_Current (mA) 0.00664 49.6 0.01479 73.0 0.00646 51.5 ©2019 Integrated Device Technology, Inc. Base_Current (mA) 0.00412 41.9 0.01217 65.3 0.00425 43.6 Table 16E. 3.3V LVCMOS Output Calculation Table LVCMOS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Table 16C. 3.3V LVDS Output Calculation Table LVDS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 FQ_Factor (mA/MHz) Base_Current (mA) 37.5 61.1 40.1 Table 16F. 2.5V LVCMOS Output Calculation Table LVCMOS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 65 Base_Current (mA) 31.0 54.6 33.2 January 28, 2019 8T49N282 Datasheet Table 16G. 1.8V LVCMOS Output Calculation Table LVCMOS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Base_Current (mA) 26.8 50.4 29.0 Applying the values to the following equation will yield output current by frequency: Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base_Current where: Qx Current is the specific output current according to output type and frequency FQ_Factor is used for calculating current increase due to output frequency Base_Current is the base current for each output path independent of output frequency The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: TJ = TA + (JA * Pdtotal) where: TJ is the junction temperature (°C) TA is the ambient temperature (°C) JA is the thermal resistance value from Table 15, dependent on ambient airflow (°C/W) Pdtotal is the total power dissipation of the 8T49N282 under usage conditions, including power dissipated due to loading (W) Note that for LVPECL outputs the power dissipation through the load is assumed to be 27.95mW. When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 2) and output frequency: PdOUT = CPD * FOUT * VCCO2 where: PdOUT is the power dissipation of the output (W) CPD is the power dissipation capacitance (pF) FOUT is the output frequency of the selected output (MHz) VCCO is the voltage supplied to the appropriate output (V) ©2019 Integrated Device Technology, Inc. 66 January 28, 2019 8T49N282 Datasheet Example Calculations Example 1. Common Customer Configuration (3.3V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PLL0 PLL1 Output Type LVPECL LVPECL LVPECL LVPECL LVDS LVDS LVCMOS LVCMOS Frequency (MHz) 245.76 245.76 33.333 33.333 125 125 25 25 Enabled Enabled VCCO 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 • Core Supply Current, ICC = 100mA (max) • Analog Supply Current, ICCA = 265mA (max) Q0 Current = 0.00624x245.76 + 40.3 = 41.83mA Q1 Current = 0.00624x245.76 + 40.3 = 41.83mA Q2 Current = 0.01445x33.333 + 63.6 = 64.08mA Q3 Current = 0.01445x33.333 + 63.6 = 64.08mA Q4 Current = 0.00646x125 + 51.5 = 52.3mA Q5 Current = 0.00646x125 + 51.5 = 52.3mA Q6 Current = 40.1mA Q7 Current = 40.1mA • Total Output Current = 396.62mA (max) Total Device Current = 100mA + 265mA + 396.6mA = 761.6mA Total Device Power = 3.465V * 761.6mA = 2639mW • Power dissipated through output loading: LVPECL = 27.95mW * 4 = 111.8mW LVDS = already accounted for in device power LVCMOS = 14.5pF * 25MHz * 3.465V2 * 2 output pairs = 8.7mW • Total Power = 2639mW + 111.8mW + 8.7mW = 2759.5mW or 2.76W With an ambient temperature of 85°C and no airflow, the junction temperature is: TJ = 85°C + 16.1°C/W * 2.76W = 129.4°C This junction temperature is above the maximum allowable. In instances where maximum junction temperature is exceeded adjustments need to be made to either airflow or ambient temperature. In this case, adjusting airflow to 1m/s (JA = 12.4°C/W) will reduce junction temperature to 119.2°C. If no airflow adjustments can be made, the maximum ambient operating temperature must be reduced by a minimum of 4.4°C. ©2019 Integrated Device Technology, Inc. 67 January 28, 2019 8T49N282 Datasheet Example 2. High-Frequency Customer Configuration (3.3V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PLL0 PLL1 Output Type LVDS LVDS LVPECL LVPECL LVDS LVDS LVPECL LVDS Frequency (MHz) 625.00 625.00 161.133 161.133 25 25 125 156.25 Enabled Disabled VCCO 2.5 2.5 2.5 2.5 3.3 3.3 2.5 2.5 • Core Supply Current, ICC = 100mA (max) • Analog Supply Current, ICCA = 187mA (max, PLL0 path only) Q0 Current = 0.00412x625 + 41.9 = 44.48mA Q1 Current = 0.00412x625 + 41.9 = 44.48mA Q2 Current = 0.01179x161.133 + 56.4 = 58.3mA Q3 Current = 0.01179x161.133 + 56.4 = 58.3mA Q4 Current = 0.00646x25 + 51.5 = 51.66mA Q5 Current = 0.00646x25 + 51.5 = 51.66mA Q6 Current = 0.00369x125 + 35.4 = 35.86mA Q7 Current = 0.00425x156.25 + 43.6 = 44.26mA • Total Output Current = 285.68mA (VCCO = 2.5V), 103.3mA (VCCO = 3.3V) Total Device Power = 3.465V *(100mA + 187mA + 103.3mA) + 2.625V * 285.68mA = 2102.3mW • Power dissipated through output loading: LVPECL = 27.95mW * 3 = 83.9mW LVDS = already accounted for in device power LVCMOS = n/a Total Power = 2102.3mW + 83.9mW = 2186.2mW or 2.19W With an ambient temperature of 85°C, the junction temperature is: TJ = 85°C + 16.1°C/W *2.19W = 120.3°C This junction temperature is below the maximum allowable. ©2019 Integrated Device Technology, Inc. 68 January 28, 2019 8T49N282 Datasheet Example 3. Low Power Customer Configuration (2.5V Core Voltage) Output Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PLL0 PLL1 Output Type LVDS LVDS LVDS LVCMOS LVCMOS LVCMOS LVCMOS LVDS VCCO Frequency (MHz) 156.25 156.25 161.133 33.333 25 25 25 156.25 Enabled Enabled 2.5 2.5 2.5 1.8 1.8 1.8 1.8 2.5 • Core Supply Current, ICC = 95mA (max) • Analog Supply Current, ICCA = 260mA (max) Q0 Current = 0.00412x156.25 + 41.9 = 42.54mA Q1 Current = 0.00412x156.25 + 41.9 = 42.54mA Q2 Current = 0.01217x161.133 + 65.3 = 67.26mA Q3 Current = 50.4mA Q4 Current = 29mA Q5 Current = 29mA Q6 Current = 29mA Q7 Current = 0.00425x156.25 + 43.6 = 44.26mA • Total Output Current = 196.6mA (VCCO = 2.5V), 137.4mA (VCCO = 1.8V) Total Device Power = 2.625V *(95mA + 260mA + 196.6mA) + 1.89V * 137.4mA = 1707.6mW • Power dissipated through output loading: LVPECL = n/a LVDS = already accounted for in device power LVCMOS_33.3MHz = 17pF * 33.3MHz * 1.89V2 * 1 output pair = 2.02mW LVCMOS_25MHz = 12.5pF * 25MHz * 1.89V2 * 3 output pairs = 3.35mW Total Power = 1707.6mW + 2.02mW + 3.35mW = 1713mW or 1.7W With an ambient temperature of 85°C, the junction temperature is: TJ = 85°C + 16.1°C/W *1.7W = 112.4°C This junction temperature is below the maximum allowable. ©2019 Integrated Device Technology, Inc. 69 January 28, 2019 8T49N282 Datasheet Reliability Information Table 17. JA vs. Air Flow Table for a 72-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 16.1°C/W 12.4°C/W 11.1°C/W NOTE: Theta JA (JA)values calculated using a 4-layer JEDEC PCB (114.3mm x 101.6mm), with 2oz. (70um) copper plating on all 4 layers. Transistor Count The transistor count for 8T49N282 is: 959,346 Marking Diagram 1. Lines 1 and 2 are the part number. 2. “002” is indicative of a configuration-specific number (dash code). 3. “#” denotes stepping. 4. “YYWW” denotes: “YY” is the last two digits of the year, and “WW” is the work week number  that the part was assembled. 5. “$” denotes the mark code. Package Outline Drawings The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most current data available. www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-75-mm-sq-050-mm-pitch-qfn-sawn ©2019 Integrated Device Technology, Inc. 70 January 28, 2019 8T49N282 Datasheet Ordering Information Table 18. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8T49N282C-dddNLGI IDT8T49N282C-dddNLGI “Lead-Free” 72-Lead VFQFN Tray -40C to +85C 8T49N282C-dddNLGI8 IDT8T49N282C-dddNLGI “Lead-Free” 72-Lead VFQFN Tape & Reel, Pin 1 Orientation: EIA-481-C -40C to +85C 8T49N282C-dddNLGI# IDT8T49N282C-dddNLGI “Lead-Free” 72-Lead VFQFN Tape & Reel, Pin 1 Orientation: EIA-481-D -40C to +85C NOTE: For the specific -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document. Table 19. Pin 1 Orientation in Tape and Reel Packaging Part Number Suffix Pin 1 Orientation Illustration Correct Pin 1 ORIENTATION NLGI8 CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 1 (EIA-481-C) USER DIRECTION OF FEED Correct Pin 1 ORIENTATION NLGI# CARRIER TAPE TOPSIDE (Round Sprocket Holes) Quadrant 2 (EIA-481-D) USER DIRECTION OF FEED ©2019 Integrated Device Technology, Inc. 71 January 28, 2019 8T49N282 Datasheet ERRATA Errata # 1: EEPROM CRC Check Failure Errata: if the UFT++ attempts to load its initial configuration from an external EEPROM and the CRC check fails, the serial port will not complete write operations and will only respond to reads with values of 0 until device is reset via nRST pin. - if no EEPROM access is attempted, no EEPROM is found or the EEPROM read succeeds there are no issues - The CRC failure condition can be detected by reading the Global Interrupt Status Register at address 21Fh. If the nEEP_CRC bit is low, then the device's serial port is now in the failed state - if the device is also programmed to load its registers from the internal One-Time Programmable memory, those register settings will be correctly loaded and used. Work-Around: by reading the nEEP_CRC bit, this condition can be detected. Once detected, the user may attempt to retry the EEPROM load operation by asserting then releasing the nRST input pin. If the retry attempt continues to fail, then no further recovery is possible. Note that a persistent EEPROM CRC failure indicates a corrupted configuration is present and the device could not be correctly configured anyway. Fix Plan: None Errata # 2: GPIOs Can't Use Input Mode if VCCO = 1.8V Errata: When the VCCO pin adjacent to a GPIO pin is set to 1.8V and the core VCC of the chip is at 3.3V, the GPIO pin will not behave as an input, either a General-Purpose Input or an Output Enable. Mappings are according to the following relationships GPIO0 / VCCO3 GPIO1 / VCCO3 GPIO2 / VCCO4 GPIO3 / VCCO7 GPIO4 / VCCO4 GPIO5 / VCCO5 GPIO6 / VCCO6 GPIO7 / VCCO7 Work-Around: Ensure that voltage used on VCCO pins is no less than VCC - 1.6V. Fix Plan: None ©2019 Integrated Device Technology, Inc. 72 January 28, 2019 8T49N282 Datasheet Revision History Revision Date January 28, 2019 Description of Change • Corrected the I2C read sequence diagrams in Figure 6 and Figure 7 to match I2C specification and device actual performance. Note: Only the drawings were incorrect – the part’s behavior did not change and continues to meet the I2C specification. • Added a Marking Diagram • Updated the Package Outline Drawings; however, no mechanical changes February 2, 2016 Per PCN# W1512-01, Effective Date 03/18/2016 - changed Part/Order Number from 8T49N282B-dddNLGI to 8T49N282C-dddNLGI, and Marking from IDT8T49N282B-dddNLGI to IDT8T49N282C-dddNLGI. Updated Datasheet header/footer. October 2, 2015 Updated pin descriptions for pins 2, 3, 67/68, and 23/24. Output Phase Control on Switchover - added sentence to second and third paragraphs. Added notes to Table 4. AC Characteristics Table - updated Note 5. Updated Figure 16, 8T49N282 Power Domains. July 8, 2015 Device Start-up & Reset Behavior - added second paragraph. May 4, 2015 Thermal Considerations - corrected Table number in paragraph. April 27, 2015 AC Characteristics Table - added missing minimum Output Frequency spec for Q2, Q3 (LVPECL, LVDS) and LVCMOS. Termination for 3.3V LVPECL Outputs - updated Figure 14A. Crystal Recommendation - included additional crystal recommendation. May 29, 2014 Second column, last paragraph; replaced last sentence. Output Phase Alignment; replaced fourth paragraph. Second column, first bullet; changed “VCO period (TVCO)” to “source clock period”. Changed “1 x TVCO” to “250ps”. LVCMOS operation; replaced last sentence. Corrected typo “Femto NG” to FemtoClock NG” (4 places). REV_ID[3:0], fixed typo in default value “00010b” to “0010b”. UFTADD[6:2]; replaced description. UFTADD[1], changed Default Value from “-” to “0b”. Replaced description. UFTADD[0], changed Default Value from “-” to “0b”. Replaced description. 00AB row, replaced “Rsvd” with “10” for D7:D6 and D5:D4. Replaced “tjit()” with “tjit()”. Replaced XTAL_IN and XTAL_OUT with OSCI and OSCO respectively. Changed Q6 Frequency to 125MHz. Changed Q4, Q5 VCCO to 3.3V. Updated calculations. Updated Package Outline drawings. Ordering Information; added pin orientation info. Added Pin 1 Orientation table. Updated Contact Information ©2019 Integrated Device Technology, Inc. 73 January 28, 2019 Revision Date Description of Change April 17, 2014 Renumbered figures with the Block Diagram as Figure 1. Added NOTE 1 to CIN. General-Purpose I/Os & Interrupts section: replaced '0x006E' and '0x0076' with '006Eh' and '0076h'. General-Purpose I/Os & Interrupts section: added last paragraph. SPI Mode Operation: replaced text (3 paragraphs). Figure 1: replaced figure. Figure 1 Title: replaced text ‘SPI Read Timing Diagram’ with ‘SPI Read Sequencing Diagram’. Figure 2: replaced figure. Figure 3: replaced figure. Figure 4: replaced figure. I2C Master Mode, 3rd bullet: replaced '0xE0' with 'E0h'. I2C Master Mode, 4th bullet: replaced '0x05' with '05h'. Text section; replaced '0xE0' with 'E0h'. and ‘0x006’ with ‘006h’. I2C Boot-up Initialization Mode, second paragraph; replaced “The BOOTFAIL bit in the Status Control register will also be set in this event.” with “The BOOTFAIL bit (021Eh) in the Global Interrupt Status register will also be set in this event”. EEPROM Offset (Hex) column; deleted ‘0x’ of 0x## (15 instances). Table Header: deleted ‘(Binary)’ from ‘Default Value”. Replaced values formatting for Default Value column. Outputs, VO (Q[0:7], nQ[0:7]): Changed VCCO to VCCOX. Outputs, VO (GPIO, SDATA, SCLK, nINT): changed GPIO to GPIO[0:7]. Added Note: NOTE: VCCOX denotes VCCO0, VCCO1, VCCO2, VCCO3, VCCO4, VCCO5, VCCO6, VCCO7. Table Header: Changed VCCOX to VCC. ERRATA; 1st paragraph; replaced '0x21F' with '21Fh'. March 7, 2014 Move Pin Assignment from page 9 to page 5. Fixed package drawings on page. March 5, 2014 Applications - updated bullets. Features - added Power Down Mode bullet. Deleted Compliance section. 3.3V Power Supply Table - added test condition to original ICCA spec. Added second spec to ICCA. Updated Note 2. 2.5V Power Supply Table - added test condition to original ICCA spec. Added second spec to ICCA. Updated Note 2. Renumbered Tables starting with Table 9D, and changed to Table 10A. Applications Information, Crystal Recommendation Note - updated Fox part numbers. Revised Power Dissipation and Thermal Considerations section. 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