EVK-UFT285-6-7 Evaluation Board User Guide
USER GUIDE
Introduction
The EVK-UFT285-6-7 is designed to help the customer evaluate the 8T49N285, 8T49N286, and 8T49N287 devices, members
of IDT's 3rd generation Universal Frequency Translator family. When the board is connected to a PC running IDT Timing
Commander™ software through USB, the device can be configured and programmed to generate frequencies with best-in-class
performances.
Contents
The EVK-UFT285-6-7 evaluation board ships with the following:
• 1 – EVK-UFT285-6-7 Evaluation Board
• 1 – USB Cable
Requirements
1. PC Requirements:
• IDT Timing Commander software installed.
• USB 2.0 interface. The evaluation board USB module is not compatible with USB 3.0. If using a computer with high speed
USB ports, please check if there's a standard USB 2.0 port available for use. The hardware drivers are automatically
installed during the Timing Commander installation.
•
•
•
•
•
Windows XP SP3 or later.
Processor: Minimum 1GHz.
Memory: Minimum 512MB, recommended 1GB.
Available Disk Space: Min 600MB (1.5GB 64bit), recommended 1GB (2GB 64bit)
Network access during installation if the .NET framework is not currently installed on the system.
2. Power Supply with 3.3V and 1000mA rating
3. Three banana plug cables to connect the power supply to the board.
Quick Start: Powering Up the Board
(1) Set 3.3V supply current limit to 500mA.
(2) Remove all output terminations.
(3) Set Dip Switch selectors to the middle position.
(4) Connect a cable from a PC to the USB port.
(5) Connect VEE to the black GND jack.
(6) Connect 3.3V to VCC_J and VDDO_J.
(7) Power on the Power Supply.
(8) Press the Reset Button.
Once correct operation is verified, set the power supply limit for the number of outputs to be active.
The USB port must be powered by the PC in order to have the correct I2C bus voltage levels.
The board ships with a 38.88MHz crystal and will have a default frequency of 155.52MHz on Q0. If all outputs are unterminated,
current should measure ~256mA with 3.3V on VCC_J and VDDO_J. If all outputs are terminated, current should measure
~262mA.
When evaluating performance with the default hardware configuration, it is recommended that all active outputs be terminated
50ohms to VEE by either terminator plugs or an instrument.
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©2015 Integrated Device Technology, Inc.
EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Board Overview
Use the following diagram to identify: power supply jacks, USB connector, input and output SMA connectors, reset button,
EEPROM, etc.
Figure 1. Evaluation Board Top View
8T49N286I_EVB
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Legend–Evaluation Board Top View
Inputs
CLK0_S
Clock 0 sense lines.
CLK0
Clock 0 input lines. Can be configured for differential or single-ended input.
CLK1_S
Clock 1 sense lines.
CLK1
Clock 1 input lines. Can be configured for differential or single-ended input.
CLK2
Clock 2 input lines. Can be configured for differential or single-ended input.
CLK3
Clock 3 input lines. Can be configured for differential or single-ended input.
Outputs
Q0
Output Q0. Can be a differential pair or two individual single-ended outputs.
Q1
Output Q1. Can be a differential pair or two individual single-ended outputs
Q2
Output Q2. Can be a differential pair or two individual single-ended outputs.
Q3
Output Q3. Can be a differential pair or two individual single-ended outputs.
Q4
Output Q4. Can be a differential pair or two individual single-ended outputs.
Q5
Output Q5. Can be a differential pair or two individual single-ended outputs.
Q6
Output Q6. Can be a differential pair or two individual single-ended outputs.
Q7
Output Q7. Can be a differential pair or two individual single-ended outputs.
Other
A
Dip Switch for DC control signals (CLK_SEL, PLL_BYPASS, etc)
B
VCCO_J
C
VCC_J
D
GPIOs
E
RESET
F
IDT8T49N286 – the device to be evaluated
G
USB connector
H
EEPROM – AT24CO4C
J
Ground Jack
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Figure 2. Evaluation Board Bottom View
Legend–Evaluation Board Bottom View
X1
3.2 x 2.5 mm SMD Fox-603-38.88-4 Crystal
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Schematics
The following figures are schematics that are applicable to specific sections of this User Guide. The complete schematics are
available in a separate document.
Figure 3. Inputs Schematic
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Figure 4. Output Termination Schematic
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Figure 5. Crystal Interface Schematic
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Figure 6. EEPROM/I2C Schematic
(If the device is programmed to boot from EEPROM, use
R156=0ohm, R131=1Kohm, and do not populate LD10)
(0 ohm in a system
design)
(1K ohm in a
system design)
Figure 7. DC Control Schematic
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Figure 8. VCCO Power Filtering
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Figure 9. VCC Filtering
J6
V C C _J
VC C A _PLL0
BLM18B B221SN 1D
C 15
0. 1u
VC C _J
T p
y
9 5
~
mA
T p
y
9 5
~
mA
C 17
10uF
C 11
10uF
C 13
0. 1u
C 16
10uF
C 18
0. 1u
V C C A_66
VC C A _PLL0
F B2
C 12
10u
C 14
0. 1u
GN D
V C C A_70
VC C A_P LL1
F B10
V C C A_19
C 26
10u
C 65
10uF
C 27
0. 1u
B LM18B B221SN 1D
C 61
0.1u
C 62
10uF
C 66
10u
C 63
0. 1u
C 67
0. 1u
F B18
J14
VC C
V CC
VC C A_P LL1
GN D
GN D
V C C A_71
V C C A_20
C 42
10u
BLM18B B221SN 1D
C 193
0. 1u
C 192
10uF
C 119
10uF
C 76
10u
C 120
0.1u
C 43
0. 1u
C 77
0. 1u
GN D
GN D
GN D
V C C A_72
V C C A_21
C 53
10u
C 55
0. 1u
Co
ls e t o h
t e DU
T
C 87
10u
VC C O0
VC C O1
VC C O2
C 88
0. 1u
V C C O3
GN D
C 103
0.1u
C 104
0. 1u
C 105
0. 1u
C 106
0.1u
GN D
GN D
GN D
GN D
VC C O4
VC C O5
VC C O6
V C C O7
GN D
C 89
10u
C 107
0.1u
C 108
0. 1u
GN D
C 109
0. 1u
GN D
GN D
GN D
GN D
10
J5
C 90
0. 1u
C 110
0.1u
GN D
REVISION B 04/01/15
J4
GN D
VC C A _25
GN D
EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Board Power Supply
Core Voltages
The core voltage includes a digital voltage VDD and an analog voltage VDDA. Both core voltages are powered by the external
bench power supply connected to J6 (VCC_J). See Figure 9 for details
Output Voltages
VDDO_J (J1) supplies the global voltage for the outputs and can be biased by the external power supply at 1.8V (all outputs
LVCMOS), 2.5V, or 3.3V.
Mixed Voltage Operation
This board provides the option to operate the outputs with a mixed combination of output voltages. Refer to Figure 8 for a
complete view of the VCCO schematic. Each VCCOx has a 0 resistor that connects it to the global VCCO_J power rail. This
resistor can be removed and the voltage can be provided using the test point. For example, the schematic below can be
configured so that Q0 (VCCO0) operates at 2.5V and Q4 LVCMOS (VCCO4) operates at 1.8V as follows:
1) Connect 2.5V to J1 (VCCO_J).
2) Remove R146. This isolates VCCO4 from global VCCO_J.
3) Solder a wire onto test point VCCO4 and bias with a 1.8V supply.
Figure 10. Mixed Output Voltage Operation
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EVK-UFT285-6-7 EVALUATION BOARD USER GUIDE
Input Configuration
The inputs are configured with an ac-coupling termination scheme. This scheme allows flexibility for either differential or
single-ended inputs. The default configuration is as follows:
Table 1: Default Input Configuration
Input
Default Termination
Sense Lines
CLK0
50ohms to ground, ac-coupled into the device
Use SMAs J15/J18 for observation of the input signal
CLK1
50ohms to ground, ac-coupled into the device
Available but not connected. Populate R47 and R59 to observe
input signal on SMAs J23/J30
CLK2
50ohms to ground, ac-coupled into the device
Not available
CLK3
50ohms to ground, ac-coupled into the device
Not available
Differential Input
Connect the input signal to CLKx and nCLKx. For CLK0, the CLK0_S and nCLK0_s sense lines are available for observation of
the signal. They can be connected with 50ohm impedance cables to an oscilloscope with 50ohm termination, otherwise, they
should be terminated with 50ohm plugs in order prevent reflections.
Single-ended Input
Connect the input signal to CLKx and float nCLKx. For CLK0, connect CLK0_S with a 50ohm impedance cable to an oscilloscope
with 50ohm termination or terminate with a 50ohm plug.
Input Signals below 1MHz
For slow-frequency signals below 1MHz, we recommend that the coupling capacitors for the corresponding input be replaced
with zero-ohm resistors and that the signal input dc-offset be set so that it meets the device's Vcmr requirements. Refer to Figure
3 to locate the components listed below.
Table 2: Input Termination Schemes
Signal Frequency
AC-coupling capacitors:
CLK0 (C121, C122)
CLK1 (C130,C131)
CLK2 (C150,C151)
CLK3 (C160,C161)
Input Signal DC Offset
>1MHz
1µF
Don't care
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