FemtoClock® NG QUAD Universal
Frequency Translator
8T49N488
DATA SHEET
General Description
Features
The 8T49N488 is a quad PLL with FemtoClock® NG technology, it
integrates low phase noise Frequency Translator / Synthesizer, Jitter
attenuation, and with alarm and monitoring functions suitable for
networking and communications applications. The device has four
fully independent PLLs, each PLL is able to generate any output
frequency in the 0.98MHz - 312.5MHz range and most output
frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for
details). A wide range of input reference clocks and operation
reference clock may be used as the source for the output frequency.
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•
•
Each PLL of 8T49N488 has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
•
Synthesizes output frequencies from an external reference
clock REFCLK.
•
Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
Applications: PCI Express, Computing, General Purpose
•
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
•
Universal Frequency TranslatorTM/Frequency Synthesizer and
Jitter attenuator
Outputs are programmable as LVPECL or LVDS
•
•
•
•
•
•
Input frequency range: 8kHz ~ 710MHz Low-Bandwidth
Programmable output frequency: 0.98MHz up to 1,300MHz
Two differential inputs support the following input levels:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 16MHz ~ 710MHz High-Bandwidth
REFCLK frequency range: 16MHz ~ 40MHz
Input clock monitor and alarm
Smoothed reference switch
Factory-set register configuration for power-up default state
•
•
•
•
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
Power-up default configuration
Configuration customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I2C
I2C Serial interface for register programming
•
RMS phase jitter at 161.1328125MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
•
RMS phase jitter at 400MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 333fs (typical), Synthesizer Mode (Integer FB)
•
•
•
•
Full 2.5V ±5% supply mode
3) Low-Bandwidth Frequency Translator
•
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Four fully independent PLLs
•
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2) High-Bandwidth Frequency Translator
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Fourth generation FemtoClock® NG technology
-40°C to 85°C ambient operating temperature
10mm X 10mm CABGA package
Lead-free (RoHS 6) packaging
Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I2C interface and the
device can be completely reconfigured.
8T49N488 REVISION B 03/23/15
1
©2015 Integrated Device Technology, Inc.
8T49N488 DATA SHEET
Complete Block Diagram
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Pin Descriptions and Pin Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
E5
REFCLK
Input
Pulldown
Reference clock for device operation.
C2, C3
CLK0A,
CLK1A
Input
Pulldown
Non-inverting differential clock input.
D2,
D3
nCLK0A,
nCLK1A
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating (set by the
internal pullup and pulldown resistors).
B7, C7
CLK0B,
CLK1B
Input
Pulldown
Non-inverting differential clock input.
B6,
C6
nCLK0B,
nCLK1B
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating (set by the
internal pullup and pulldown resistors).
G8, G7
CLK0C,
CLK1C
Input
Pulldown
Non-inverting differential clock input.
F8,
F7
nCLK0C,
nCLK1C
Input
Pullup/
Pulldown
Inverting differential clock input. VCC/2 default when left floating (set by the
internal pullup and pulldown resistors).
H3, G3
CLK0D,
CLK1D
Input
Pulldown
Non-inverting differential clock input.
H4,
G4
nCLK0D,
nCLK1D
Input
Pullup/
Pulldown
Inverting differential clock input. VCC2 default when left floating (set by the
internal pullup and pulldown resistors).
B1,A2
Q0A, nQ0A
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
B4, A6
Q1A, nQ1A
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
A9, B9
Q0B, nQ0B
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
D8, F9
Q1B, nQ1B
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
J9, J8
Q0C, nQ0C
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
H6, J4
Q1C, nQ1C
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
J1, H1
Q0D, nQ0D
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
F2, D1
Q1D, nQ1D
Output
Differential output. Output type is programmable to LVDS or LVPECL
interface levels.
A4, A5
LF0A, LF1A
Analog I/O
Loop filter connection node pins.LF0A is the output, LF1A is the input.
D9, E9,
LF0B, LF1B
Analog I/O
Loop filter connection node pins.LF0B is the output, LF1B is the input.
J6, J5
LF0C, LF1C
Analog I/O
Loop filter connection node pins.LF0C is the output, LF1C is the input.
F1, E1
LF0D, LF1D
Analog I/O
Loop filter connection node pins.LF0D is the output, LF1D is the input.
E4
Rsvd
Input
Reserved, connect to VEE
C8
Rsvd
Input
Reserved, connect to VEE
H7
Rsvd
Input
Reserved, connect to VEE
G2
Rsvd
Input
Reserved, connect to VEE
E2
LOCKA
Output
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
C5
LOCKB
Output
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 1. Pin Descriptions
Number
Name
E8
LOCKC
Output
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
H5
LOCKD
Output
Lock Indicator - indicates that the PLL is in a locked condition.
LVCMOS/LVTTL interface levels.
D4
CLK_SELA
Input
Pulldown
Input clock select. Selects the active differential clock input.
0 = CLK0A, nCLK0A (default)
1 = CLK1A, nCLK1A
D6
CLK_SELB
Input
Pulldown
Input clock select. Selects the active differential clock input.
0 = CLK0B, nCLK0B (default)
1 = CLK1B, nCLK1B
F6
CLK_SELC
Input
Pulldown
Input clock select. Selects the active differential clock input.
0 = CLK0C, nCLK0C (default)
1 = CLK1C, nCLK1C
F4
CLK_SELD
Input
Pulldown
Input clock select. Selects the active differential clock input.
0 = CLK0D, nCLK0D (default)
1 = CLK1D, nCLK1D
E6
PLL_BYPAS
S
Input
Pulldown
Bypasses the VCXO PLL.
0 = PLL Mode (default)
1 = PLL Bypassed
G6
SDATA
I/O
Pullup
I2C Data Input/Output. Open drain.
G5
SCLK
Input
Pullup
I2C Clock Input. LVCMOS/LVTTL interface levels.
C1
VCCA_A
Power
Analog power supply for PLLA
C4
VCCO_A
Power
Output power supply for PLLA
B5
VCC_A
Power
Core power supply for PLLA
A7
VCCA_B
Power
Analog power supply for PLLB
D5
VCCO_B
Power
Output power supply for PLLB
D7
VCC_B
Power
Core power supply for PLLB
E7
VCCA_C
Power
Analog power supply for PLLC
G9
VCCO_C
Power
Output power supply for PLLC
F5
VCC_C
Power
Core power supply for PLLC
E3
VCCA_D
Power
Analog power supply for PLLD
J3
VCCO_D
Power
Output power supply for PLLD
F3
VCC_D
Power
Core power supply for PLLD
A3, B2, B3
VEE_A
Power
Negative supply for PLLA
A8, B8, C9
VEE_B
Power
Negative supply for PLLB
H8, H9, J7
VEE_C
Power
Negative supply for PLLC
G1, H2, J2
VEE_D
Power
Negative supply for PLLD
REVISION B 03/23/15
Type
Description
4
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
3.5
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
RPULLDOWN
Input Pulldown
Resistor
REFCLK,
PLL_BYPASS
12.5
k
RPULLUP
Input Pullup
Resistor
SDATA, SCLK
12.5
k
Pin Assignment
J
Q0D
VEE_D
VCCO_D
nQ1C
LF1C
LF0C
VEE_C
nQ0C
Q0C
H
nQ0D
VEE_D
CLK0D
nCLK0D
LOCKD
Q1C
RSVD
VEE_C
VEE_C
G
VEE_D
RSVD
CLK1D
nCLK1D
SCLK
SDATA
CLK1C
CLK0C
VCCO_C
F
LF0D
Q1D
VCC_D
CLK_SELD
VCC_C
CLK_SELC
nCLK1C
nCLK0C
nQ1B
E
LF1D
LOCKA
VCCA_D
RSVD
REFCLK
PLL_BY
PASS
VCCA_C
LOCKC
LF1B
D
nQ1D
nCLK0A
nCLK1A
CLK_SELA
VCCO_B
CLK_SELB
VCC_B
Q1B
LF0B
C
VCCA_A
CLK0A
CLK1A
VCCO_A
LOCKB
NCLK1B
CLK1B
RSVD
VEE_B
B
Q0A
VEE_A
VEE_A
Q1A
VCC_A
nCLK0B
CLK0B
VEE_B
nQ0B
nQ0A
VEE_A
LF0A
LF1A
nQ1A
VCCA_B
VEE_B
Q0B
2
3
4
5
6
7
8
9
A
1
8T49N488 Pin Map (bottom view)
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Functional Description
Output Dividers & Supported Output Frequencies
The 8T49N488 is a four-PLL device. The four PLLs are fully independent and identical. Each PLL can generate desired outputs frequency
(0.98MHz - 1300MHz) from any input source in the operating range
(8kHz - 710MHz). It is capable of synthesizing frequencies from REFCLK source. The output frequency is generated regardless of the relationship to the input frequency. Each PLL of 8T49N488 can
translate the desired output frequency from input clock. In this frequency translation mode, a low-bandwidth, jitter attenuation option is
available that makes use of an external fixed-frequency REFCLK to
translate from a noisy input source. If the input clock is known to be
fairly clean or if some modulation on the input needs to be tracked,
then the high-bandwidth frequency translation mode can be used,
without the need for the external clock source.
The internal VCO is capable of operating in a range anywhere from
1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of
the desired output frequency that results in a VCO operating
frequency within that range. The output divider stage N[10:0] is
limited to selection of integers from 2 to 2046. Please refer to Table 3
for the values of N applicable to the desired output frequency.
Table 3. Output Divider Settings & Frequency Ranges
The input clock references and REFCLK input are monitored
continuously and appropriate alarm outputs are raised by register
bits and hard-wired pins in the event of any out-of-specification
conditions arising. Clock switching is supported in manual, revertive
& non-revertive modes.
Each PLL of 8T49N488 has factory-programmed configuration as the
default operating state after reset. This default may be overwritten by I2C register access at any time, but those over-written
settings will be lost on power-down. Please contact IDT if a specific
set of power-up default settings is desired.
The following sections apply individually to each PLL. Signal and
register bit names have a lowercase ‘x’ on the end where ‘x’ should
be ‘A’, ‘B’, ‘C’ or ‘D’ as appropriate for the PLL being controlled.
Register
Setting
Frequency
Divider
Minimum
fOUT
Maximum
fOUT
Nn[10:0]
N
(MHz)
(MHz)
0000000000x
2
997.5
1300
00000000010
2
997.5
1300
00000000011
3
665
866.7
00000000100
4
498.75
650
00000000101
5
399
520
0000000011x
6
332.5
433.3
0000000100x
8
249.4
325
0000000101x
10
199.5
260
0000000110x
12
166.3
216.7
0000000111x
14
142.5
185.7
0000001000x
16
124.7
162.5
0000001001x
18
110.8
144.4
...
Even N
1995 / N
2600 / N
1111111111x
2046
0.98
1.27
Operating Modes
Each PLL of 8T49N488 has three operating modes which are set by
the MODE_SEL[1:0] bits. There are two frequency translator modes
- low bandwidth and high bandwidth and a frequency synthesizer
mode.
Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configuration of
the device.
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Frequency Synthesizer Mode
This mode of operation allows an arbitrary output frequency to be
generated from external REFCLK input. For improved phase noise
performance, the REFCLK input frequency is doubled. As can be
seen from the block diagram in Figure 1, only the upper feedback
loop is used in this mode of operation. It is recommended that CLK0
and CLK1 be left unused in this mode of operation.
The input reference frequency range is now extended up to 710MHz.
A pre-divider stage P is needed to keep the operating frequencies at
the phase detector within limits.
Low-Bandwidth Frequency Translator Mode
As can be seen from the block diagram in Figure 3, this mode
involves two PLL loops. The lower loop with the large integer dividers
is the low bandwidth loop and it sets the output-to-input frequency
translation ratio.This loop drives the upper DCXO loop (digitally
controlled crystal oscillator) via an analog-digital converter.
The upper feedback loop supports a delta-sigma fractional feedback
divider. This allows the VCO operating frequency to be a non-integer
multiple of the REFCLK frequency. By using an integer multiple only,
lower phase noise jitter on the output can be achieved, however the
use of the delta-sigma divider logic will provide excellent
performance on the output if a fractional divisor is used.
Figure 3. Low Bandwidth Frequency Translator Mode
Block Diagram
The phase detector of the lower loop is designed to work with
frequencies in the 8kHz - 16kHz range. The pre-divider stage is used
to scale down the input frequency by an integer value to achieve a
frequency in this range. By dividing down the fed-back VCO
operating frequency by the integer divider M1[18:0] to as close as
possible to the same frequency, exact output frequency translations
can be achieved.
Figure 1. Frequency Synthesizer Mode Block Diagram
High-Bandwidth Frequency Translator Mode
This mode of operation is used to translate one of two input clocks of
the same nominal frequency into an output frequency. As can be
seen from the block diagram in Figure 2, similarly to the Frequency
Synthesizer mode, only the upper feedback loop is used.
Alarm Conditions & Status Bits
Each PLL of 8T49N488 monitors a number of conditions and reports
their status via both output pins and/or register bits. All alarms will
behave as indicated below in all modes of operation, but some of the
conditions monitored have no valid meaning in some operating
modes. For example, the status of CLK0BAD, CLK1BAD and
CLK_ACTIVE are not relevant in Frequency Synthesizer mode. The
outputs will still be active and it is left to the user to determine which
to monitor and how to respond to them based on the known operating
mode.
CLK_ACTIVE - indicates which input clock reference is being used to
derive the output frequency.
LOCK - This status is asserted on the pin & register bit when the PLL
is locked to the appropriate input reference for the chosen mode of
operation. The status bit will not assert until frequency lock has been
achieved, but will de-assert once lock is lost.
Figure 2. High Bandwidth Frequency Translator Mode
Block Diagram
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
REFBAD - indicates if valid edges are being received on the REFCLK
input. Detection is performed by comparing the input to the feedback
signal at the upper loop’s Phase / Frequency Detector (PFD). If three
edges are received on the feedback without an edge on the REFCLK
input, the REFBAD alarm is asserted in register bit. Once an edge is
detected on the REFCLK input, the alarm is immediately deasserted.
Each PLL of 8T49N488 will only switch input references on command
from the user. The user must either change the CLK_SEL register bit
(if in Manual via Register) or CLK_SEL input pin (if in Manual via Pin).
Automatic Switching Mode
When the AUTO_MAN[1:0] field is set to either of the automatic
selection modes (Revertive or Non-Revertive), each PLL of
8T49N488 determines which input reference it prefers / starts from by
the state of the CLK_SEL register bit only. The CLK_SEL input pin is
not used in either Automatic switching mode.
CLK0BAD - indicates if valid edges are being received on the CLK0
reference input. Detection is performed by comparing the input to the
feedback signal at the appropriate Phase / Frequency Detector
(PFD). When operating in high-bandwidth mode, the feedback at the
upper PFD is used. In low-bandwidth mode, the feedback at the lower
PFD is used. If three edges are received on the feedback without an
edge on the divided down (÷P) CLK0 reference input, the CLK0BAD
alarm is asserted on register bit. Once an edge is detected on the
CLK0 reference input, the alarm is deasserted.
When starting from an unlocked condition, the device will lock to the
input reference indicated by the CLK_SEL register bit. It will not pay
attention to the non-selected input reference until a locked state has
been achieved. This is necessary to prevent ‘hunting’ behavior during
the locking phase.
CLK1BAD - indicates if valid edges are being received on the CLK1
reference input. Behavior is as indicated for the CLK0BAD alarm, but
with the CLK1 input being monitored and the CLK1BAD register bits
being affected.
Once the PLL of 8T49N488 has achieved a stable lock, it will remain
locked to the preferred input reference as long as there is a valid clock
on it. If at some point, that clock fails, then the device will
automatically switch to the other input reference as long as there is a
valid clock there. If there is not a valid clock on either input reference,
each PLL of 8T49N488 will go into holdover (Low Bandwidth
Frequency Translator mode) or free-run (High Bandwidth Frequency
Translator mode) state. In either case, the HOLDOVER alarm will be
raised.
HOLDOVER - indicates that the device is not locked to a valid input
reference clock. This can occur in Manual switchover mode if the
selected reference input has gone bad, even if the other reference
input is still good. In automatic mode, this will only assert if both input
references are bad.
The PLL will recover from holdover / free-run state once a valid clock
is re-established on either reference input. If clocks are valid on both
input references, the device will choose the reference indicated by
the CLK_SEL register bit.
Input Reference Selection and Switching
When operating in Frequency Synthesizer mode, the CLK0 and
CLK1 inputs are not used and the contents of this section do not
apply. Except as noted below, when operating in either High or Low
Bandwidth Frequency Translator mode, the contents of this section
apply equally when in either of those modes.
If running from the non-preferred input reference and a valid clock
returns, there is a difference in behavior between Revertive and
Non-revertive modes. In Revertive mode, the device will switch back
to the reference indicated by the CLK_SEL register bit even if there
is still a valid clock on the non-preferred reference input. In
Non-revertive mode, each PLL 8T49N488 will not switch back as long
as the non-preferred input reference still has a valid clock on it.
Both input references CLK0 and CLK1 must be the same nominal
frequency. These may be driven by any type of clock source. A
difference in frequency may cause the PLL to lose lock when
switching between input references. Please contact IDT for the exact
limits for your situation.
Switchover Behavior of the PLL
Even though the two input references have the same nominal
frequency, there may be minor differences in frequency and
potentially large differences in phase between them. Each PLL of
8T49N488 will adjust its output to the new input reference. It will use
Phase Slope Limiting to adjust the output phase at a fixed maximum
rate until the output phase and frequency are now aligned to the new
input reference. Phase will always be adjusted by extending the clock
period of the output so that no unacceptably short clock periods are
generated on the output.
TEach PLL has global control bits AUTO_MAN[1:0] to dictate the
order of priority and switching mode to be used between the CLK0
and CLK1 inputs.
Manual Switching Mode
When the AUTO_MAN[1:0] field is set to Manual via Pin, then each
PLL of 8T49N488 will use the CLK_SEL input pin to determine which
input to use as a reference. Similarly, if set to Manual via Register,
then the device will use the CLK_SEL register bit to determine the
input reference. In either case, the PLL will lock to the selected
reference if there is a valid clock present on that input.
Holdover / Free-run Behavior
When both input references have failed (Automatic mode) or the selected input has failed (Manual mode), each PLL of 8T49N488 will
enter holdover (Low Bandwidth Frequency Translator mode) or
free-run (High Bandwidth Frequency Translator mode) state if. In
both cases, once the input reference is lost, the PLL will stop making
adjustments to the output phase.
If there is not a valid clock present on the selected input, each PLL of
8T49N488 will go into holdover (Low Bandwidth Frequency
Translator mode) or free-run (High Bandwidth Frequency Translator
mode) state. In either case, the HOLDOVER alarm will be raised.
This will occur even if there is a valid clock on the non-selected
reference input. The device will recover from holdover / free-run state
once a valid clock is re-established on the selected reference input.
REVISION B 03/23/15
8
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Serial Interface Configuration Description
If operating in Low Bandwidth Frequency Translation mode, the PLL
will continue to reference itself to the local reference and will hold its
output phase and frequency in relation to that source. Output stability
is determined by the stability of the local reference REFCLK in this
case.
The 8T49N488 has an I2C-compatible configuration interface to access any of the internal registers (Table 4D) for frequency and PLL
parameter programming. Each PLL acts as a slave device on the I2C
bus and has the address 0b11011xx, where xx is set to fixed value by
A0 & A1 (see Table 4A for details). The interface accepts byte-oriented block write and block read operations. An address byte (P) specifies the register address (Table 4D) as the byte position of the first
register to write or read. Data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit
first, see table 4B, 4C). Read and write block transfers can be stopped after any complete byte transfer. It is recommended to terminate
I2C the read or write transfer after accessing byte #23 of each PLL.
However, if operating in High Bandwidth Frequency Translation
mode, the PLL no longer has any frequency reference to use and output stability is now determined by the stability of the internal VCO.
If the device is programmed to perform Manual switching, once the
selected input reference recovers, the 8T49N488 will switch back to
that input reference. If programmed for either Automatic mode, the
device will switch back to whichever input reference has a valid clock
first.
For full electrical I2C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK.
Output Configuration
Note: If a different device slave address is desired, please contact
IDT.
The two outputs of each PLL both provide the same clock frequency.
The two outputs are individually selectable as LVDS or LVPECL output types via the Q0_TYPE and Q1_TYPE register bits. when the
output is disabled, it will show a high impedance condition.
Table 4A. I2C Device Slave Address
A6
A5
A4
A3
A2
A1
A0
R/W
PLL-A
1
1
0
1
1
0
0
R/W
PLL-B
1
1
0
1
1
0
1
R/W
PLL-C
1
1
0
1
1
1
0
R/W
PLL-D
1
1
0
1
1
1
1
R/W
Table 4B. Block Write Operation
Bit
Description
1
2:8
9
10
11:18
19
20:27
28
29-36
37
...
...
...
START
Slave
Address
W (0)
ACK
Address
Byte (P)
ACK
Data Byte
(P)
ACK
Data Byte
(P+1)
ACK
Data Byte
...
ACK
STOP
1
7
1
1
8
1
8
1
8
1
8
1
1
Length (bits)
Table 4C. Block Read Operation
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39-46
47
...
...
...
Description
START
Slave
Address
W
(0)
A
C
K
Address
Byte (P)
A
C
K
Repeate
d START
Slave
Address
R
(1)
A
C
K
Data
Byte (P)
A
C
K
Data
Byte
(P+1)
A
C
K
Data
Byte
...
A
C
K
STOP
Length (bits)
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
REVISION B 03/23/15
9
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Register Descriptions
Please consult IDT fro configuration software and/or guides to assist
in selection of optimal register settings for the desired configurations.
The below register map applies to each PLL.
Table 4D. I2C Register Map
Reg
Binary
Register
Address
Register Bit
D7
D6
D5
D4
D3
D2
D1
D0
0
00000
MFRACx[17]
MFRACx[16]
MFRACx[15]
MFRACx[14]
MFRACx[13]
MFRACx[12]
MFRACx[11]
MFRACx[10]
1
00001
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
2
00010
MFRACx[9]
MFRACx[8]
MFRACx[7]
MFRACx[6]
MFRACx[5]
MFRACx[4]
MFRACx[3]
MFRACx[2]
3
00011
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
4
00100
MFRACx[1]
MFRACx[0]
MINTx[7]
MINTx[6]
MINTx[5]
MINTx[4]
MINTx[3]
MINTx[2]
5
00101
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
6
00110
MINTx[1]
MINTx[0]
Px[16]
Px[15]
Px[14]
Px[13]
Px[12]
Px[11]
7
00111
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
8
01000
Px[10]
Px[9]
Px[8]
Px[7]
Px[6]
Px[5]
Px[4]
Px[3]
9
01001
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
10
01010
Px[2]
Px[1]
Px[0]
M1_x[16]
M1_x[15]
M1_x[14]
M1_x[13]
M1_x[12]
11
01011
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
12
01100
M1_x[11]
M1_x[10]
M1_x[9]
M1_x[8]
M1_x[7]
M1_x[6]
M1_x[5]
M1_x[4]
13
01101
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
14
01110
M1_x[3]
M1_x[2]
M1_x[1]
M1_x[0]
Nx[10]
Nx[9]
Nx[8]
Nx[7]
15
01111
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
16
10000
Nx[6]
Nx[5]
Nx[4]
Nx[3]
Nx[2]
Nx[1]
Nx[0]
BWx[6]
17
10001
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
18
10010
BWx[5]
BWx[4]
BWx[3]
BWx[2]
BWx[1]
BWx[0]
Q1_TYPEx
Q0_TYPEx
19
10011
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
20
10100
MODE_SELx[1]
MODE_SELx[0]
0
1
OE1_x
OE0_x
Rsvd
Rsvd
21
10101
CLK_SELx
AUTO_MANx[1]
AUTO_MANx[0]
0
ADC_RATEx[1]
ADC_RATEx[0]
LCK_WINx[1]
LCK_WINx[0]
22
10110
1
0
1
0
DBL_REFCLKx
0
0
1
23
10111
CLK_ACTIVEx
HOLDOVERx
CLK1BADx
CLK0BADx
REFBADx
LOCKx
Rsvd
Rsvd
NOTE: X denotes: A, B, C or D.
REVISION B 03/23/15
10
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 4E. Configuration-Specific Control Bits
Register Bits
Function
Q0_TYPEx
Determines the output type for output pair Q0, nQ0 for PLLx.
0 = LVPECL
1 = LVDS
Q1_TYPEx
Determines the output type for output pair Q1, nQ1 for PLLx.
0 = LVPECL
1 = LVDS
Px[16:0]
Reference Pre-Divider for PLLx.
M1_x[16:0]
Integer Feedback Divider in Lower Feedback Loop for PLLx.
M_INTx[7:0]
Feedback Divider, Integer Value in Upper Feedback Loop for PLLx.
M_FRACx[17:0]
Feedback Divider, Fractional Value in Upper Feedback Loop for PLLx.
Nx[10:0]
Output Divider for PLLx.
BWx[6:0]
Internal Operation Settings for PLLx.
Please use IDT 8T49N488 Configuration Software to determine the correct settings for these bits for the specific
configuration. Alternatively, please consult with IDT directly for further information on the functions of these bits.The
function of these bits are explained in Tables 4H and 4I.
Table 4F. Global Control Bits
Register Bits
MODE_SELx[1:0]
Function
PLL Mode Select for PLLx.
00 = Low Bandwidth Frequency Translator
01 = Frequency Synthesizer
10 = High Bandwidth Frequency Translator
11 = High Bandwidth Frequency Translator
OE0_x
Output Enable Control for Output 0 for PLLx.
0 = Output Q0, nQ0 disabled
1 = Output Q0, nQ0 enabled
OE1_x
Output Enable Control for Output 1 for PLLx.
0 = Output Q1, nQ1 disabled
1 = Output Q1, nQ1 enabled
Rsvd
AUTO_MANx[1:0]
CLK_SELx
Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed
Selects how input clock selection is performed for PLLx.
00 = Manual Selection via pin only
01 = Automatic, non-revertive
10 = Automatic, revertive
11 = Manual Selection via register only
In manual clock selection via register mode for PLLx, this bit will command which input clock is selected. In the
automatic modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect.
0 = CLK0
1 = CLK1
ADC_RATEx[1:0]
Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the REFCLK input frequency for PLLx.
00 = REFCLK Frequency 16 when doubler is disabled
01 = REFCLK Frequency 8 when doubler is disabled
10 = REFCLK Frequency 4 (recommended) when doubler is disabled
11 = REFCLK Frequency 2 when doubler is disabled
LCK_WINx[1:0]
Sets the width of the window in which a new reference edge must fall relative to the feedback edge for PLLx.
00 = 2sec (recommended)
01 = 4sec
10 = 8sec
11 = 16sec
DBL_REFCLKx
When set, this bit will double the frequency of the REFCLK input before applying it to the Phase-Frequency
Detector for PLLx.
REVISION B 03/23/15
11
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 4G. Global Status Bits
Register Bits
Function
CLK0BADx
Status Bit for input clock 0 for PLLx.
0 = input CLK0 good
1 = input bad. Self clears when input clock returns to good status
CLK1BADx
Status Bit for input clock 1 for PLLx.
0 = input CLK1 good
1 = input bad. Self clears when input clock returns to good status
REFBADx
Status Bit for PLLx.
0 = REFCLK input good
1 = REFCLK input bad. Self-clears when the REFCLK clock returns to good status
LOCKx
Status bit for PLLx. This bit is mirrored on LOCKx pin.
0 = PLL unlocked
1 = PLL locked
HOLDOVERx
Status Bit for PLLx.
0 = Input to phase detector is within specifications and device is tracking to it
1 = Phase detector input not within specifications and DCXO is frozen at last value
CLK_ACTIVEx
Status Bit for PLLx. Indicates which input clock is active. Automatically updates during fail-over switching.
Table 4H. BW[6:0] Bits
Mode
Synthesizer Mode
BWx[6]
BWx[5]
BWx[4]
BWx[3]
BWx[2]
BWx[1]
BWx[0]
PLL2_LFx[1]
PLL2_LFx[0]
DSM_ORDx
DSM_ENx
PLL2_CPx[1]
PLL2_CPx[0]
PLL2_LOW_LCPx
High-Bandwidth Mode
PLL2_LFx[1]
PLL2_LFx[0]
DSM_ORDx
DSM_ENx
PLL2_CPx[1]
PLL2_CPx[0]
PLL2_LOW_LCPx
Low-Bandwidth Mode
ADC_GAINx[3]
ADC_GAINx[2]
ADC_GAINx[1]
ADC_GAINx[0]
PLL1_CPx[1]
PLL1_CPx[0]
PLL2_LOW_LCPx
Table 4I. Functions of Fields in BW[6:0]
Register Bits
Function
PLL2_LFx[1:0]
Sets loop filter values for upper loop PLL in Frequency Synthesizer & High-Bandwidth modes for PLLx.
Defaults to setting of 00 when in Low Bandwidth Mode. See Table 4J for settings.
DSM_ORDx
DSM_ENx
PLL2_CPx[1:0]
Sets Delta-Sigma Modulation to 2nd (0) or 3rd order (1) operation for PLLx.
Enables Delta-Sigma Modulator for PLLx.
0 = Disabled - feedback in integer mode only
1 = Enabled - feedback in fractional mode
Upper loop PLL charge pump current settings for PLLx.
00 = 173A (defaults to this setting in Low Bandwidth Mode)
01 = 346A
10 = 692A
11 = reserved
PLL2_LOW_Icpx
Reduces Charge Pump current by 1/3 to reduce bandwidth variations resulting from higher feedback register
settings or high VCO operating frequency (>2.4GHz) for PLLx.
ADC_GAINx[3:0]
Gain setting for ADC in Low Bandwidth Mode.
PLL1_CPx[1:0]
REVISION B 03/23/15
Lower loop PLL charge pump current settings (lower loop is only used in Low Bandwidth Mode) for PLLx.
00 = 800A
01 = 400A
10 = 200A
11 = 100A
12
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 4J. Upper Loop (PLL2) Bandwidth Settings
Desired
Bandwidth
PLL2_CP
PLL2_LOW
_ICP
200kHz
00
1
00
400kHz
01
1
01
800kHz
10
1
10
2MHz
10
1
11
PLL2_LF
Frequency Synthesizer Mode
High Bandwidth Frequency Translator Mode
200kHz
00
1
00
400kHz
01
1
01
800kHz
10
1
10
4MHz
10
0
11
NOTE: To achieve 4MHz bandwidth, reference to the phase detector should be 80MHz.
REVISION B 03/23/15
13
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.6V
Inputs, VI
-0.5V to VCC_X + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VCCO_X + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, JA
12.4C/W (0 mps)
Package Thermal Impedance, JC
12.5C/W (0 mps)
Storage Temperature, TSTG
-65C to 150C
DC Electrical Characteristics
Table 5A. LVPECL Power Supply DC Characteristics, VCC_X = VCCO_X = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
VCC_X
Core Supply Voltage
VCCA_X
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
Analog Supply Voltage
VCC_X – 0.26
2.5
VCC_X
V
VCCO_X
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
1127
mA
ICCA
Analog Supply Current
104
mA
NOTE: X denotes: A, B, C or D.
Table 5B. LVDS Power Supply DC Characteristics, VCC_X = VCCO_X = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VCC_X
Core Supply Voltage
VCCA_X
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
Analog Supply Voltage
VCC_X – 0.26
2.5
VCC_X
V
VCCO_X
Output Supply Voltage
2.375
2.5
2.625
V
IEE
Power Supply Current
956
mA
ICCA
Analog Supply Current
104
mA
ICCO
Output Supply Current
168
mA
NOTE: X denotes: A, B, C or D.
REVISION B 03/23/15
14
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 5C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
VIH
Input High Voltage
VCC_X = 2.5V
VIL
Input Low Voltage
VCC_X = 2.5V
IIH
Input
High Current;
NOTE 1
IIL
Input
Low Current;
NOTE 1
Typical
Maximum
Units
1.7
VCC + 0.3
V
-0.3
0.7
V
PLL_BYPASS,
REFCLK,
CLK_SELx
VCC_X = VIN = 2.625V
150
µA
SCLK, SDATA
VCC_X = VIN = 2.625V
5
µA
PLL_BYPASS,
REFCLK,
CLK_SELx
VCC_X = 2.625V, VIN = 0V
-5
µA
SCLK, SDATA
VCC_X = 2.625V, VIN = 0V
-150
µA
1.8
V
VOH
Output
High Voltage
SDATA,
LOCKx
VCCO_X = 2.625V, IOH = -8mA
VOL
Output
Low Voltage
SDATA,
LOCKx
VCCO_X = 2.625V, IOH = 8mA
0.5
V
NOTE: X denotes: A, B, C or D.
NOTE 1: For PLL_BYPASS, REFCLK, SCLK and SDATA pins, specification is for each individual PLL and is guaranteed by design. Production
Test is performed with all PLLs combined.
Table 5D. Differential DC Characteristics, VCC_X = VCCO_X = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
IIH
IIL
Parameter
Input
High Current
Input
Low Current
Test Conditions
Minimum
Typical
Maximum
Units
150
µA
CLK0[A:D],
nCLK0[A:D],
CLK1[A:D],
nCLK1[A:D],
VCC_X = VIN = 2.625V
CLK0[A:D],
CLK1[A:D],
VCC_X= 2.625V, VIN = 0V
-5
µA
nCLK0[A:D],
nCLK1[A:D]
VCC_X =2.625V, VIN = 0V
-150
µA
VPP
Peak-to-Peak Voltage
0.15
1.3
V
VCMR
Common Mode Input
Voltage; NOTE 1
VEE + 0.5
VCC – 1.0
V
Maximum
Units
NOTE: X denotes: A, B, C or D.
NOTE 1: Common mode input voltage is defined at the crosspoint.
Table 5E. LVPECL DC Characteristics, VCC_X = VCCO_X = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VOH
Output High Voltage; NOTE 1
VCCO _X – 1.1
VCCO _X – 0.7
V
VOL
Output Low Voltage NOTE 1
VCCO _X – 2.0
VCCO _X – 1.5
V
VSWING
Peak-to-Peak Output Voltage
Swing
0.6
1.0
V
NOTE: X denotes: A, B, C or D.
NOTE 1: Outputs terminated with 50 to VCCO_X – 2V.
REVISION B 03/23/15
15
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Table 5F. LVDS DC Characteristics, VCC_X = VCCO_X = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VOD
Differential Output Voltage
VOD
VOD Magnitude Change
VOS
Offset Voltage
VOS
VOS Magnitude Change
Minimum
Typical
Maximum
Units
454
mV
50
mV
1.375
V
50
mV
Maximum
Units
16
40
MHz
High Bandwidth Mode
16
710
MHz
Low Bandwidth Mode
0.008
710
MHz
5
MHz
247
1.125
NOTE: X denotes: A, B, C or D.
Table 6. Input Frequency Characteristics, VCC_X = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
REFCLK
fIN
Input
Frequency;
NOTE 1
CLK0[A:D],
nCLK0[A:D],
CLK1[A:D],
nCLK1[A:D],
SCLK
Minimum
Typical
NOTE: X denotes: A, B, C or D.
NOTE 1: For the input REFCLK and CLK0x, nCLK0x, CLK1x, nCLK1x frequency range, the M value must be set for the VCO to operate within
the 1995MHz to 2600MHz range.
REVISION B 03/23/15
16
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
AC Electrical Characteristics
Table 7. AC Characteristics, VCC_X = VCCO_X = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C*
Symbol
Parameter
fOUT
Output Frequency
0.98
1300
MHz
fVCO
VCO Frequency
1995
2600
MHz
tjit(Ø)
Test Conditions
RMS Phase Jitter
(Random),
Integer Divide Ratio
NOTE 1
tjit(cc)
Cycle-to-Cycle Jitter;
NOTE 2, 3
tR / tF
Output
Rise/Fall Time;
NOTE 3
odc
Minimum
Typical
Maximum
Units
Synth Mode (Integer FB),
fOUT = 400MHz, 40MHz REFCLK,
Integration Range: 12kHz – 20MHz
333
435
fs
Synth Mode (FracN FB),
fOUT = 698.81MHz, 40MHz REFCLK,
Integration Range: 12kHz – 20MHz
408
665
fs
HBW Mode,
fIN = 133.33MHz, fOUT = 400MHz,
Integration Range: 12kHz – 20MHz
338
490
fs
LBW Mode (near integer), 40MHz REFCLK,
fIN = 19.44MHz, fOUT = 622.08MHz,
Integration Range: 12kHz – 20MHz
444
680
fs
LBW Mode (FracN), 40MHz REFCLK,
fIN = 25MHz, fOUT = 161.1328125MHz,
Integration Range: 12kHz – 20MHz
465
680
fs
Frequency Synthesizer Mode
35
ps
Frequency Translator Mode
40
ps
LVPECL
Outputs
20% to 80%
100
520
ps
LVDS
Outputs
20% to 80%
100
520
ps
fOUT < 600MHz
45
55
%
fOUT 600MHz
40
60
%
Output Duty Cycle; NOTE 3
NOTE: X denotes: A, B, C or D.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: For RMS Phase Jitter measurement in Synth and HBW mode, all four PLLs are programmed with the same configuration. For the
LBW mode. only the PLL under test is programmed with LBW configuration, the other PLLs are programmed with Synth mode with the same
output frequency. A Rohde & Schwarz SMA-100 signal generator, 9kHz – 6GHz, is used as the REFLCK source. All configurations are with
DBL_REFCLK bit set to 1.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Measurements are collected with the following output frequency: 66.6667MHz, 125MHz, 156.25MHz, 161.138125MHz, 400MHz,
622.08MHz, 698.81MHz, 1300MHz.
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Noise Power dBc / Hz
Typical Phase Noise at 400MHz (HBW Mode)
Offset Frequency (Hz)
REVISION B 03/23/15
18
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Parameter Measurement Information
2V
2V
2.5V±5%
POWER SUPPLY
+ Float GND –
VCC_X,
,
V
CCO_X
VCCA_X
VCC_X,
SCOPE
VCCO_X
Qx
VCCA_X
nQx
-0.5V±0.125V
VCCA_X, the “X” denotes A, B, C, D
VCCA_X, the “X” denotes A, B, C, D
2.5V Core/2.5V LVPECL Output Load Test Circuit
2.5V Core/2.5V LVDS Output Load Test Circuit
VCC_X
nCLKx
CLKx
VEE
RMS Phase Jitter
Differential Input Levels
nQx
nQx
Qx
Qx
tcycle n
tcycle n+1
tjit(cc) = |tcycle n – tcycle n+1|
1000 Cycles
Differential Output Duty Cycle/Output Pulse Width/Period
Cycle-to-Cycle Jitter
REVISION B 03/23/15
19
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8T49N488 DATA SHEET
Parameter Measurement Information, continued
nQx
nQx
80%
80%
VOD
Qx
20%
20%
tR
Qx
tF
LVDS Output Rise/Fall Time
LVPECL Output Rise/Fall Time
Offset Voltage Setup
Differential Output Voltage Setup
REVISION B 03/23/15
20
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLKx/nCLKx Inputs
LVPECL Outputs
For applications not requiring the use of either differential input, both
CLKx and nCLKx can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLKx to ground.
It is recommended that CLKx, nCLKx be left unconnected in
frequency synthesizer mode.
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating there should be no trace
attached.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
Recommended Values for Low-Bandwidth Mode Loop Filter
External loop filter components are not needed in Frequency
Synthesizer or High-Bandwidth modes. In Low-Bandwidth mode, the
loop filter structure and components are recommended, refer to the
Application Schematic. Please consult IDT if other values are
needed.
REVISION B 03/23/15
21
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Wiring the Differential Input to Accept Single-Ended Levels
Figure 4 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VCC/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2
value should be adjusted to set V1 at 1.25V. The values below are for
when both the single ended swing and VCC are at the same voltage.
This configuration requires that the sum of the output impedance of
the driver (Ro) and the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
impedance. For most 50 applications, R3 and R4 can be 100. The
values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VCC + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
VCC
VCC
VCC
VCC
R3
100
Ro
RS
R1
1K
Zo = 50 Ohm
+
Driver
V1
R4
Ro + Rs = Zo
Receiv er
-
100
C1
0.1uF
R2
1K
Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
REVISION B 03/23/15
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8T49N488 DATA SHEET
Differential Clock Input Interface
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 5A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
The CLKx /nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 5A to 5E show interface
examples for the CLKx /nCLKx inputs driven by the most common
driver types. The input interfaces suggested here are examples only.
2.5V
1.8V
Zo = 50
CLK
Zo = 50
nCLK
Differential
Input
LVHSTL
R1
50
IDT Open Emitter
LVHSTL Driver
R2
50
Figure 5A. CLKx/nCLKx Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 5B. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 5C. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 5D. CLKx/nCLKx Input Driven by a
2.5V LVDS Driver
2.5V
2.5V
*R3
33
Zo = 50
CLK
Zo = 50
nCLK
HCSL
*R4
33
R1
50
R2
50
Differential
Input
*Optional – R3 and R4 can be 0
Figure 5E. CLKx/nCLKx Input Driven by a
2.5V HCSL Driver
REVISION B 03/23/15
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8T49N488 DATA SHEET
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
LVDS
Driver
standard termination schematic as shown in Figure 6A can be used
with either type of output structure. Figure 6B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
ZO ZT
ZT
LVDS
Receiver
Figure 6A. Standard Termination
LVDS
Driver
ZO ZT
C
ZT
2 LVDS
ZT Receiver
2
Figure 6B. Optional Termination
REVISION B 03/23/15
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8T49N488 DATA SHEET
Termination for 2.5V LVPECL Outputs
ground level. The R3 in Figure 7B can be eliminated and the
termination is shown in Figure 7C.
Figure 7A and Figure 7B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCCO_X – 2V. For VCCO_X = 2.5V, the VCCO _X – 2V is very close to
2.5V
VCCO = 2.5V
2.5V
2.5V
VCCO = 2.5V
R1
250
R3
250
50
+
50
+
50
–
50
2.5V LVPECL Driver
–
R1
50
2.5V LVPECL Driver
R2
62.5
R2
50
R4
62.5
R3
18
Figure 7A. 2.5V LVPECL Driver Termination Example
Figure 7B. 2.5V LVPECL Driver Termination Example
2.5V
VCCO = 2.5V
50
+
50
–
2.5V LVPECL Driver
R1
50
R2
50
Figure 7C. 2.5V LVPECL Driver Termination Example
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8T49N488 DATA SHEET
Schematic Layout
Figure 8 (next page) shows an example 8T49N488i application
schematic. The schematic example focuses on functional
connections and is not configuration specific. Refer to the pin
description and functional tables in the datasheet to ensure that
PLL_BYPASS and CLK_SEL_x pins are properly set. Input and
output terminations shown are intended as examples only and may
not match the exact user application. To promote readability in this
schematic, only Jitter Attenuator B and the global pins PLL_BYPASS,
REF_CLK and SDATA and SCLK are shown connected. Jitter
Attenuators A, C and D are recommended to be connected similarly
to Jitter Attenuator B, however different connections may be used; the
four jitter attenuators are fully independent
In order to achieve the best possible filtering, it is highly
recommended that the 0.1µF capacitors on the device side of the
ferrite beads be placed on the device side of the PCB as close to the
power pins as possible. This is represented by the placement of
these capacitors in the schematic. If space is limited, the ferrite
beads, 10µf and 0.1µF capacitor connected to 2.5V can be placed on
the opposite side of the PCB. If space permits, place all filter
components on the device side of the board.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The 8T49N488i provides separate
VCC, VCCA and VCCO power supplies for each jitter attenuator to
isolate any high switching noise from coupling into the internal PLLs.
REVISION B 03/23/15
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8T49N488 DATA SHEET
PLL_BYPASS Control Input Examples
VCC
Set Logic
Input to '1'
Set Logic
Input to '0'
V CC
R U1
1k
Frequency Tra nslators A , C and D
not connected for clari ty
RU2
N ot In s tal l
To Logic
Input
pins
To Logic
Input
pins
R D1
N ot I ns t all
RD2
1k
2. 5V
FB 2
2
V C C _B
C 10
1
B LM18B B221S N 1
P LL_BY PA S S
2. 5V
C9
0. 1uF
10 uF
U1
Ro
= 7 Oh m
R 11
Zo = 50 Ohm
E6
E5
G6
G5
43
D riv er_LV C M OS
PLL_B Y P A SS
R E FC L K
Rsv
Rsv
Rsv
Rsv
SD ATA
SC LK
d
d
d
d
D4
C LK _SE L_A
V C C _A
V C C A_A
V C C O_A
2. 5V
A5
A4
R2
4. 7k
LF1_A
LF0_A
V E E_A
V E E_A
V E E_A
R 15
4. 7k
C2
D2
C3
D3
C LK 0_A
nC LK 0_A
Q0_A
nQ0_A
C LK 1_A
nC LK 1_A
Q1_A
nQ1_A
D6
C LK _SE L_B
C LK _SE L_B
E9
LF _I N
LF _OU T D 9
V C C _B
V C C A_B
V C C O_B
LF1_B
LF0_B
V E E_B
V E E_B
V E E_B
R 28 220k
R 29
470k
B7
B6
C LK 1_B
nC LK 1_B
C7
C6
J5
J6
Zo = 50 Ohm
C LK 0_B
C LK 0_B
nC LK 0_B
Q0_B
nQ0_B
C LK 1_B
nC LK 1_B
Q1_B
nQ1_B
C LK _SE L_C
VC C _C
V C C A _C
V C C O _C
LF1_C
LF0_C
VE E _C
VE E _C
VE E _C
2. 5V
FB 1
2
V C C O _B
A3
B2
B3
C 11
E2
10uF
1
B LM18B B221S N 1
C8
0. 1uF
B1
A2
B4
A6
Plac e 0 .1uF byp ass cap
dire ctl y ad jace nt t o t he
corr esp ondi ng V CC p in.
D7
A7
D5
V C C _B
VC C A _B
V C C O _B
A8
B8
C9
C7
0. 1uF
C5
0. 1uF
C4
0. 1uF
G7
F7
Zo = 50 Ohm
LOC K_B
A9
B9
Q0_B
nQ0_B
D8
F9
Q1_B
nQ1_B
F5
E7
G9
H8
H9
J7
C LK 1_B
C LK 0_C
nC LK 0_C
Q 0_C
nQ 0_C
C LK 1_C
nC LK 1_C
Q 1_C
nQ 1_C
F4
C LK _SE L_D
VC C _D
V C C A _D
V C C O _D
Zo = 50 Ohm
nC LK 1_B
E1
F1
R 23
50
+
R 27
100
Z o = 50 O hm
nQ0_B
-
LF1_D
LF0_D
VE E _D
VE E _D
VE E _D
H6
J4
G3
G4
C LK 0_D
nC LK 0_D
Q 0_D
nQ 0_D
C LK 1_D
nC LK 1_D
Q 1_D
nQ 1_D
Z o = 50 O hm
Q1_B
F3
E3
J3
+
Z o = 50 O hm
nQ1_B
-
G1
H2
J2
L OC K _D
H3
H4
LV D S R ec eiv er
J9
J8
H5
R 25
24
Z o = 50 O hm
Q0_B
L OC K _C
G8
F8
R 24
50
B5
C1
C4
E8
nC LK 0_B
LV D S D riv er
2. 5V P E C L D r iv er
C6
10uF
LOC K_B
C LK 0_B
nC LK 0_B
F6
R 33
Zo = 50 Ohm 100
10
C5
C 22
1nF
C 23
1uF
R1
V C C A_B
LOC K_A
SD ATA
S C LK
C 51
1nF
E4
C8
H7
G2
2. 5V P E C L R ec ei v er
R 12
50
R9
50
J1
H1
F2
D1
R 10
24
For PECL AC termination options consult the
IDT Applications Note "Termination - AC
Coupling Clock Receivers"
Figure 8. 8T49N488 Schematic Example
REVISION B 03/23/15
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8T49N488 DATA SHEET
2.5V LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the 8T49N488.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 8T49N488 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * IEE_MAX = 2.625V * 1127mA = 2958.375W
•
Power (outputs)MAX = 33.2mW/Loaded Output pair
If all outputs are loaded, the total power is 8 * 33.2mW = 265.6mW
Total Power_MAX (2.625V, with all outputs switching) = 2958.375mW + 265.6mW = 3223.975mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 12.4°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 12.4°C/W * 3.224W = 124.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8. JA vs. Air FlowTable for an 80-Ball CABGA
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, NOTE 1
0
1
2
3
12.4°C/W
11°C/W
10.3°C/W
10°C/W
NOTE 1: JA simulation is performed with 8-layers, 8in. x 8in. PCB for the 10x10, 1mm ball pitch BGA package.
REVISION B 03/23/15
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8T49N488 DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 9.
VCCO
Q1
VOUT
RL
50Ω
VCCO - 2V
Figure 9. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to the load, use the following equations which assume a 50 load, and a termination
voltage of VCCO – 2V.
•
For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.7V
(VCCO_MAX – VOH_MAX) = 0.7V
•
For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.5V
(VCCO_MAX – VOL_MAX) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) =
[(2V – 0.7V)/50] * 0.7V = 18.2mW
Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW
REVISION B 03/23/15
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8T49N488 DATA SHEET
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the 8T49N488.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the 8T49N488 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VCC_MAX * (ICC_MAXl + ICCA_MAX) = 2.625V * (956mA + 104mA) = 2782.5mW
•
Power (outputs)MAX= VCCO_MAX * ICCO_MAX = 2.625V * 168mA = 441mW
Total Power_MAX = 2782.5mW + 441mW = 3223.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 12.4°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 3.224W * 12.4°C/W = 124.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 9. JA vs. Air FlowTable for an 80-Ball CABGA
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, NOTE 1
0
1
2
3
12.4°C/W
11°C/W
10.3°C/W
10°C/W
NOTE 1: JA simulation is performed with 8-layers, 8in. x 8in. PCB for the 10x10, 1mm ball pitch BGA package.
REVISION B 03/23/15
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8T49N488 DATA SHEET
Reliability Information
Table 10A. JA vs. Air Flow Table for an 80-Ball CABGA
JA vs. Air Flow
Meters per Second
Multi-Layer PCB, NOTE 1
0
1
2
3
12.4°C/W
11°C/W
10.3°C/W
10°C/W
NOTE 1: JA simulation is performed with 8-layers, 8in. x 8in. PCB for the 10x10, 1mm ball pitch BGA package.
Table 10B. JC Table for an 80-Ball CABGA
JC
Meters per Second
Multi-Layer PCB, NOTE 1
0
12.5°C/W
Transistor Count
The transistor count for 8T49N488 is: 203,572
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8T49N488 DATA SHEET
80-Ball CABGA Package Outline and Package Dimensions
REVISION B 03/23/15
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8T49N488 DATA SHEET
80-Ball CABGA (AS) Land Pattern
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8T49N488 DATA SHEET
Ordering Information
Table 11. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
8T49N488A-dddASGI
IDT8T49N488A-dddASGI
Plastic 80-Ball CABGA,
Lead-Free
Tray
-40C to +85C
8T49N488A-dddASGI8
IDT8T49N488A-dddASGI
Plastic 80-Ball CABGA,
Lead-Free
Tape & Reel
-40C to +85C
NOTE: For the specific -ddd order codes, refer to FemtoClock NG Universal Frequency Translator Ordering Product Information document.
REVISION B 03/23/15
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FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
8T49N488 DATA SHEET
Revision History Sheet
Rev
Table
Page
A
T2
T5C
5
15
Pin Characteristics Table - added PLL_BYPASS to RPulldown row.
LVCMOS DC Characteristics Table - added NOTE 1 to IIH / IIL.
2/6/13
A
T4E
12
Corrected typo: M_INTx[8:0] to M_INTx[7:0]
6/28/13
Replaced schematic and text.
6/25/14
Pin Assignment - corrected typo on E1 and G9 pins.
Deleted part number prefix/suffix throughout the datasheet.
Updated datasheet header/footer.
3/23/15
A
26-27
5
B
REVISION B 03/23/15
Description of Change
Date
35
FEMTOCLOCK®NG QUAD UNIVERSAL FREQUENCY TRANSLATOR
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Tech Support
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email: clocks@idt.com
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
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