FemtoClock® NG Jitter Attenuator and
Clock Synthesizer
8V19N407
DATA SHEET
General Description
Features
8V19N407 is a fully integrated FemtoClock® NG Jitter Attenuator
and Clock Synthesizer. The device is a high-performance clock
solution for conditioning and frequency/phase management of
wireless base station radio equipment boards and is optimized to
deliver excellent phase noise performance. The device supports
JESD204B subclass 0 and 1 clock implementations. The device is
very flexible in programming of the output frequency and phase. A
two-stage PLL architecture supports both jitter attenuation and
frequency multiplication. The first stage PLL is the jitter attenuator
and uses an external VCXO for best possible phase noise
characteristics.The second stage PLL lock on the VCXO-PLL output
signal and synthesizes the target frequency. The second-stage PLL
use an internal VCO.
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The device supports the clock generation of high-frequency clocks
from the VCO and low-frequency system reference signals
(SYSREF). The system reference signals are internally
synchronized to the clock signals. Delay functions exist for achieving
alignment and controlled phase delay between system reference
and clock signals and to align/delay individual output signals. The
input is monitored for activity. The “hold-over” is provided to handle
clock input failure scenarios. Auto-lock, individually programmable
output frequency dividers and phase adjustment capabilities are
added for flexibility. The device is configured through a 4-wire SP
serial interface and reports lock and signal loss status in internal
registers and optionally via an lock detect (nINT) output. The device
is packaged in a lead-free (RoHS 6) 72-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
The device is a member of the high-performance clock family from
IDT.
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REVISION 2 10/1/15
1
Core timing unit for JESD204B wireless infrastructure clocks
Fourth generation FemtoClock® NG technology
First stage PLL uses an external VCXO for jitter attenuation
Second PLL stage facilitates an integrated VCO for frequency
synthesis
8V19N407-19: fVCO = 1900 - 2000MHz
8V19N407-24: fVCO = 2400 - 2500MHz
Five differential configurable LVPECL, LVDS clock outputs with a
variable output amplitude
Four differential LVDS system reference (SYSREF) signal outputs
Synchronization between clock and system reference signals
Wide input frequency range supported by 8-bit pre- and 15-bit
VCXO-PLL feedback divider
Output clock frequencies: fVCO ÷ N
Three independent output clock frequency dividers N (range of ÷1
to ÷96)
Phase delay capabilities for alignment/delay for clock and
SYSREF signals
Individual output phase adjustment (Clock): one-period of the
selected VCO frequency in 64 steps
Individual output phase adjustment (SYSREF): approximately
half-period of the selected VCO frequency in 8 steps
Internal, SPI controlled SYSREF pulse generation
SYSREF frequencies: fVCO ÷ NS
SYSREF frequency dividers NS: ÷64 to ÷2048 (10 dividers)
Clock input compatible with LVPECL, LVDS and LVCMOS signals
Dedicated power-down features for reducing power consumption
Input clock monitoring
Holdover for temporary loss of input signal scenarios
Support of output power-down and output disable
Typical clock output phase noise at 614.4MHz:
1kHz offset:
-122.3 dBc/Hz
10kHz offset:
-123.6 dBc/Hz
100kHz offset:
-128.3 dBc/Hz
1MHz offset:
-149.4 dBc/Hz
10MHz offset:
-155.6 dBc/Hz
RMS phase noise of 614.4 MHz clock (12kHz - 20MHz):
500MHz
50 to VDDx - 2.5V
÷5
384
491.52
500
÷6
320
÷8
240
307.2
÷10
192
245.76
÷12
160
÷16
120
153.6
156.25
÷20
96
122.88
125
÷24
80
NOTE 1. Individual setting for each output QCLKA[1:0], QCLKB[1:0]
and QCLKC.
÷32
60
76.8
78.125
÷40
48
61.44
62.5
Each QCLK output can be individually disabled to the logic low state
by clearing the corresponding OUTEN bit. See Table 2H for details.
÷48
40
51.2
LVDS (EF 0)
0
0
0
Power off
100 across
312.5
0
0
1
400mV
100 across
250
0
1
0
700mV
100 across
1
1000mV,
fOUT > 500MHz
100 across
0
÷64
30
38.4
÷80
24
30.72
÷96
20
25.6
1
Table 2H. QCLK Output Enable1
OUTEN
31.25
NOTE 1. 1920MHz: 8V19N407-19
NOTE 2. 2457.6MHz: 8V19N407-24
NOTE 3. 2500MHz: 8V19N407-24
0
QCLK is disabled in logic low state
1
QCLK is enabled
NOTE 1. Individual setting for each output QCLKA[1:0], QCLKB[1:0]
and QCLKC.
Clock channel power: Setting the corresponding nPOWER bit will
power-down the N divider and delay stage of an clock output channel
to save operating currents in situations of an output channel not used
for frequency generation.
Output Format
All differential device clock outputs (QCLK) can be individually
configured in format (LVPECL, LVDS), output amplitude, state
(enable, disable) and power state (power on, power off). Outputs in
LVPECL format are terminated to a termination voltage VT according
to the configured output amplitude. Outputs in LVDS format are
terminated 100across the terminals. The outputs of the 8V19N407
was designed for flexibility in amplitude control. The output offset
voltage changes with amplitude. For strict LVDS compliance, it is
recommended to AC-couple the LVDS outputs and re-bias to VBIAS =
1.25V. The lowest output amplitude settings correspond with the least
amount of power consumed. Unused clock outputs may not be
terminated externally to save current consumption. The QCLK
outputs LVPECL, LVDS format configuration is shown in Table 2G.
For LVPECL format, set EF = 1 and terminate the LVPECL output
pair 50 to the specified recommended termination voltage shown in
Table 2G. For LVDS format, set EF = 0 and terminate the output pair
100 across the QCLK, nQCLK terminals. Independent on the state
of the EF bit, the A[1:0] bits control the output amplitude of QCLK
outputs.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
Output Operation
Table 2I. Clock Channel Power Operation1
nPOWER
Clock Channel
0
Divider N and delay stage powered up
1
Divider N and delay stage powered down
NOTE 1. Individual setting for each clock channel A, B and C
(dividers NA, NB, NC and clock delay stages A, B, C). See Table
3E for register configuration.
SYSREF Outputs (QREF)
Each QREF output can be individually configured as SYSREF output
or as clock output by setting the corresponding MUX bit. For
JESD204B-operation, configure QREF outputs as SYSREF outputs.
See Table 2J for details.
9
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 2J. QREF Output Configuration1
QREF MUX
See Table 2P and Section, “SYSREF Generation” on page 12. Each
individual QREF output can also be disabled into logic low state by
clearing the OUTEN bit. For SYSREF operation, the QREF outputs
should be configured as shown in Table 2L:
Operation
Clock Mode
• Frequency divided by N
• Output amplitude: use any setting in
Table 2K
• Set nPOWER = 1 to power down the
corresponding (unused) SYSREF delay
stage A0-B1
• Set OUTEN = 1 (output enable)
0
Table 2L. QREF Output Control1 (SYSREF, MUX = 1)
Clock mode (MUX = 0): QREF outputs operate as additional clock
outputs, increasing the available clock signal fanout. In this mode, the
output amplitude can be configured to one of three different values.
In clock mode, the output frequency of is controlled by the N divider
of the corresponding device clock output. For instance, the divider NA
controls the output frequency of both QCLKA0, A1 and QREFA0, A1.
The QREF output delay setting is controlled by the delay circuit of
the associated clock output QCLK. See Table 2K for details.
A[0]
Output Operation
X
0
0
QREF output buffer
powered down
0
0
1
0
1
0
0
1
1
1
0
1
VO, PP = 400mV
1
1
0
VO, PP = 700mV
1
1
1
VO, PP = 1000mV,
fOUT > 500MHz
100 across
0
1
VO, PP = 400mV
100 across
QCLK Outputs
The 8V19N407 has output dividers which generate the supported
clock frequencies at outputs QCLK synchronously. After the SPI
controlled synchronization of output dividers, all output clocks QCLK
will be in alignment with each other. Outputs which selected different
output dividers are aligned on the incident rising edge.
QCLK Delay Circuits
QREF disabled in logic
low state
The clock outputs QCLK have an individual delay element () to
advance/delay its clock output phase of an clock output bank if an
offset is desired on a particular output. The delay circuit operates by
inserting a delay into the clock signal coming out of the individual
QCLK bank outputs by a discrete number of one clock period of the
FemtoClock NG VCO. The user may select a number of steps to
insert via the appropriate register. Each of the two output banks
supports 64 steps of phase delay (the delay unit is a function of the
internal VCO frequency. See Table 2O). For fine delay, the SYSREF
outputs have individual phase delay circuits, each delay circuit
supports eight steps. See Table 2P.
JESD204B (SYSREF) Operation (MUX = 1): The QREF outputs
support the generation of SYSREF pulses in JESD204B
applications. The delay stages can be used to establish repeatable
phase relationships of QCLK outputs to each other and to the SYREF
signals QREF: the QCLK delay stages support 64 steps of delay and
the QREF outputs support additional 8 steps of fine-delay.
REVISION 2 10/1/15
Output Termination
Power off
Synchronization and Phase Alignment
Table 2K. QREF Output Control (MUX = 0)
A[1]
Output Operation
0
SYSREF power down features: Setting the corresponding
nPOWER bit will power-down the delay circuit. A QREF output
buffer can be powered-down by setting A[1:0] = 00. The QREF
outputs automatically power-down when SRO = 0 (counted pulse
mode) and no SYSREF pulses are generated. QREF outputs will
power up automatically for SYSREF pulse generation, controlled by
the SYSREF generation sequence (see Section, “QREF Phase
Delay and SYSREF Synchronization Sequence, (Sequence S2)” on
page 14). Applications not using a QREF output should power the
delay circuit down (nPOWER = 1) and also power off the output buffer
(set MUX = 0, A[1:0] = 00). Powered-down output buffers save
operating current even with presence of external terminations. See
Table 2M and Table 2K for details.
NOTE 1. Individual setting for each output QREF output
QREFA[1:0], QREFB[1:0].
OUTEN
A[0]
0
NOTE 1. Individual setting for each output QREF output
QREFA[1:0], QREFB[1:0].
SYSREF Mode (JESD204B)
• Set nPOWER = 0 to power up the
corresponding SYSREF delay stage
A0-B1
• Set the QREF output amplitude to
400mV (A[1:0] = 01)
• Set OUTEN = 1 (output enable)
1
A[1]
The delay capabilities of the clock and SYSREF outputs can be used
to establish a specific, repeatable phase relationship between any
QCLK and QREF outputs. QREF outputs that are configured with the
same delay value are aligned to each other.
10
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Table 2M. A,B, C QCLK Phase Delay1
Phase Delay (in ns
Phase Delay (in ns for a VCO Frequency of:
Delay Unit
1 ----------f VCO
1920MHz2
2457.6MHz3
2500MHz4
0
0
0
0
0
1
1 · 1/fVCO
0.520
0.406
0.400
2
2 · 1/fVCO
1.041
0.8138
0.800
...
...
...
...
...
· 1/fVCO
· 0.520
· 0.406
· 0.400
...
...
...
...
...
63
63 · 1/fVCO
32.812
25.634
25.200
NOTE 1. Individual setting for each clock output Bank A, B and C.
NOTE 2. 1920MHz: 8V19N407-19.
NOTE 3. 2457.6MHz: 8V19N407-24.
NOTE 4. 2500MHz: 8V19N407-24.
Table 2N. A0, A1, B0, B1 SYSREF Phase Delay1 2
Phase Delay (in ns for a VCO Frequency (fVCO) of:
Delay Unit
Delay
1920MHz
2500MHz
2949.12MHz
0
000
0
0.000
0.000
0.000
1
001
tDelay
0.165
0.165
0.165
2
010
1/fVCO
0.521
0.339
0.407
3
011
tDelay + 1/fVCO
0.686
0.504
0.572
4
100
2/fVCO
1.042
0.678
0.814
5
101
tDelay + 2/fVCO
1.207
0.843
0.979
6
110
3/fVCO
1.563
1.017
1.221
7
111
tDelay + 3/fVCO
1.728
1.182
1.386
NOTE 1. tDelay is implemented by inserting a buffer delay of 165ps (±20% tolerance).
NOTE 2. Individual setting for each SYSREF delay stages. See Table 3G for register configurations.
QREF (SYSREF) to QCLK Phase Alignment
QCLK (N =2, = 8)
The QREF outputs have a deterministic phase relation to the QCLK
outputs. The delay circuits in both QCLK and QREF paths add phase
offset to configure the phase relationship of each QCLK and QREF
pair. There are 64 delay steps for each QCLK output bank and
additional 8 delay steps on each QREF output. The QCLK delay unit
is equal to one VCO period, the QREF delay unit is equal to
approximately one half VCO period (fine delay). Each QCLK output
bank and each QREF output can be individually advanced, aligned
or delayed with respect to an incident QCLK rising edge. See Figure
1: For phase alignment between the incident edge of QCLK outputs
and QREF, set the phase delay to = 9 (QCLK) and = 0 (QREF).
As a pre-condition for alignment of SYSREF pulses to the incident
clock edge, set the SYSREF synchronizer divider to the least
common multiple value of clock dividers NA and NB (see Table 3K).
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
1÷fVCO
QCLK (N = 4, = 9)
QCLK (N = 2, = 9)
QREFm ( = 0 to 7)
incident edge
Figure 1. QREF to QCLK Phase Relationship
11
REVISION 2 10/1/15
8V19N407 DATA SHEET
SYSREF Generation
The QREF outputs generate SYSREF signal pulses that support
JESD204B synchronization functions. Following SYSREF pulse
generation modes are available and configurable by SPI:
The generation of SYSREF pulses is configured by SPI commands
and is available after the initial setup of output clock divider and
QREF phase delay stages.
• Counted pulse mode: 1 to 255 pulses are generated by the device.
SYSREF activity stops automatically after the transmission of the
selected number of pulses and the QREF output powers down.
An essential part of the SYSREF generation is the sequence of SPI
commands to apply to synchronize the SYSREF pulses to the clock
divider and delay state machines.
• Continuous mode. The SYSREF signal is a clock signal.
.
Table 2O. SYSREF Generation1 2
NS
SRO
3
2
SYSREF Operation (fSYSREF) for fVCO (MHz)
1
0
NS
1920
2457.6
2500
Counted Pulse Mode
(Use the SRPC register to configure the number of generated SYSREF pulses)
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
0
1
0
÷64
30
38.4
39.0625
÷96
20
25.6
26.04166
÷128
15
19.2
19.53125
÷192
10
12.8
13.02083
0
÷256
7.5
9.6
9.76562
0
1
÷384
5
6.4
6.51041
1
0
÷512
3.75
4.8
4.88281
1
1
1
÷768
2.5
3.2
3.25520
1
0
0
0
÷1024
1.875
2.4
2.44140
1
0
0
1
÷2048
0.9375
1.2
1.22070
Continues Pulse Mode
1
0
0
0
0
÷64
30
38.4
39.0625
0
0
0
1
÷96
20
25.6
26.04166
0
0
1
0
÷128
15
19.2
19.53125
0
0
1
1
÷192
10
12.8
13.02083
0
1
0
0
÷256
7.5
9.6
9.76562
0
1
0
1
÷384
5
6.4
6.51041
0
1
1
0
÷512
3.75
4.8
4.88281
0
1
1
1
÷768
2.5
3.2
3.25520
1
0
0
0
÷1024
1.875
2.4
2.44140
1
0
0
1
÷2048
0.9375
1.2
1.22070
NOTE 1. SRO and SRPC are global settings. See Table 2P for the setting sequence to apply.
NOTE 2. SYSREF setting should only be used with 400mV and 700mV amplitude setting.
REVISION 2 10/1/15
12
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
QCLK Phase Delay and SYSREF Synchronization Sequence (S2)
Precondition: Delay circuits are set to powered-up (nPOWER = 0).
Set MUX = 1 to assign the SYSREF function to the QREF outputs,
NS to the SYSREF pulse rate and configure the SYSREF
synchronizer divider value to the least common multiple value of NA
and NB.
Table 2P. SYSREF Generation Sequence
SRO
SYSREF
Pulse Mode
Operation
Pre-condition:
• MUX = 1, nPOWER = 0, A[1:0] = 01
• Write SR_REQ0 = 1 (register 5). QREF outputs will power up.
• OUTEN = 1
• Write SR_REQ1 = 1 (register 25): NS dividers are reset and
• SPRC[7:0] contains the number of pulses
to generate (1...255)
synchronize.
• NS[3:0] contains the SYSREF divider
• Write SR_RESET = 1 (register 29): Continuous clocks or a number
• SYNC[3:0] is set to the least common
of specified pulses will be generated at QREF outputs.
multiple value of NA and NB.
See Table 2P for detailed description of the sequences.
0
Counted
Start operation: apply sequence S2
• QREF output will power-up for SYSREF
pulse generation.
• The programmed number of SYSREF
pulses is generated
• QREF output will power down
automatically
• The three SR_REQ0, 1 and SR_RESET
bits clear automatically
Repeated use: apply sequence (S2) at any
time
Pre-condition:
• A[1:0] = 01
• MUX = 1, nPOWER = 0
• OUTEN=1
• NS[3:0] contains the SYSREF divider
1
Continues
• SYNC[3:0] is set to the least common
multiple value of NA and NB.
Start operation: apply sequence S2
Stop operation: Set SRO = 0
Restart function: Set SRO = 1 and apply
sequence S2
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
13
REVISION 2 10/1/15
8V19N407 DATA SHEET
Device Start-up, Reset and Synchronization
The QREF phase delay and SYSREF synchronization sequence is
also used to trigger the synchronized generation of SYSREF pulses.
The last steps, it is recommended to clear all interrupts in preparation
to start monitoring the devices status bits.
After the 8V19N407 first powers-up, an internal reset signal is
auto-generated. The registers are initialized with the default values
listed in the table for each register.
Status Conditions & Interrupts
During startup, it is not required to apply an input clock to the CLK
input: the VCXO-PLL will “free-run” with the frequency of the external
VCXO. The control voltage to the external VCXO (LFV pin) will be
held at VDD/2 to support fast PLL lock and the VCXO-PLL will begin
operation with their charge pumps in the middle of their operating
range.
The 8V19N407 has an interrupt output to signal changes in status
conditions. Settings for status conditions may be accessed in the
Status and Interrupt Enable registers. The 8V19N407 has several
conditions that can indicate faults and status changes in the
operation of the device. These are shown in Table 2Q and can be
monitored directly in the status registers. A changed bit on any or all
of these can be programmed to generate an interrupt signal (nINT)
via settings in the Interrupt Enable registers.
As a second step, the user should write the desired PLL dividers.
Configure other operation settings such the output divider, SYSREF
divider and output phase delay settings into the registers and apply
software-controlled divider reset and QREF phase delay stage
synchronization sequences. This is done by two separate
SPI-controlled reset procedures which should be applied in the order
below. First, apply the output divider reset sequence:
Table 2Q. Status Bit Functions
Status if Bit is:
Bit Name
Clock Output Divider Reset Sequence, (Sequence S1)
•
•
•
1
0
STAT2
VCO calibration
Completed
Not
completed
step 2: write logic 1 to the NR_REQ1 register bit
STAT1
VCXO-PLL
Locked
Unlocked
step 3: write logic 1 to the NR_RESET bit
STAT0
CLK state
Active
LOS
step 1: write logic 1 to the NR_REQ0 register bit
This completes the reset of the output divider stages. Each
subsequent change of any N output divider value requires to re-apply
above divider reset sequence.
For the reference monitor circuit, if there has been no activity on the
reference input for three consecutive clock edges (of the feedback
1st-stage VCXO signal) then the appropriate status bit will transition
to a 0. It will not return to 1 until activity has resumed for three clock
edges.
Then, configure the delay stages and when completed, apply the
second sequence to synchronize the QREF output delay stages:
QREF Phase Delay and SYSREF Synchronization
Sequence, (Sequence S2)
•
•
•
Function
The lock detect circuit operate by monitoring the loop filter voltage on
the first PLL (VCXO-PLL). If the monitored voltage exceeds a range,
this indicates an out-of-lock condition.
step 1: write logic 1 to the SR_REQ0 register bit
step 2: write logic 1 to the SR_REQ1 register bit
It is normal when attempting to achieve lock for there to be multiple
times when an out-of-lock condition as described above would occur
before a full, stable lock is achieved. To prevent a bouncing status, the
lock detect bit will not become asserted until the lock is stable. Once
a stable lock has been achieved, this de-bounce circuit is deactivated
so the lock-detect bit will de-assert immediately if a subsequent
out-of-lock condition occurs.
step 3: write logic 1 to the SR_RESET bit
This completes the synchronization of the delay stages.
The clock divider reset sequence and the QREF phase delay &
SYSREF synchronization sequence must be done in two separate
SPI write cycles (do not combine both sequences in a single SPI
write).
If sequences S1 and S2 are programmed in any order other than that
which is recommended, this could result in an unknown state of the
SYSREF generation. In order to reactivate the SYSREF
Synchronization Sequence, power down QREF outputs by
programming nPOWER bits to “1”. The device is now ready for a new
SYSREF Synchronization Sequence.
The Interrupt and Interrupt Enable registers are used to control the
behavior of the nINT output based on changes in the status
indicators. If any of the status indicators STAT[1:0] change, that will
set the corresponding INT[1:0] bit of the Interrupt registers. If any of
the INT[1:0] bits are set and their corresponding interrupt enable bit
INTEN[1:0] is asserted, it will generate an interrupt (low level on
nINT).
Any change of the output divider values or delay stage configuration
requires to re-apply initialization/ synchronization through the
respective SPI sequence individually.
Interrupts are cleared by writing a 1 to the appropriate INT[1:0] bit(s)
in the Interrupt register after the underlying fault condition has been
resolved. When all valid interrupt sources have been cleared in this
manner, this will release the nINT output until the next unmasked
fault.
When synchronizing the output delay stages through the
synchronization sequence, care must be taken prevent writing a logic
1 to the NR_REQ0, NR_REQ1, NR_RESET register bits in the same
base register write cycle (write a logic 0 to these bits, which will not
affect them).
REVISION 2 10/1/15
14
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
SPI Mode Operation with MISO Output in High Impedance
SPI mode slave operation requires that some function external to the
8V19N407 has performed any necessary serial bus arbitration and/or
address decoding at the level of the board or system. By default, the
MISO data output is in high-impedance state. The 8V19N407 begins
a cycle by detecting an asserted (low) state on the nLE input at a
rising edge of SPICLK. This is also coincident with the first bit of data
being shifted into the device. In SPI mode, the first bit is the Most
Significant Bit (MSB) of the data word being written. Data must be
written in 32-bit words, with nLE remaining asserted and one data bit
being shifted in to the 8V19N407 on every rising edge of SPICLK. If
nLE is deasserted (high) at any time except following the 32nd falling
edge of SPICLK, then this is treated as an error and the shift register
contents are discarded. No data is written to any internal registers. If
nLE is deasserted (high) as expected after the 32nd falling edge of
SPICLK, then this will result in the shift register contents being acted
on according to the instructions (address + R/W) in it. During write
operation, the MISO output remains in high-impedance state. The
word format of the 32-bit quantity in the shift register is shown in
Figure 2. The register fields in the 8V19N407 have been organized
so that the 4 LSBs in each 32-bit register row are not used for data
transfer. Three of these bits will represent the base address for the
eight 32-bit base registers and the 4th bit indicates whether a read or
write operation is requested. If a read operation is requested, 32-bits
of read data will be provided in the immediately subsequent access.
The nLE must be deasserted (high) and then reasserted (low). On
the first SPICLK rising edge, once nLE is re-asserted to low state, the
MISO output will turn to active state and one data bit will be placed
on the MISO output at each rising edge of SPICLK as long as nLE
remains asserted (low). If nLE is deasserted (high) before 32-bits of
read data have been shifted out, the read cycle will be considered to
be completed. If nLE remains asserted (low) longer than 32-bit times,
then the data during those extra clock periods will be undefined. The
MSB of the data will be presented first. When nLE is de-asserted
(high), the MISO output will go into high impedance state and the SPI
bus is available for transactions with other devices.
2
tSU tH1
tLO tHI
tH2
tPW
nLE
1
Start Write Command (D3=0)
2
Complete Write Command
SPICLK
1
MOSI
D31
D30
D29
D28
MISO
D1
D0
High Impedance
Figure 2. SPI Write Cycle Timing Diagram, MISO High Impedance
tPW
tH2
nLE
3
Start Read Data Out
4
Complete Read Data Out
SPICLK
4
3
MOSI
D1
D0
tPZLH
MISO
High Impedance
tP
D31
tPLHZ
D30
…
D0
High Imp.
Figure 3. SPI Read Cycle Timing Diagram, MISO High Impedance
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
15
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 2R. SPI Read / Write Cycle Timing Parameters
Symbol
Parameter
Test Condition
Minimum
Maximum
Unit
fCLK
SPICLK frequency
-
20
MHz
tSU
tH1
nLE, MOSI setup time to SPICLK
15
-
ns
SPICLK to nLE, MOSI hold time
10
-
ns
tH2
SPICLK falling edge to nLE rising edge,
hold time
10
-
ns
tLO
SPICLK low period
25
-
ns
tHI
SPICLK high period
25
-
ns
tPW
nLE deasserted pulse width
50
-
ns
tPZLH
Propagation Delay, MISO Output High
Impedance to Active High or Low
External pullup = 5k
16
ns
tPLHZ
Propagation Delay, MISO Output Active
High or Low to High Impedance
External pullup = 5k
2
ns
tP
Propagation Delay, SPICLK to MISO
External pullup = 5k
20
ns
Table 2S. SPI Interface I/O Voltage Select
SELSV
SPI Interface I/O Voltage (SPICLK, MOSI, MISO, nLE, nINT)
0
1.8V
1 (default)
3.3V
REVISION 2 10/1/15
16
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Register Descriptions
The Serial Control port of the 8V19N407 supports SPI mode operation.
Below indicates how registers may be accessed.
0
Register
Base Address
Table 3A. . Register Map
Register Name
3
D7
D6
D5
D4
D3
D2
D1
D0
QCLKC Control
Table 3E 0000 XXXX
QC
DLY[5]
QC
DLY[4]
QC
DLY[3]
QC
DLY[2]
R/Wn
0
0
0
1
MV Feedback
Divider Control
Table 3C
1111 1111
MV[7]
MV[6]
MV[5]
MV[4]
MV[3]
MV[2]
MV[1]
MV[0]
2
MF Feedback
Divider
Table 3C
0001 0000
MF[7]
MF[6]
MF[5]
MF[4]
MF[3]
MF[2]
MF[1]
MF[0]
3
SYSREF Control
Table 3K
1000 0001
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRO
4
QCLKC Control
QCLKB Control
Table 3E 0000 XXXX
QC
DLY[1]
QC
DLY[0]
QB
DLY[1]
QB
DLY[0]
R/Wn
0
0
1
5
Reset Control
MV Feedback
Divider Control
Table 3S
Table 3C
X000 0000
SR_REQ0
MV[14]
MV[13]
MV[12]
MV[11]
MV[10]
MV[9]
MV[8]
6
QREFA1, A0
Control
Table 3G
1000 1000
QREFA1
A[1]
QREFA1
A[0]
QREFA1
EF
QREFA1
MUX
QREFA0
A[1]
QREFA0
A[0]
QREFA0
EF
QREFA0
MUX
7
Reset Control
SYSREF Control
Table 3S
Table 3K
X000 1000
NR_REQ0
Reserved
SYNC
nPOWER
Reserved
SYNC
N[3]
SYNC
N[2]
SYNC
N[1]
SYNC
N[0]
8
QCLKB Control
Table 3E 0000 XXXX
QB
DLY[5]
QB
DLY[4]
QB
DLY[3]
QB
DLY[2]
R/Wn
0
1
0
9
PV Pre-Divider
Table 3C
1111 1111
PV[7]
PV[6]
PV[5]
PV[4]
PV[3]
PV[2]
PV[1]
PV[0]
Reserved
STAT2
STAT1
STAT0
Reserved
Reserved
INT1
INT0
NS[3]
NS[2]
NS[1]
NS[0]
QREFB1
OE
QREFB0
OE
QREFA1
OE
QREFA0
OE
Table 3E 0000 XXXX
QA
DLY[5]
QA
DLY[4]
QA
DLY[3]
QA
DLY[2]
R/Wn
0
1
1
Table 3I
POLV
HOLD
CPV[5]
CPV[4]
CPV[3]
CPV[2]
CPV[1]
CPV[0]
10 Status Control
Table 3O XXXX X0XX
SYSREF Control
11 QREF B1, B0
Control
Table 3K
Table 3G
12 QCLKA Control
13 VCXO-PLL Control
0100 1111
0010 0000
14 Reserved
—
0001 1000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
15 Reserved
—
1000 0000
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
QA
DLY[1]
QA
DLY[0]
Reserved
BYPASS
R/Wn
1
0
0
16
QCLKA Control
Table 3E
0000 XXXX
VCXO-PLL Control Table 3I
17
QREFA1 Control
QREFA0 Control
Table 3G
0001 0001
QREFA1
DLY[2]
QREFA1
DLY[1]
QREFA1
DLY[0]
QREFA1
nPOWER
QREFA0
DLY[2]
QREFA0
DLY[1]
QREFA0
DLY[0]
QREFA0
nPOWER
18 QCLKA Control
Table 3E
0000 0100
QCLKA
N[4]
QCLKA
N[3]
QCLKA
N[2]
QCLKA
N[1]
QCLKA
N[0]
QA
OE
Ch A
nPOWER
Reserved
QCLKB Control
QCLKC Control
Table 3E
0000 0100
QCLKB
N[4]
QCLKB
N[3]
QCLKB
N[2]
QCLKB
N[1]
QCLKB
N[0]
QB
OE
Ch B
nPOWER
QCLKC
N[0]
Table 3E 0000 XXXX
QCLKC
N[4]
QCLKC
N[3]
QCLKC
N[2]
QCLKC
N[1]
R/Wn
1
0
1
4
19
20 QCLKC Control
5
Default
Setting
0
1
2
See
21
QREFB1 Control
QREFB0 Control
Table 3G
0001 0001
QREFB1
DLY[2]
QREFB1
DLY[1]
QREFB1
DLY[0]
QREFB1
nPOWER
QREFB0
DLY[2]
QREFB0
DLY[1]
QREFB0
DLY[0]
QREFB0
nPOWER
22
QREFB1 Control
QREFB0 Control
Table 3G
1000 1000
QREFB1
A[1]
QREFB1
A[0]
QREFB1
EF
QREFB1
MUX
QREFB0
A[1]
QREFB0
A[0]
QREFB0
EF
QREFB0
MUX
23 SYSREF Control
Table 3K
0000 0000
SRPC[7]
SRPC[6]
SRPC[5]
SRPC[4]
SRPC[3]
SRPC[2]
SRPC[1]
SRPC[0]
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
17
REVISION 2 10/1/15
8V19N407 DATA SHEET
6
Register
Base Address
Table 3A. . Register Map (Continued)
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
24 QCLKC Control
Table
3ETable
3M
1000 XXXX
QC
OE
Ch C
nPOWER
Reserved
SPI_REL
R/Wn
1
1
0
Reset Control
25 QCLKB1, B0
Control
Table 3S
Table 3E
X010 0100
SR_REQ1
Reserved
QCLKB1
A[1]
QCLKB1
A[0]
QCLKB1
EF
QCLKB0
A[1]
QCLKB0
A[0]
QCLKB0
EF
26
QCLKA1, A0
Control
Table 3E
0010 0100
Reserved
Reserved
QCLKA1
A[1]
QCLKA1
A[0]
QCLKA1
EF
QCLKA0
A[1]
QCLKA0
A[0]
QCLKA0
EF
27
Reset Control
QVCXO Control
Table 3S
Table 3E
X100 0001
NR_REQ1
QVCXO
A[1]
QVCXO
A[0]
QVCXO
EF
Reserved
Reserved
Reserved
Reserved
QCLKC
A[1]
QCLKC
A[0]
QCLKC
EF
Reserved
R/Wn
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved
VCO_SEL
Reserved
INTEN1
INTEN0
NR_RESET Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
28 QCLKC Control
7
Default
Setting
See
Table 3E 1000 XXXX
29
Reset Control
VCO Control
Table 3S
Table 3M
X000 1010
30
VCO Control
Interrupt Enable
Table 3M
Table 3Q
0011 0000
Table 3S
X011 1110
31 Reset Control
SR_RESET Reserved
Reserved
PLL Divider Control Registers
The divider control registers contains the frequency divider settings for the VCXO-PLL and FemtoClock NG PLL.
Table 3B. PLL Divider Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
1
MV[7]
MV[6]
MV[5]
MV[4]
MV[3]
MV[2]
MV[1]
MV[0]
2
MF[7]
MF[6]
MF[5]
MF[4]
MF[3]
MF[2]
MF[1]
MF[0]
5
SR_REQ0
MV[14]
MV[13]
MV[12]
MV[11]
MV[10]
MV[9]
MV[8]
9
PV[7]
PV[6]
PV[5]
PV[4]
PV[3]
PV[2]
PV[1]
PV[0]
Table 3C. PLL Divider Control Register Function Descriptions
Factory
Default
Bits
Name
MV[14:0]
VCXO-PLL Feedback Divider
000 0000 VCXO-PLL Feedback Divider. Range: MV = ÷4 to ÷32767. Binary encoding.
1111 1111 Default divider: MV = ÷255
PV[7:0]
VCXO-PLL Pre-Divider
1111 1111
VCXO-PLL Pre Divider. Range: PV = ÷1 to ÷255. Binary encoding.
Default divider: PV = ÷255
MF[7:0]
FemtoClock NG PLL
Feedback Divider
0001 0000
FemtoClock NG PLL Feedback Divider. Range: MF = ÷8 to ÷255.
Binary encoding. Default divider: MF = ÷16
REVISION 2 10/1/15
Function
18
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
QCLK, QVCXO Control Registers
The QCLK, QVCXO Device Clock Output Control Registers contain the settings for the clock frequency divider, phase delay, power state,
enable state, signal format and signal amplitude.
Table 3D. QCLKn, QVCXO Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
0
QC
DLY[5]
QC
DLY[4]
QC
DLY[3]
QC
DLY[2]
R/W
0
0
0
4
QC
DLY[1]
QC
DLY[0]
QB
DLY[1]
QB
DLY[0]
R/W
0
0
1
8
QB
DLY[5]
QB
DLY[4]
QB
DLY[3]
QB
DLY[2]
R/W
0
1
0
12
QA
DLY[5]
QA
DLY[4]
QA
DLY[3]
QA
DLY[2]
R/W
0
1
1
16
QA
DLY[1]
QA
DLY[0]
Reserved
BYPASS
R/W
1
0
0
18
QCLKA
N[4]
QCLKA
N[3]
QCLKA
N[2]
QCLKA
N[1]
QCLKA
N[0]
QA
OE
Ch A
nPOWER
Reserved
19
QCLKB
N[4]
QCLKB
N[3]
QCLKB
N[2]
QCLKB
N[1]
QCLKB
N[0]
QB
OE
Ch B
nPOWER
QCLKC
N[0]
20
QCLKC
N[4]
QCLKC
N[3]
QCLKC
N[2]
QCLKC
N[1]
R/Wn
1
0
1
24
QC
OE
Ch C
nPOWER
Reserved
SPI_REL
R/Wn
1
1
0
25
SR_REQ1
Reserved
QCLKB1
A[1]
QCLKB1
A[0]
QCLKB1
EF
QCLKB0
A[1]
QCLKB0
A[0]
QCLKB0
EF
26
Reserved
Reserved
QCLKA1
A[1]
QCLKA1
A[0]
QCLKA1
EF
QCLKA0
A[1]
QCLKA0
A[0]
QCLKA0
EF
27
NR_REQ1
QVCXO
A[1]
QVCXO
A[0]
QVCXO
EF
Reserved
Reserved
Reserved
Reserved
28
QCLKC
A[1]
QCLKC
A[0]
QCLKC
EF
Reserved
0
1
1
1
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
19
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 3E. QCLK, QVCXO Control Register Function Descriptions
Bits
Name
OE
QCLK Output
Enable
Factory
Default
Function
1 = QCLKx output(s) are enabled
1
0 = QCLKx output(s) are disabled in the active low state
x denominate(s) the clock output(s) (e.g. x = B denominates QCLKB0 and CLKB1).
1 = Output channel X is powered down
nPOWER
Clock Output
Channel Power
0
0 = Output channel X is powered up
x denominates the output channel A, B or C. A channel consists of the output divider and
delay stage, e.g. A and NA for channel A.
These bits control the value of the clock frequency divider and output frequency
NA[4:0],
NB[4:0],
NC[4:0]
Clock Divider Setting
00000
N[4:0]
Clock Divider
N[4:0]
Clock Divider
00000
÷2
01000
÷16
00001
÷3
01001
÷20
00010
÷4
01010
÷24
00011
÷5
01011
÷32
00100
÷6
01100
÷40
00101
÷8
01101
÷48
00110
÷10
01110
÷80
00111
÷12
01111
÷96
10000
÷1
11011
÷64
These bits control the selection of phase delay of the clock outputs. One unit of corresponds to the delay of 1/fVCO. For fine delay adjustments, use the delay circuits of the
QREF outputs.
DLY[5:0]
EF
Clock Phase
Delay
QCLK, QVCXO
Output Format
000000
0
Delay
000000
0
000001
1/fVCO
000010
2· (1/fVCO)
...
...
· (1/fVCO)
Sets the output format:
0 = LVDS (Requires LVDS 100 output termination across a differential pair.
1 = LVPECL (Requires LVPECL 50 termination to the specified recommended termination voltage).
QCLK, QVCXO amplitude control
A[1:0]
QCLK,QVCXO
Output Amplitude
REVISION 2 10/1/15
10
Output Termination
A[1]
A[0]
Amplitude
0
0
Output is
powered- down
0
1
400mV
50 to VDDx - 1.5V
1
0
700mV
50 to VDDx - 2V
1
1
1000mV,
fOUT > 500MHz
20
LVPECL (EF = 1)
LVDS (EF = 0)
Should not have any
termination
100across
differential pair
50 to VDDx - 2.5V
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
QREF Output Control Registers
The QREF Control Registers contain the settings for the SYSREF output enable, power state, signal source and phase delay. Since the
registers have an identical format and bit meaning, they are described only once.
Table 3F. QREF Output Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
6
QREFA1
A[1]
QREFA1
A[0]
QREFA1
EF
QREFA1
MUX
QREFA0
A[1]
QREFA0
A[0]
QREFA0
EF
QREFA0
MUX
11
NS[3]
NS[2]
NS[1]
NS[0]
QREFB1
OE
QREFB0
OE
QREFA1
OE
QREFA0
OE
17
QREFA1
DLY[2]
QREFA1
DLY[1]
QREFA1
DLY[0]
QREFA1
nPOWER
QREFA0
DLY[2]
QREFA0
DLY[1]
QREFA0
DLY[0]
QREFA0
nPOWER
21
QREFB1
DLY[2]
QREFB1
DLY[1]
QREFB1
DLY[0]
QREFB0
nPOWER
QREFB0
DLY[2]
QREFB0
DLY[1]
QREFB0
DLY[0]
QREFB0
nPOWER
22
QREFB1
A[1]
QREFB1
A[0]
QREFB1
EF
QREFB1
MUX
QREFB0
A[1]
QREFB0
A[0]
QREFB0
EF
QREFB0
MUX
Table 3G. QREF Output Control Register Function Descriptions1
Factory
Default
Bits
Name
MUX
QREF Signal Source
0
nPOWER
Output Power
1
DLY[2:0]
SYSREF Phase Delay
EF
QREF Output Format
000
0
Function
1 = QREFn signal source is the QREFn delay circuit (SYSREF mode)
0 = QREFn signal source is the respective N clock divider (Clock mode)
1 = QREFn and delay block is powered down
0 = QREFn and delay block is powered up
These bits control the selection of phase-delay of the QREF outputs.
Sets the QREF output format:
0 = QREFn is LVDS (Requires LVDS 100 output termination across a differential
pair). Use this format for SYSREF or clock signals.
1 = QREFn is LVPECL (Requires LVPECL 50 output termination to the specified
recommended termination voltage). Use this format for clock signals.
QREFn Amplitude Control
A[1:0]
OE
QREF Output Amplitude
QREF Enable
10
1
Output Termination
A[1]
A[0]
QREF
Amplitude
0
0
Powered-down
0
1
400mV
50 to VDDx - 1.5V
1
0
700mV
50 to VDDx - 2V
1
1
1000mV,
fOUT > 500MHz
LVPECL (EF = 1)
Should not have
any termination
LVDS (EF = 0)
100across
differential pair
50 to VDDx - 2.5V
1 = QREFn output is enabled
0 = QREFn output is disabled in the active low state
NOTE 1. Subscript “n” represents the output number.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
21
REVISION 2 10/1/15
8V19N407 DATA SHEET
VCXO-PLL Control Registers
The device control register contains settings for the VCXO-PLL charge pump and VCXO control voltage polarity and VCXO-bypass.
Table 3H. VCXO-PLL Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
13
POLV
HOLD
CPV[5]
CPV[4]
CPV[3]
CPV[2]
CPV[1]
CPV[0]
16
QA
DLY[1]
QA
DLY[0]
Reserved
BYPASS
R/Wn
1
0
0
Table 3I. VCXO-PLL Control Register Function Descriptions
Bits
Name
CPV[5:0]
VCXO-PLL Charge-Pump
Current
POLV
VCXO Polarity
Factory
Default
Function
10 0000
Controls the charge pump current of the VCXO-PLL. Charge pump current is
the binary value of this register multiplied by 20µA.
ICP = 20µA · CPV[5:0]. Default setting is 640µA (32 · 20µA)
0
0 = Positive polarity. Use for an external VCXO with a positive f(VC)
characteristics.
1 = Negative polarity. Use for an external VCXO with a negative f(VC)
characteristics.
0 = Normal operation
HOLD
Holdover Control
0
BYPASS
VCXO-PLL Bypass
0
1 = VCXO-PLL is set to holdover. The control voltage of the external VCXO is
set to VDD/2.
0 = VCXO-PLL is enabled
1 = VCXO-PLL is bypassed
SYSREF Control Registers
The SYSREF pulse count register (SRPC) contains the binary setting for the number of SYSREF pulses generated by the device.
Table 3J. SYSREF Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
3
VCO_DIV
nPOWER
VCO
N[3]
VCO
N[2]
VCO
N[1]
VCO
N[0]
VCO
nPOWER
Reserved
SRO
7
NR_REQ0
Reserved
SYNC
nPOWER
Reserved
SYNC
N[3]
SYNC
N[2]
SYNC
N[1]
SYNC
N[0]
11
NS[3]
NS[2]
NS[1]
NS[0]
QREFB1
OE
QREFB0
OE
QREFA1
OE
QREFA0
OE
23
SRPC[7]
SRPC[6]
SRPC[5]
SRPC[4]
SRPC[3]
SRPC[2]
SRPC[1]
SRPC[0]
REVISION 2 10/1/15
22
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Table 3K. SYSREF Control Register Function Descriptions
Bits
SRPC[7:0]
Name
SYSREF Pulse
Count
Factory
Default
0000 0000
Function
Binary value of the SYSREF pulses generated by the 8V19N407 and output at all enabled QREF outputs. Allows to generate 1 to 255 pulses after each write access. Requires SRO = 0. The programmed number of SYSREF pulses is generated after the
SYSREF synchronization procedure completes. See Section, “SYSREF Generation” on
page 12.
SYSREF Divider Value
NS[3:0]
SYNC
nPOWER
SYSREF
Frequency Divider
Synchronizer Power
Control
0100
0
NS3
NS2
NS1
NS0
Value
0
0
0
0
÷64
0
0
0
1
÷96
0
0
1
0
÷128
0
0
1
1
÷192
0
1
0
0
÷256
0
1
0
1
÷384
0
1
1
0
÷512
0
1
1
1
÷768
1
0
0
0
÷1024
1
0
0
1
÷2048
1
0
X
X
1010-1111 are undefined.
0 = SYSREF synchronizer power up
1 = SYSREF synchronizer power down
Power down the SYSREF synchronizer if all QREFn outputs are used as clock outputs.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
23
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 3K. SYSREF Control Register Function Descriptions (Continued)
Bits
Factory
Default
Name
Function
SYSREF Synchronizer divider value. This divider controls the release of SYSREF pulses at coincident QCLKAn and QCLKBn clock edges. For SYSREF operation, set this divider value to the least common multiple of the clock divider values NA and NB. For
instance, if NA = ÷2 and NB = ÷3, set the SYNC divider to ÷6 (SYNC[3:0] = 0100).
SYNC
N[3:0]
SRO
SYSREF
Synchronizer
Divider
SYNC3
SYNC2
SYNC1
SYNC0
0
0
0
0
÷2
0
0
0
1
÷3
0
0
1
0
÷4
0
0
1
1
÷5
0
1
0
0
÷6
0
1
0
1
÷8
0
1
1
0
÷10
0
1
1
1
÷12
1
0
0
0
÷16
1
0
0
1
÷20
1
0
1
0
÷24
1
0
1
1
÷32
1
1
0
0
÷40
1
1
0
1
÷48
1
1
1
0
÷80
1
1
1
1
÷96
1000
SYSREF Operation
1
Value
0 = Single SYSREF pulse generation mode.
Number of pulses is controlled by SRPC[7:0].
1 = Continuous SYSREF pulse generation
FemtoClock NG PLL Control Registers
The FemtoClock NG registers contain the setting for the divider, selection and power state.
Table 3L. FemtoClockNG PLL Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
24
QC
OE
Ch C
nPOWER
Reserved
SPI_REL
R/Wn
1
1
0
30
Reserved
Reserved
Reserved
Reserved
VCO_SEL
Reserved
INTEN1
INTEN0
Table 3M. FemtoClockNG PLL Control Register Function Descriptions
Bits
Name
VCO_SEL
VCO Frequency Select
SPI_REL
FemtoClock NG PLL Relock
REVISION 2 10/1/15
Factory
Default
Function
0
This bit must be set ‘0’
0
0 = no effect
1 = Creates a pulse that forces a re-lock on the FemtoClock NG PLL. Bit auto-clears. (Any changes of VCO-PLL parameters, such as Feedback Divider MF
requires re-locking using SPI_REL bit.)
24
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Status Registers
This register contains the clock status bits STAT[2:0] and latched copies of these bits (INT[1:0]).
Table 3N. Status Register Bit Allocations
Register Bit
Register
D7
10
D6
D5
D4
STAT2
STAT1
STAT0
D3
D2
D1
D0
Reserved
INT1
INT0
Table 3O. Status Register Function Descriptions
Bits
Name
STAT2
VCO Calibration
Factory
Default
Function
VCO calibration status:
1 = Completed
-
0 = Not completed
VCXO-PLL (1st stage) lock status:
STAT1
VCXO-PLL Lock Status
-
1 = VCXO-PLL is locked
0 = VCXO-PLL is unlocked
CLK Input clock status:
STAT0
Clock Input CLK Status
-
1 = CLK input clock is present
0 = CLK input clock not detected
INT[1:0]
Individual Interrupt Status &
Clear Bits
These bits contain a latched version of the STAT[1:0] bits: The INT[1:0] bits
indicate a fault condition (0) since the last interrupt clear command. Writing a 1 to
a INT[1:0] bit position will clear that interrupt latch, provided the corresponding
fault condition has also been cleared. Clearing the latch with the corresponding
STAT[1:0] bit still indicating a fault (0) will result in an immediate re-trigger of the
latch.
-
Interrupt Enable Register
This register controls the interrupt functions of the 8V19N407.
Table 3P. Interrupt Enable Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
30
Reserved
Reserved
Reserved
Reserved
SEL
Reserved
INTEN1
INTEN0
Table 3Q. Interrupt Enable Register Function Descriptions
Bits
INTEN[1:0]
Name
Interrupt Enable Bits
Factory
Default
00
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
Function
A setting of 0 in any of these bit positions will mask the corresponding INT[1:0]
latch bit from affecting the interrupt output signal (nINT). A setting of 1 in any
bit position will enable that INT[1:0] latch bit to drive the interrupt signal nINT.
Setting all INTEN[1:0] to 0 has the effect of disabling interrupts from the
device.
25
REVISION 2 10/1/15
8V19N407 DATA SHEET
Reset Control Registers
The Reset Control Registers contain the settings for the register
controlled-reset and restart capabilities of the device. Output divider
reset (NR_REQ0, NR_REQ1, NR_RESET): the divider reset
sequence is required after device startup and after any N divider
value change. See Section, “Clock Output Divider Reset Sequence,
(Sequence S1)” on page 14.
The QREF phase delay and SYSREF synchronization sequence is
required for the synchronization of the delay stages after each delay
stage configuration, and is also applicable for the generation of
SYSREF pulses. Sequence: write a logic 1 to SR_REQ0, SR_REQ1
and SR_RESET in this order to generate a programmable number of
SYSREF pulses at all enabled QREF outputs. See Section, “QREF
Phase Delay and SYSREF Synchronization Sequence, (Sequence
S2)” on page 14.
Table 3R. Reset Control Register Bit Allocations
Register Bit
Register
D7
D6
D5
D4
D3
D2
D1
D0
5
SR_REQ0
MV[14]
MV[13]
MV[12]
MV[11]
MV[10]
MV[9]
MV[8]
7
NR_REQ0
Reserved
SYNC
nPOWER
Reserved
SYNC
N[3]
SYNC
N[2]
SYNC
N[1]
SYNC
N[0]
25
SR_REQ1
Reserved
QCLKB1
A[1]
QCLKB1
A[0]
QCLKB1
EF
QCLKB0
A[1]
QCLKB0
A[0]
QCLKB0
EF
27
NR_REQ1
QVCXO
A[1]
QVCXO
A[0]
QVCXO
EF
Reserved
Reserved
Reserved
Reserved
29
SR_RESET
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
31
NR_RESET
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VCO_FSEL
REVISION 2 10/1/15
26
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Table 3S. Reset Control Register Function Descriptions
Bits
Name
NR_REQ0
NA, NB, NC Output Divider
Reset Request 01, Auto-clear
NR_REQ1
NA, NB, NC Output Divider
Reset Request 1, Auto-clear
Factory
Default
X
X
Function
Writing a 1 to the bit position D7 in register 7 is the first step of the
reset/re-synchronization sequence for the frequency dividers NA-C. All QCLK
outputs are set to the logic low stage. This bit auto-clears after the reset
sequence. Writing a 0 to this bit position has no effect.
Writing a 1 to the bit position D7 in register 29 is the second step of the
reset/re-synchronization sequence for the frequency dividers NA-C. After this
bit is set to logic 1, the dividers NA-C can be reset synchronously by writing a
logic 1 to the NR_RESET bit (register 31, bit position D7)
Independent on the selected output dividers NA-C, the QCLK outputs will then
restart with a rising edge simultaneously.
This bit clears itself after the completion of the reset sequence and QCLK[A-C]
outputs are reset. Writing a 0 to this bit position has no effect.
NR_RESET
NA, NB, NC Output Divider
Divider Reset Auto-clear
SR_REQ0
SYSREF Synchronization
Request 02, Auto-clear
SR_REQ1
SYSREF Synchronization
Request 1, Auto-clear
X
Writing a 1 to the bit position D7 in register 31 is the third and final step of the
reset/re-synchronization sequence for the frequency dividers NA-C. The
dividers re-start synchronously up to 10 clock periods after this reset bit is
written. This bit clears itself after the completion of the reset sequence and
QCLK[A-C] outputs are reset. Writing a 0 to this bit position has no effect.
X
Writing a 1 to the bit position D7 in register 5 is the first step of the
synchronization sequence for the SYSREF outputs (QREF). This bit
auto-clears after the reset sequence. Writing a 0 to this bit position has no
effect. Requires SRO = 0, otherwise no function.
X
Writing a 1 to the bit position D7 in register 27 is the second step of the
synchronization sequence for the SYSREF outputs (QREF). The NS divider is
reset. The SYSREF outputs (QREF) are active and set to logic low level in
preparation to the last step (SR_RESET). Requires SRO = 0, otherwise no
function.
This bit clears itself after the completion of the reset sequence and QREF
outputs are reset. Writing a 0 to this bit position has no effect.
Writing a 1 to the bit position D7 in register 29 is the third and final step of the
synchronization sequence for the SYSREF outputs (QREF).
SR_RESET
SYSREF Synchronization
Reset Auto-clear
X
After writing a 1 to SR_RESET, the number of SYSREF pulses programmed in
SRPC[7:0] are synchronously output at all enabled QREF outputs.
This bit clears itself after the completion of the synchronization sequence.
Writing a 0 to this bit position has no effect. Requires SRO = 0, otherwise no
function.
NOTE 1. See Section, “Clock Output Divider Reset Sequence, (Sequence S1)” on page 14.
NOTE 2. See Section, “QREF Phase Delay and SYSREF Synchronization Sequence, (Sequence S2)” on page 14.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
27
REVISION 2 10/1/15
8V19N407 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Table 4A. Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDDx
4.6V
Inputs
-0.5V to VDDx + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VDDx + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Junction Temperature, TJ
125C
Storage Temperature, TSTG
-65C to 150C
Table 4B. Pin Characteristics
Symbol
Parameter
CIN
Input
nLE, MOSI,
Capacitance SPICLK
4
pF
RPULLUP
Input Pullup Resistor
51
k
RPULLDOWN
Input Pulldown Resistor
51
k
ROUT
Output
Impedance
SELSV = 1 (3.3V)
30
SELSV = 0 (1.8V)
40
REVISION 2 10/1/15
Test Conditions
MISO, INT
28
Minimum
Typical
Maximum
Units
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
DC Electrical Characteristics
Table 5A. Power Supply DC Characteristics, VDDx = VDDQx = 3.3V ± 5%, TA = -40°C to +85°C1, 2, 3, 4
Symbol
Parameter
VDDx
Power Supply Voltage
VDDQx
Output Supply Voltage
IDDx
Test Conditions
IDDQx
Output Supply Current,
LVDS5, 7
Typical
Maximum
Units
3.135
3.3
3.465
V
3.135
Power Supply Current5
Output Supply Current,
LVPECL5, 6
Minimum
3.3
3.465
V
LVPECL Output Setting
325
350
mA
LVDS Output Setting
355
370
mA
400mV Amplitude Setting
300
400
mA
700mV Amplitude Setting
315
420
mA
1000mV Amplitude Setting,
fOUT > 500MHz
354
460
mA
400mV Amplitude Setting
452
550
mA
700mV Amplitude Setting
522
620
mA
1000mV Amplitude Setting,
fOUT > 500MHz
617
670
mA
NOTE 1. VDDx denotes VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7.
NOTE 2. VDDQx denotes VDDQA, VDDQB, VDDQC.
NOTE 3. IDDx denotes IDD1, IDD2, IDD3, IDD4, IDD5, IDD6, IDD7.
NOTE 4. IDDQx denotes IDDQA, IDDQB, IDDQC.
NOTE 5. Both VCXO-PLL and FemtoClock NG PLL are locked and all output clocks are running (QREFn are in QCLK mode). SYSREF delay
stages and synchronizer control are disabled.
NOTE 6. Outputs not terminated.
NOTE 7. Outputs not terminated with 100 across the differential pair.
Table 5B. LVCMOS/LVTTL DC Characteristics, VDDx = VDDQx = 3.3V ± 5%, TA = -40°C to +85°C1, 2
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
SPICLK, nLE, MOSI
IIL
Input
Low Current
VOH
Output
High Voltage
VOL
Output
Low Voltage
Maximum
Units
1.3
1.8
V
SELSV = 1
2.3
VDDX
V
SELSV = 0
-0.3
0.35
V
SELSV = 1
-0.3
0.6
V
VDD5 = 3.3V, VIN = 3.3V
150
µA
SELSV
VDD5 = 3.3V, VIN = 3.3V
5
µA
SPICLK, nLE, MOSI
VDD5 = 3.465V, VIN = 0V
-5
µA
SELSV
VDD5 = 3.465V, VIN = 0V
-150
µA
VDDQx = 3.465V, SELSV = 0
IOH = -2mA
1.65
V
VDDQx = 3.465V, SELSV = 1
IOH = -4mA
2.0
V
nINT, MISO
nINT, MISO
Test Conditions
Minimum
SELSV = 0
Typical
VDDQx = 3.465V, SELSV = 0
IOL = 2mA
0.15
V
VDDQx = 3.465V, SELSV = 1
IOL = 4mA
0.5
V
NOTE 1. VDDx denotes: VDD1, VDD2, VDD3, VDD4, VDD5, VDD6 and VDD7.
NOTE 2. VDDQx denotes VDDQA, VDDQB, VDDQC.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
29
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 5C. Differential Input DC Characteristics, VDD5 = 3.3V ± 5%, TA = -40°C to +85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
IIH
Input
High Current
CLK, nCLK,
VCXO, nVCXO
IIL
Input
Low Current
CLK, VCXO
VDD5 = 3.465V, VIN = 0V
-5
µA
nCLK, nVCXO
VDD5 = 3.465V, VIN = 0V
-150
µA
VDD5 = VIN = 3.465V
Maximum
Units
150
µA
Table 5D. LVPECL DC Characteristics (QCLKn, EF = 1), VDDQx = 3.3V ± 5%, GND = 0V, TA = -40°C to +85°C1
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDDQX – 1.41
VDDQX – 0.9
VDDQX – 0.55
V
400mV Amplitude Setting
VDDQX – 1.66
VDDQX – 1.3
VDDQX – 1.11
V
700mV Amplitude Setting
VDDQX – 1.965
VDDQX – 1.6
VDDQX – 1.35
V
1000mV Amplitude Setting,
fOUT >500MHz
VDDQX – 2.22
VDDQX – 2.0
VDDQX – 1.5
V
400mV Amplitude Setting
VOH
VOL
Output High Voltage2
700mV Amplitude Setting
1000mV Amplitude Setting,
fOUT >500MHz
Output Low Voltage2
NOTE 1. VDDQx denotes: VDDQA, VDDQB, VDDQC.
NOTE 2. Outputs terminated with 50 to VDDQx – 1.5V (400mV amplitude setting), VDDQx – 2.0V (700mV amplitude setting),
VDDQx – 2.5V (1000mV amplitude setting).
Table 5E. LVDS DC Characteristics (QCLKn, EF = 0), VDDQx = 3.3V ± 5%, GND = 0V, TA = -40°C to +85°C1
Symbol
VOS
VOS
Parameter
Offset Voltage2
Test Conditions
Minimum
Typical
Maximum
Units
400mV Amplitude Setting
2.3
V
700mV Amplitude Setting
2.1
V
1000mV Amplitude Setting,
fOUT >500MHz
1.9
V
20
mV
VOS Magnitude Change
NOTE 1. VDDQx denotes VDDQA, VDDQB, VDDQC.
NOTE 2. VOS changes with VDD.
Table 5F. LVDS DC Characteristics (QREFn), VDDQx = 3.3V ± 5%, GND = 0V, TA = -40°C to +85°C 1
Symbol
VOS
VOS
Parameter
Offset Voltage2
Test Conditions
Minimum
Typical
Maximum
Units
400mV Amplitude Setting
2.3
V
700mV Amplitude Setting
2.1
V
1000mV Amplitude Setting,
fOUT >500MHz
1.9
V
20
mV
VOS Magnitude Change
NOTE 1. VDDQx denotes VDDQA, VDDQB, VDDQC.
NOTE 2. VOS changes with VDD.
REVISION 2 10/1/15
30
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
AC Electrical Characteristics
Table 6A. AC Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V, TA = -40°C to +85°C 1
Symbol
Parameter
fVCO
VCO Frequency Range
QCLKx
fOUT
Output
Frequency2
QREFx
VPP
Peak-to-peak
Input Voltage3
VCMR
Common Mode Input Voltage4
Test Conditions
Minimum
8V19N407-19
8V19N407-24
400mV Amplitude Setting
fVCO ÷ 96
700mV Amplitude Setting
fVCO ÷ 96
LVPECL Differential Output
Voltage Swing, Peak-to-peak
VOD
VOD
tsk(o)
LVDS Differential Output
Voltage6
2000
MHz
2400
2500
MHz
fVCO
MHz
fVCO
MHz
0.2
1.4
V
1.1
VDD – 0.3
V
570
mV
500
700mV Amplitude Setting
fVCO ÷ 96
1000mV Amplitude Setting
500
310
425
700mV Amplitude Setting
500
730
1020
mV
1000mV Amplitude Setting
870
1080
1200
mV
400mV Amplitude Setting
620
850
1140
mV
700mV Amplitude Setting
1000
1460
2040
mV
1000mV Amplitude Setting
1740
2160
2400
mV
400mV Amplitude Setting
600
800
1000
mV
700mV Amplitude Setting
950
1400
1850
mV
1000mV Amplitude Setting
1450
2140
2600
mV
LVDS VOD Magnitude Change
50
mV
QCLKx
Same N divider, Delay = 0
65
110
ps
QCLKx
Any N Divider, Incident Rising Edge,
Delay = 0
75
140
ps
Output Skew7, 8 QREFx
Delay = 0
20
50
ps
Any Equal Delay Settings
20
50
ps
QREFx to
QCLKx
Any Divider, Incident Rising QCLK Edge,
Delay = 0
110
200
ps
QCLK
(LVPECL)
20% to 80%
700mV Amplitude setting
150
300
ps
QCLK
(LVDS)
20% to 80%
700mV Amplitude setting
150
300
ps
20%-80% - SELSV = 0
1000
2650
ps
20%-80% - SELSV = 1
600
1000
ps
QREFx
t R / tF
1900
fVCO ÷ 96
400mV Amplitude Setting
VO(PP)5
Units
400mV Amplitude Setting
CLK, nCLK
LVPECL Output Voltage
Swing, Peak-to-peak
Maximum
1000mV Amplitude Setting
Typical
Output
Rise/Fall Time,
Differential
Output
Rise/Fall Time9
Output Isolation
nINT, MISO
(LVCMOS)
fOUT = 1228.8MHz
52
58
77
dB
fOUT = 614.4MHz
55
59
80
dB
fOUT = 307.2MHz
58
69
79
dB
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
31
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 6A. AC Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V, TA = -40°C to +85°C 1 (Continued)
Symbol
Parameter
odc
Output
Duty Cycle
QCLK[8:0],
QREF[6:0]
Test Conditions
Minimum
Typical
Maximum
Units
Divide by1
42
48
54
%
Other Dividers
45
50
55
%
210
1000
ms
VCXO-PLL Bandwidth = 30Hz,
tLOCK
PLL Lock Time
Device fully powered, measured from
the first presence of a valid PLL
reference clock to the complete lock of
all PLLs
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions. VDDQx denotes VDDQA, VDDQB, VDDQC. VDDx denotes VDD1, VDD2, VDD3, VDD4,
VDD5, VDD6, VDD7.
NOTE 2. Used as clock output.
NOTE 3. VIL should not be less than -0.3V.
NOTE 4. Common mode input voltage is defined as the signal crosspoint.
NOTE 5. LVPECL outputs terminated with 50 to VDDQx – 1.5V (400mV amplitude setting), VDDQx – 2.0V (700mV amplitude setting), VDDQx
– 2.5V (1000mV amplitude setting).
NOTE 6. LVDS outputs terminated 100 across terminals.
NOTE 7. This parameter is defined in accordance with JEDEC standard 65.
NOTE 8. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 9. Single-ended output nINT terminated according to Figure 12.
REVISION 2 10/1/15
32
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Table 6B. 8V19N407-19 QCLK Phase Noise and Jitter Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V,
TA = -40°C to +85°C 1, 2, 3, 4, 5, 6
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Integration Range: 1kHz - 76.8MHz
104.7
160.6
fs
Integration Range: 12kHz - 20MHz
91.4
129.8
fs
N(10)
10Hz offset from Carrier
-50.5
N(100)
100Hz offset from Carrier
-85.6
1kHz offset from Carrier
-116.2
-93.0
dBc/Hz
10kHz offset from Carrier
-118.2
-114.3
dBc/Hz
100kHz offset from Carrier
-122.8
-119.3
dBc/Hz
800kHz offset from Carrier
-142.6
-139.8
dBc/Hz
1MHz offset from Carrier
-144.7
-141.7
dBc/Hz
Noise Floor
-154
300Hz - 100kHz
-87
-64
dBc
f = 983.04MHz
tjit(Ø)
RMS Phase Jitter (Random)
N(1k)
N(10k)
N(100k)
Single-side Band Phase Noise
N(800k)
N(1M)
N()
Spurious Attenuation
dBc/Hz
dBc/Hz
dBc/Hz
>100kHz
-85
-63
dBc
Phase Detector Spurious
-69
-61
dBc
Integration Range: 1kHz - 76.8MHz
108.1
172.0
fs
145.0
f = 491.52MHz
tjit(Ø)
RMS Phase Jitter (Random)
Integration Range: 12kHz - 20MHz
92.4
N(10)
10Hz offset from Carrier
-57.1
dBc/Hz
N(100)
100Hz offset from Carrier
-92.7
dBc/Hz
1kHz offset from Carrier
-123.4
-107.2
dBc/Hz
N(1k)
N(10k)
N(100k)
Single-side Band Phase Noise
N(800k)
N(1M)
fs
10kHz offset from Carrier
-124.5
-120.7
dBc/Hz
100kHz offset from Carrier
-128.9
-125.3
dBc/Hz
800kHz offset from Carrier
-148.2
-145.1
dBc/Hz
1MHz offset from Carrier
-150.0
-146.8
dBc/Hz
N()
Noise Floor
-157
300Hz - 100kHz
-93
-70
dBc
>100kHz
-85
-66
dBc
Phase Detector Spurious
-76
-63
dBc
Integration Range: 1kHz - 40MHz
124.1
175.4
fs
Integration Range: 12kHz - 20MHz
98.5
142.0
fs
N(10)
10Hz offset from Carrier
-63.0
N(100)
100Hz offset from Carrier
-98.2
1kHz offset from Carrier
-129.2
-112.0
dBc/Hz
10kHz offset from Carrier
-130.5
-125.6
dBc/Hz
100kHz offset from Carrier
-134.9
-131.1
dBc/Hz
800kHz offset from Carrier
-153.4
-150.7
dBc/Hz
1MHz offset from Carrier
-154.8
-152.0
dBc/Hz
Noise Floor
-160
dBc/Hz
300Hz - 100kHz
-95
dBc
>100kHz
-97
Phase Detector Spurious
-87
Spurious Attenuation
dBc/Hz
f = 245.76MHz
tjit(Ø)
RMS Phase Jitter (Random)
N(1k)
N(10k)
N(100k)
Single-side Band Phase Noise
N(800k)
N(1M)
N()
Spurious Attenuation
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
33
dBc/Hz
dBc/Hz
-78
dBc
dBc
REVISION 2 10/1/15
8V19N407 DATA SHEET
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. VDDQx denotes VDDQA, VDDQB, VDDQC. VDDx denotes VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7.
NOTE 3. Phase noise and spurious specifications apply for device operation with QREFn outputs inactive (no SYSREF pulses generated).
NOTE 4. A VCXO has been used with Phase Noise and Spurious Attenuation measurements with typical offset values of 1kHz -131dBc/Hz,
10kHz -155dBc/Hz, 100kHz -160dBc/Hz and 1MHz -162dBc/Hz.
NOTE 5. Voltage regulator to supply VDDX was used with a typical power supply rejection ratio of 80dB at 1kHz and ultra low noise generation
with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.
NOTE 6. Outputs configured as LVDS 700mV.
REVISION 2 10/1/15
34
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Table 6C. 8V19N407-24 QCLK Phase Noise and Jitter Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V,
TA = -40°C to +85°C 1, 2, 3, 4, 5, 6
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Integration Range: 1kHz - 76.8MHz
82.5
114.1
fs
Integration Range: 12kHz - 20MHz
73.7
103.5
fs
N(10)
10Hz offset from Carrier
-52.5
N(100)
100Hz offset from Carrier
-86.8
1kHz offset from Carrier
-116.9
-111.7
dBc/Hz
10kHz offset from Carrier
-118.1
-114.1
dBc/Hz
100kHz offset from Carrier
-122.7
-119.4
dBc/Hz
800kHz offset from Carrier
-142.7
-139.8
dBc/Hz
1MHz offset from Carrier
-144.7
-141.7
dBc/Hz
Noise Floor
-154
300Hz - 100kHz
-92
-75
dBc
f = 1228.8MHz
tjit(Ø)
RMS Phase Jitter (Random)
N(1k)
N(10k)
N(100k)
Single-side Band Phase Noise
N(800k)
N(1M)
N()
Spurious Attenuation
dBc/Hz
dBc/Hz
dBc/Hz
>100kHz
-85
-74
dBc
Phase Detector Spurious
-68
-60
dBc
Integration Range: 1kHz - 76.8MHz
99.8
132.0
fs
110.9
f = 614.4MHz
tjit(Ø)
RMS Phase Jitter (Random)
Integration Range: 12kHz - 20MHz
80.9
N(10)
10Hz offset from Carrier
-58.4
dBc/Hz
N(100)
100Hz offset from Carrier
-93.0
dBc/Hz
1kHz offset from Carrier
-122.3
-118.2
dBc/Hz
N(1k)
N(10k)
N(100k)
Single-side Band Phase Noise
N(800k)
N(1M)
fs
10kHz offset from Carrier
-123.6
-119.6
dBc/Hz
100kHz offset from Carrier
-128.3
-125.2
dBc/Hz
800kHz offset from Carrier
-147.7
-144.8
dBc/Hz
1MHz offset from Carrier
-149.4
-146.4
dBc/Hz
N()
Noise Floor
-154
300Hz - 100kHz
-95
-81
dBc
>100kHz
-85
-69
dBc
Phase Detector Spurious
-79
-68
dBc
Integration Range: 1kHz - 76.8MHz
101.9
136.4
fs
Integration Range: 12kHz - 20MHz
81.3
111.6
fs
N(10)
10Hz offset from Carrier
-64.0
N(100)
100Hz offset from Carrier
-98.7
1kHz offset from Carrier
-128.9
-124.9
dBc/Hz
10kHz offset from Carrier
-130.1
-122.0
dBc/Hz
100kHz offset from Carrier
-134.6
-131.3
dBc/Hz
800kHz offset from Carrier
-153.2
-150.2
dBc/Hz
1MHz offset from Carrier
-154.6
-151.5
dBc/Hz
Noise Floor
-160
Spurious Attenuation
dBc/Hz
f = 307.2MHz
tjit(Ø)
RMS Phase Jitter (Random)
N(1k)
N(10k)
N(100k)
N(800k)
N(1M)
Single-side Band Phase Noise
N()
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
35
dBc/Hz
dBc/Hz
dBc/Hz
REVISION 2 10/1/15
8V19N407 DATA SHEET
Table 6C. 8V19N407-24 QCLK Phase Noise and Jitter Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V,
TA = -40°C to +85°C 1, 2, 3, 4, 5, 6
Symbol
Parameter
Spurious Attenuation
Test Conditions
Minimum
Typical
Maximum
Units
300Hz - 100kHz
-98
-81
dBc
>100kHz
-96
-79
dBc
Phase Detector Spurious
-80
Integration Range: 1kHz - 40MHz
103.3
139.2
fs
Integration Range: 12kHz - 20MHz
83.7
114.7
fs
dBc
f = 156.25MHz
tjit(Ø)
RMS Phase Jitter (Random)
N(10)
10Hz offset from Carrier
-69.1
dBc/Hz
N(100)
100Hz offset from Carrier
-103.3
dBc/Hz
1kHz offset from Carrier
-133.5
-124.9
dBc/Hz
10kHz offset from Carrier
-137.2
-132.7
dBc/Hz
100kHz offset from Carrier
-142.4
-137.9
dBc/Hz
1MHz offset from Carrier
-158.4
-155.6
dBc/Hz
Noise Floor
-161.8
N(1k)
N(10k)
Single-side Band Phase Noise
N(100k)
N(1M)
N()
dBc/Hz
f = 125MHz
Integration Range: 1kHz - 40MHz
146.8
185.2
fs
Integration Range: 12kHz - 20MHz
109.8
142.4
fs
N(10)
10Hz offset from Carrier
-70.4
dBc/Hz
N(100)
100Hz offset from Carrier
-104.9
dBc/Hz
tjit(Ø)
RMS Phase Jitter (Random)
N(1k)
N(10k)
Single-side Band Phase Noise
N(100k)
N(1M)
N()
1kHz offset from Carrier
-135.8
-125.9
dBc/Hz
10kHz offset from Carrier
-139.0
-134.1
dBc/Hz
100kHz offset from Carrier
-143.8
-138.4
dBc/Hz
1MHz offset from Carrier
-157.3
-155.0
dBc/Hz
Noise Floor
-158.9
dBc/Hz
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. VDDQx denotes VDDQA, VDDQB, VDDQC. VDDx denotes VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7.
NOTE 3. Phase noise and spurious specifications apply for device operation with QREFn outputs inactive (no SYSREF pulses generated).
NOTE 4. A VCXO has been used with Phase Noise and Spurious Attenuation measurements with typical values of 1kHz -131dBc/Hz,
10kHz -155dBc/Hz, 100kHz -160dBc/Hz and 1MHz -162dBc/Hz.
NOTE 5. Voltage regulator to supply VDDX was used with a typical power supply rejection ratio of 80dB at 1kHz and ultra low noise generation
with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.
NOTE 6. Outputs configured as LVDS 700mV.
REVISION 2 10/1/15
36
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Table 6D. 8V19N407-19 QREF Phase Noise and Spurious Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V, TA = -40°C
to +85°C1, 2, 3, 4, 5, 6
Symbol
Parameter
N(1k)
N(10k)
N(100k)
Single-side Band Phase Noise
(SYSREF = 15MHz)
N(1M)
Test Conditions
Minimum
Typical
Maximum
Units
1kz offset from Carrier
-130
dBc/Hz
10kHz offset from Carrier
-150
dBc/Hz
100kHz offset from Carrier
-155
dBc/Hz
1MHz offset from Carrier
-156
dBc/Hz
300Hz - 100kHz
-90
dBc
>100kHz
-85
dBc
Phase Detector Spurious
-85
dBc
Spurious Attenuation
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. VDDQx denotes VDDQA, VDDQB, VDDQC. VDDx denotes VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7.
NOTE 3. Phase noise specifications are applicable for all outputs.
NOTE 4. A VCXO has been used with Phase Noise and Spurious Attenuation measurements with typical values of 1kHz -131dBc/Hz,
10kHz -155dBc/Hz, 100kHz -160dBc/Hz and 1MHz -162dBc/Hz.
NOTE 5. Voltage regulator to supply VDDX was used with a typical power supply rejection ratio of 80dB at 1kHz and ultra low noise generation
with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.
NOTE 6. Outputs configured as LVDS 700mV.
Table 6E. 8V19N407-24 QREF Phase Noise and Spurious Characteristics, VDDx = VDDQx = 3.3V ± 5%, GND = 0V,
TA = -40°C to +85°C1, 2, 3, 4, 5, 6
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
N(1k)
1kz offset from Carrier
-132
dBc/Hz
N(10k)
10kHz offset from Carrier
-147
dBc/Hz
100kHz offset from Carrier
-155
dBc/Hz
1MHz offset from Carrier
-156
dBc/Hz
300Hz - 100kHz
-88
dBc
>100kHz
-85
dBc
Phase Detector Spurious
-85
dBc
N(100k)
Single-side Band Phase Noise
(SYSREF = 19.2MHz)
N(1M)
Spurious Attenuation
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. VDDQx denotes VDDQA, VDDQB, VDDQC. VDDx denotes VDD1, VDD2, VDD3, VDD4, VDD5, VDD6, VDD7.
NOTE 3. Phase noise specifications are applicable for all outputs active, Nx not equal.
NOTE 4. A VCXO has been used with Phase Noise and Spurious Attenuation measurements with typical values of 1kHz -131dBc/Hz,
10kHz -155dBc/Hz, 100kHz -160dBc/Hz and 1MHz -162dBc/Hz.
NOTE 5. Voltage regulator to supply VDDX was used with a typical power supply rejection ratio of 80dB at 1kHz and ultra low noise generation
with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.
NOTE 6. Outputs configured as LVDS 700mV.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
37
REVISION 2 10/1/15
8V19N407 DATA SHEET
Noise Power
dBc
Hz
Typical Phase Noise at 1228.8MHz
Offset Frequency (Hz)
Noise Power
dBc
Hz
Typical Phase Noise at 307.2MHz
Offset Frequency (Hz)
REVISION 2 10/1/15
38
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Noise Power
dBc
Hz
Typical Phase Noise at 156.25MHz
Offset Frequency (Hz)
Noise Power
dBc
Hz
Typical Phase Noise at 125MHz
Offset Frequency (Hz)
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
39
REVISION 2 10/1/15
8V19N407 DATA SHEET
Noise Power
dBc
Hz
Typical Phase Noise at 983.04MHz
Offset Frequency (Hz)
Noise Power
dBc
Hz
Typical Phase Noise at 491.52MHz
Offset Frequency (Hz)
REVISION 2 10/1/15
40
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Noise Power
dBc
Hz
Typical Phase Noise at 245.76MHz
Offset Frequency (Hz)
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
41
REVISION 2 10/1/15
8V19N407 DATA SHEET
Parameter Measurement Information
nQCLKA[1:0],
nQCLKB[1:0],
nQCLKC,
nQREFA[1:0],
nQREFB[1:0]
nQx
Qx
nQy
QCLKA[1:0],
QCLKB[1:0],
QCLKC,
QREFA[1:0],
QREFB[1:0]
Qy
80%
80%
VOD
20%
20%
tR
tF
LVDS Output Rise/Fall Time
Differential Output Skew
nQCLKA[1:0],
nQCLKB[1:0], nQCLKC,
nQREFA[1:0], nQREFB[1:0]
VDD
QCLKA[1:0],
QCLKB[1:0], QCLKC,
QREFA[1:0], QREFB[1:0]
nCLK
V
Cross Points
PP
CLK
V
CMR
GND
Differential Input Level
nQCLKA[1:0],
nQCLKB[1:0],
nQCLKC,
nQREFA[1:0],
nQREFB[1:0]
QCLKA[1:0],
QCLKB[1:0],
QCLKC,
QREFA[1:0],
QREFB[1:0]
80%
Differential Output Duty Cycle/Pulse Width/Period
80%
80%
80%
VO(PP)
20%
20%
tR
MISO, nINT
tR
tF
tF
LVCMOS Output Rise/Fall Time
LVPECL Output Rise/Fall Time
REVISION 2 10/1/15
20%
20%
42
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVPECL Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Any unused LVPECL output pair can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, there should be no trace
attached.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
43
REVISION 2 10/1/15
8V19N407 DATA SHEET
Wiring the Differential Input to Accept Single-Ended Levels
Figure 4 shows how a differential input can be wired to accept single
ended levels. The reference voltage V1= VDD/2 is generated by the
bias resistors R1 and R2. The bypass capacitor (C1) is used to help
filter noise on the DC bias. This bias circuit should be located as close
to the input pin as possible. The ratio of R1 and R2 might need to be
adjusted to position the V1in the center of the input voltage swing. For
example, if the input clock is driven from a single-ended 2.5V
LVCMOS driver and the DC offset (or swing center) of this signal is
1.25V, the R1 and R2 values should be adjusted to set the V1 at
1.25V. The values below are for when both the single ended swing
and VDD are at the same voltage. This configuration requires that the
sum of the output impedance of the driver (Ro) and the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the input will attenuate the signal in half. This
can be done in one of two ways. First, R3 and R4 in parallel should
equal the transmission line impedance. For most 50 applications,
R3 and R4 can be 100. The values of the resistors can be increased
to reduce the loading for slower and weaker LVCMOS driver. When
using single-ended signaling, the noise rejection benefits of
differential signaling are reduced. Even though the differential input
can handle full rail LVCMOS signaling, it is recommended that the
amplitude be reduced while maintaining an edge rate faster than
1V/ns. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 4. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
REVISION 2 10/1/15
44
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL and other differential
signals. Both differential inputs must meet the VPP and VCMR input
requirements. Figure 5A to Figure 5C show interface examples for
the CLK /nCLK input with built-in 50 terminations driven by the most
common driver types. The input interfaces suggested here are
examples only. If the driver is from another vendor, use their
termination recommendation. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
Figure 5A. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 5C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 5B. CLK/nCLK Input Driven by a
3.3V LVDS Driver
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
45
REVISION 2 10/1/15
8V19N407 DATA SHEET
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 6. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Lead frame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
PIN
PIN PAD
SOLDER
EXPOSED HEAT SLUG
GROUND PLANE
THERMAL VIA
SOLDER
LAND PATTERN
(GROUND PAD)
PIN
PIN PAD
Figure 6. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
REVISION 2 10/1/15
46
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Termination Information
Termination for QCLK LVPECL Outputs (EF = 1)
.
Figure 7 shows an example of the termination for a QCLK LVPECL
driver. In this example, the transmission line characteristic
impedance is 50. The R1 and R2 50 resistors are matched load
terminations and are terminated to the voltage VT. VT should be set
to a voltage according to the output amplitude in Table 2G. The
termination resistors must be placed close to the receiver (line end)
VDDQx
VT = VDDx - 1.5V (400 mV Amplitude)
VT = VDDx - 2.0V (700 mV Amplitude)
VT = VDDx - 2.5V (1000 mV Amplitude)
VT
R1 = 50
R2 = 50
T = 50
QCLK
LVPECL (EF = 1)
Figure 7. QCLK LVPECL (EF = 1) Output Termination
Termination for QCLK LVDS Outputs (EF = 0)
Figure 8 and Figure 9 show examples of the termination for a QCLK
and QREF LVDS drivers. In these examples, the transmission line
characteristic impedance is 50. The 100 resistor R is matched to
the line impedance. The output amplitude is configurable, see Table
2G. The termination resistor must be placed close to the receiver
(line end) or is internal to the receiver.
VDDQx
(400mV Amplitude)
(700mV Amplitude)
(1000mV Amplitude)
T = 50
R = 100
QCLK
LVDS (EF = 0)
Figure 8. QCLK LVDS (EF = 0) Output Termination
VDDQx
T = 50
QREF
LVDS
R = 100
Figure 9. DC Termination for QREF LVDS Outputs
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
47
REVISION 2 10/1/15
8V19N407 DATA SHEET
AC Termination for QREF LVDS Outputs
Figure 10 shows an example of the AC termination for the QREF
LVDS driver. In this example, the transmission line characteristic
impedance is 50. A 100 AC-line termination must be placed close
to the receiver (line end) or is internal to the receiver. The receiver
input should be re-biased according to its common mode range
specifications.
VDDQx
0.1µF
T = 50
0.1µF
R = 100
QREF
LVDS
Figure 10. AC Termination for QREF LVDS Outputs
Figure 11 shows an example of the termination for the QREF LVDS
driver. In this example, the transmission line characteristic
impedance is 50. The 100 resistor R is matched to the line
impedance. The output amplitude is configurable, see Table 2G. The
termination resistor must be placed close to the receiver (line end). A
The receiver input should be re-biased according to its common
mode range specifications.
VDDQx
VBIAS
0.1µF
T=50
0.1µF
R = 100
QREF
LVDS
Figure 11. AC Termination for QREF LVDS Outputs
Termination for Single-ended Outputs (nINT)
.
Figure 12 shows an example of the series termination for the nINT
LVCMOS driver. In this example, the transmission line characteristic
impedance is 50
VDDQx
R = 10
T = 50
LVCMOS
Figure 12. Termination for single-ended Outputs
REVISION 2 10/1/15
48
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Schematic Example
Figure 13 and Figure 14 (next page) show an example 8V19N407
application schematic in which the device is operated at VDD = 3.3V.
To achieve optimum jitter performance, power supply isolation is
required to minimize device generated noise. The 8V19N407
provides separate power supplies to isolate any high switching noise
from coupling into the internal PLL as shown in Figure 14.
This example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure that the logic control inputs are
properly set for the application.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited the
0.1uf capacitor in each power pin filter should be placed on the device
side. The other components can be on the opposite side of the PCB.
Pull up and pull down resistors to set configuration pins can all be
placed on the PCB side opposite the device side to free up device
side area if necessary.
The required generic VCXO shown requires a separate power filter
and a termination for the VCXO output type. Since the type is not
specified, neither is a specific termination. The loop filter for the
external VCXO is three poles for best out of band rejection. The
corresponding loop filter for the internal VCO is specified as three
poles even though only two poles are populated. This leaves the
option of increasing the filter order based on system level test.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for a wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supplies frequencies, it is recommended that component
values be adjusted and if required, additional filtering be added.
Additionally, good general design practices for power plane voltage
stability suggests adding bulk capacitance in the local area of all
devices.
The output terminations and clock receivers shown in Figure 13 are
representative examples. AC coupled LVDS terminations are also
permissible as shown in the Section, “Termination Information”.
As with any high speed analog circuitry, the power supply pins are
vulnerable to board supply or device generated noise. This device
requires an external voltage regulator for the VDDx pins for isolation
of board supply noise. This regulator is indicated in the schematic by
the two different power supplies, VREG_3.3V and 3.3V. Consult the
voltage regulator specification for details of the required
performance.
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
For additional layout recommendations and guidelines, contact
clocks@idt.com.
49
REVISION 2 10/1/15
8V19N407 DATA SHEET
U2A
R1
15
56
57
58
59
60
SPICLK
MOSI
MISO
nLE
nI NT
LF
SPICLK
MOSI
MISO
nLE
nINT
0
R4
180
C1
C4
1.2nF
C2
DEPOP
56nF
3.3V
VCOR
VCO
R2
1k
3
20
C3
4. 7uF
21
62
Z o = 50 Ohm
23
24
Z o = 50 Ohm
SELSV
C
QVCXO
nQVCXO
+
R3
100
65
66
Z o = 50 Ohm
-
CR
QCLKA0
nQCLKA0
7
8
CLK_IN
QCLKA0
nQCLKA0
Z o = 50 Ohm
LVDS Rec eiv er
R6 50
+
R5
Z o = 50 Ohm
100
61
QCLKA1
nQCLKA1
9
10
Z o = 50 Ohm
LVDS Driver
QREFA0
nQREFA0
4
5
C5
30k
C6
R8
50
QREFA0
nQREFA0
R9
71
-
R7 50
nCLK_IN
+3.3V LVPECL Receiv er
Z o = 50 Ohm
LFV
R11
20k
QREFA1
nQREFA1
1nF
+
R10
100
12
13
Z o = 50 Ohm
-
8nF
C7
QCLKB0
nQCLKB0
10uF
3. 3V
1
48
47
QCLKB0
nQCLKB0
LVDS Rec eiv er
FB1
2
Z o = 50 Ohm
BLM18BB221SN1
C8
0.1uF
C9
10uF
QCLKB1
nQCLKB1
+
R12
100
46
45
Z o = 50 Ohm
-
C10
QREFB0
nQREFB0
VCC
U7
QREFB0
nQREFB0
43
42
QREFB1
nQREFB1
LVDS Rec eiv er
6
0.1uF
51
50
1
GND
VC
4
68
OUT_P
VCXO
5
OUT_N
69
QREFB1
nQREFB1
Zo = 50 Ohm
nVCXO
3
+
VCXO
QCLKC
nQCLKC
54
53
R13
100
Zo = 50 Ohm
R14
R15
150
150
+3.3V LVPECL Rec eiv er
Figure 13. Signal I/O, External VCXO and Loop Filters
REVISION 2 10/1/15
50
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
VREG_3.3V
F B2
1
2
VDD7
U2B
70
VDD7
C13
BLM18BB221SN1
C11
C12
0.1uF
10uF
3.3V
0.1uF
VDDQA
VDDQA
VREG_3.3V
6
11
1
2
C15
10uF
0.1uF
VDD6
1
BLM18BB221SN1
C14
0.1uF
67
BLM18BB221SN1
C18
0.1uF
2
VDDQA
C16
F B4
FB3
C17
0.1uF
C20
C19
10uF
0.1uF
3.3V
VREG_3.3V
FB5
F B6
1
2
63
VDD5
VDD5
VDDQB
VDDQB
44
49
VREG_3.3V
2
C27
C25
10uF
0.1uF
1
C21
BLM18BB221SN1
0.1uF
C23
10uF
C22
BLM18BB221SN1
C24
0.1uF
VDDQB
C26
0.1uF
0.1uF
FB7
1
2
BLM18BB221SN1
C28
0.1uF
27
26
19
VDD 4
C30
C29
10uF
VDD4
VDD4
VDD4
FB8
52
VDDQC
C31
0.1uF
C33
VDDQC
C32
0.1uF
0.1uF
2
3.3V
1
BLM18BB221SN1
C34
10uF
C35
0.1uF
0.1uF
VREG_3.3V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
F B9
1
2
BLM18BB221SN1
C36
0.1uF
37
18
VDD3
C38
C37
10uF
VDD3
VDD3
C39
0.1uF
0.1uF
VREG_3.3V
1
F B10
2
BLM18BB221SN1
C40
0.1uF
39
16
VDD2
C42
C41
10uF
VDD2
VDD2
22
25
28
29
30
31
32
34
33
35
36
40
C43
0.1uF
0.1uF
VREG_3.3V
F B11
2
BLM18BB221SN1
C45
10uF
VDD1
73
C46
0.1uF
ePAD
2
14
17
38
41
55
64
72
C44
0.1uF
1
VDD1
GND
GND
GND
GND
GND
GND
GND
GND
1
Figure 14. Power Filters
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
51
REVISION 2 10/1/15
8V19N407 DATA SHEET
Power Considerations
The 8V19N407 device was designed and characterized to operate within the ambient extended temperature range of -40°C to 85°C.The
ambient temperature represents the temperature around the device, not the junction temperature. Extreme care must be taken to avoid
exceeding the 125°C junction temperature, potentially damaging the device.
Equations and example calculations are also provided below.
1.
Power Dissipation.
The power dissipation for the 8V19N407 is the product of supply voltage and total IDD.
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V at ambient temperature of 85°C.
Maximum current at 85°C, IDD_TOTAL_MAX = IDD_MAX + IDDQ_MAX (All QCLKx and QVCXO are running with 700mV amplitude in LVDS mode
and Continuous SYSREFs are running with 400mV amplitude in LVDS mode)
•
Total Power Dissipation: PD = VDD_MAX * IDD_MAX = 3.465V * (370mA + 620mA) = 3.430W
2. Junction Temperature.
Junction temperature, Tj, signifies the hottest point on the device and exceeding the specified limit could cause device reliability issues.
The maximum recommended junction temperature is 125°C.
For devices like this and in systems where most heat escapes from the bottom exposed pad of the package, JB is the primary thermal
resistance of interest.
The equation to calculate Tj using JB is: Tj = JB * PD + TB
Tj = Junction Temperature
JB = Junction-to-Board Thermal Resistance
PD = Device Power Dissipation (example calculation is in section 1 above)
TB = Board Temperature
In order to calculate junction temperature, the appropriate junction-to-board thermal resistance JB must be used. Assuming a 2-ground plane
board, the appropriate value of JB is 0.713°C/W per Table 7 below.
Therefore, Tj for a PCB maintained at 115°C with all outputs switching is:
115°C + 3.430W * 0.713°C/W = 117.4°C which is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, heat transfer
method, the type of board (multi-layer) and the actual maintained board temperature. The below table is for two ground planes. The thermal
resistance will change as the number of layers in the board changes or if the board size change and other changes in other factors impacts
heat dissipation in the system.
Table 7. Thermal Resistances for 72-Lead VFQFN Package
Air Flow (m/s)
0
1
2
JB
0.713°C/W
0.713°C/W
0.713°C/W
JA
19.16°C/W
15.49°C/W
14.14°C/W
NOTE: Applicable to PCBs with two ground planes.
NOTE: ePAD size is 8.4mm x 8.4mm and connected to ground plane in PCB through 8 x 8 Thermal Via Array.
NOTE: In devices where most of the heat exits through the bottom ePAD, JB is commonly used for thermal calculations.
Transistor Count
The transistor count for 8V19N407 is: 46,972
REVISION 2 10/1/15
52
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
72 VFQFN Package Information
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
53
REVISION 2 10/1/15
8V19N407 DATA SHEET
72 VFQFN Package Information, Continued
REVISION 2 10/1/15
54
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
8V19N407 DATA SHEET
Ordering Information
Table 8. Ordering Information with MISO Output in High Impedance
Part/Order Number
Marking
8V19N407Z-19NLGI
IDT8V19N407Z-19NLGI
VCO
Frequency
Package
Shipping
Packaging
Temperature
72 Lead VFQFN, Lead-Free
Tray
-40C to 85C
72 Lead VFQFN, Lead-Free
Tape & Reel
-40C to 85C
72 Lead VFQFN, Lead-Free
Tray
-40C to 85C
72 Lead VFQFN, Lead-Free
Tape & Reel
-40C to 85C
1900 - 2000MHz
8V19N407Z-19NLGI8
IDT8V19N407Z-19NLGI
8V19N407Z-24NLGI
IDT8V19N407Z-24NLGI
2400 - 2500MHz
8V19N407Z-24NLGI8
IDT8V19N407Z-24NLGI
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
55
REVISION 2 10/1/15
8V19N407 DATA SHEET
Revision History Sheet
Rev
Table
Page
Table 6A
31
2
REVISION 2 10/1/15
Description of Change
Date
AC Characteristics Table - typographical spec errors for VO(pp):
LVPECL Output Voltage Swing
(400mV Amplitude Setting) minimum and maximum specs;
LVPECL Differential Output Voltage Swing
(400mV Amplitude Setting) minimum, typical and maximum specs
(1000mV Amplitude Setting) typical spec
56
10/1/15
FEMTOCLOCK® NG JITTER ATTENUATOR AND CLOCK SYNTHESIZER
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Tech Support
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this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
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