8V19N470BFGI

FemtoClock® NG Jitter Attenuator and Clock Synthesizer 8V19N470 Datasheet Description Features The 8V19N470 is a fully integrated FemtoClock® NG jitter attenuator and clock synthesizer designed as a high-performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. ▪ High-performance clock RF-PLL ▪ Optimized for low phase noise: ≤150dBc/Hz (1MHz offset; 245.76MHz clock) ▪ Dual-PLL architecture — 1st-PLL stage with external VCXO for clock jitter attenuation — 2nd-PLL stage with internal FemtoClock NG PLL at selectable 2949.12MHz and 2400MHz  2500MHz VCO ▪ Five output channels with a total of 11 outputs, organized in: — Two clock channels with two differential outputs — Two clock channels with three differential outputs — One VCXO-PLL channel with one selectable LVDS/ two LVCMOS outputs ▪ Each clock channel contains an integer output divider and a phase delay circuit with 512 steps of half of the VCO period ▪ Supported clock output frequencies include: — From VCO-0: 2949.12MHz, 1474.56MHz, 983.04MHz, 491.52MHz, 368.64MHz, 122.88MHz — From VCO-1: 2457.6MHz, 1228.8MHz, 614.4MHz, 307.2MHz, 153.6, 76.8MHz or 625MHz, 500MHz, 312.5MHz, 250MHz, 156.25MHz, and 125MHz ▪ Low-power LVPECL/LVDS outputs support configurable signal amplitude, DC and AC coupling and LVPECL, LVDS line terminations techniques ▪ Redundant input clock architecture — Two inputs — Individual input signal monitor — Digital holdover — Manual and automatic clock selection — Hitless switching ▪ Status monitoring and fault reporting — Input signal status — Lock status of each individual PLL (two status pins) — Hold-over and reference loss status — Mask-able status interrupt pin ▪ Voltage supply: — Device core supply voltage: 3.3V — Output supply voltage: 3.3V, 2.5V or 1.8V — Digital control I/O voltage: 1.8V (3.3V tolerant) — SPI control I/O voltage: 1.8V or 3.3V (selectable), 3.3V tolerant inputs when set to 1.8V ▪ Package: 81-FPBGA (8  8  1.35 mm, 0.8mm ball pitch) ▪ Temperature range: -40°C to +85°C The device is optimized to deliver excellent phase noise performance as required in GSM, WCDMA, LTE, LTE-A radio board implementations. A two-stage PLL architecture supports both jitter attenuation and frequency multiplication. The first stage PLL is the jitter attenuator and uses an external VCXO for best possible phase noise characteristics. The second stage PLL locks on the VCXO-PLL output signal and synthesizes the target frequency. This PLL has two VCO circuits at 2949.12MHz and 2400MHz–2500MHz, respectively, for enhanced frequency flexibility. The device generates the output clock signals from the selected VCO by frequency division. Four independent integer frequency dividers are available. Delay circuits can be used for achieving alignment and controlled phase delay between clock signals. The two redundant inputs are monitored for activity. Four selectable clock switching modes are provided to handle clock input failure scenarios. Auto-lock, individually programmable output frequency dividers and phase adjustment capabilities are added for flexibility. The device is configured through an SPI interface and reports PLL lock and signal loss status in internal registers, PLL lock status is also reported via two lock detect outputs. Internal status bit changes can also be reported via the nINT output. The device is ideal for driving converter circuits in wireless infrastructure, radar/imaging and instrumentation/medical applications. The device is a member of the high-performance clock family from IDT. Typical Applications ▪ Low phase noise clock generation, specifically for jitter-sensitive ADC and DAC circuits ▪ Wireless infrastructure applications: GSM, WCDMA, LTE, LTE-A ▪ Ethernet ©2017 Integrated Device Technology, Inc. 1 November 20, 2017 8V19N470 Datasheet Block Diagram Figure 1. Block Diagram VCXO-PLL Loop Filter VDD_LCF RZ CLK_0 nCLK_0 CLK_1 nCLK_1 Clock Monitor and Selector ÷PV ÷MV 4.7µF CP PV0, PV1 CZ PFD CP CR0 OSC LFV BYPV ÷PF FDF nOSC PFD CP x2 fVCO VDD_LCF 2949.12MHz 4.7µF CR1 EXT_SEL[1:0] 2400-2500MHz VCO LFF Dual FemtoClockNG CZF ÷MF Holdover CPF FemtoClock NG PLL Loop  Filter RZF LFFR QCLK_V nQCLK_V VCXO-PLL Channel CLKA ÷NA (int) Channel A CLKB ÷NB (int) Channel B CLKC ÷NC (int) QCLK_A0 nQCLK_A0 QCLK_A1 nQCLK_A1 QCLK_A2 nQCLK_A2 QCLK_B0 nQCLK_B0 QCLK_B1 nQCLK_B1 QCLK_B2 nQCLK_B2 QCLK_C0 nQCLK_C0 QCLK_C1 nQCLK_C1 Channel C RES_CAL CLKD 2.8k ÷ND (int) QCLK_D0 nQCLK_D0 QCLK_D1 nQCLK_D1 Channel D SDO SDIO SCLK nCS nRESET nINT SPI 1.8V/3.3V LOCK_F Register File ©2017 Integrated Device Technology, Inc. LOCK_V 2 November 20, 2017 8V19N470 Datasheet Pin Assignments Figure 2. Ball Map for 8  8  1.35mm, 81-CABGA Package with 0.8mm Ball Pitch  Bottom View A QCLK _A2 VDDO_ QCLKA LFV VDD_ CPV VDD_ OSC Q_CLK  V VDD_ SPI nQCLK _D0 QCLK _D0 B nQCLK _A2 VDD_ QCLKA RES_ CAL OSC nOSC nQ_CLK  V EXT_ SEL0 nQCLK _D1 QCLK _D1 C QCLK _A1 nQCLK _A1 GND SDO SDIO nINT nCS VDD_ QCLKD VDDO_ QCLKD D QCLK _A0 nQCLK _A0 GND CLK_0 CLK_1 SCLK nRESET GND VDD_ LOGIC E GND GND GND nCLK_0 nCLK_1 VDD_ INP LOCK _V EXT_ SEL1 LOCK _F F QCLK _B2 nQCLK _B2 GND GND GND GND GND GND GND G QCLK_ B1 nQCLK _B1 CLDO0 CBIAS0 CLDO1 CBIAS1 GND VDD_ QCLKC VDDO_ QCLKC H nQCLK _B0 VDD_ QCLKB GND CR0 CR1 VDD_ LCV GND nQCLK _C1 QCLK _C1 J QCLK _B0 VDDO_ QCLKB VDD_ CPF LFF LFFR VDD_ LCF GND nQCLK _C0 QCLK _C0 9 8 7 6 5 4 3 2 1 ©2017 Integrated Device Technology, Inc. 3 November 20, 2017 8V19N470 Datasheet Pin Descriptions Table 1. Pin Descriptions[a] Number Name D6 CLK_0 E6 nCLK_0 D5 CLK_1 Type[b] Description PD Input PD/PU PD Input Device clock 1 inverting and non-inverting differential clock input. Inverting input is biased to VDD_V / 2 by default when left floating. Compatible with LVPECL, LVDS and LVCMOS signals. E5 nCLK_1 B3 EXT_SEL0 Input PD Clock reference select 0. 1.8V LVCMOS interface levels. 3.3V tolerant. E2 EXT_SEL1 Input PD Clock reference select 1. 1.8V LVCMOS interface levels. 3.3V tolerant. D9, D8 QCLK_A0, nQCLK_A0 Output Differential clock output A0 (Channel A). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKA supply voltage. C9, C8 QCLK_A1, nQCLK_A1 Output Differential clock output A1 (Channel A). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKA supply voltage. A9, B9 QCLK_A2, nQCLK_A2 Output Differential clock output A2 (Channel A). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKA supply voltage. J9, H9 QCLK_B0, nQCLK_B0 Output Differential clock output B0 (Channel B). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKB supply voltage. G9, G8 QCLK_B1, nQCLK_B1 Output Differential clock output B1 (Channel B). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKB supply voltage. F9, F8 QCLK_B2, nQCLK_B2 Output Differential clock output B2 (Channel B). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKB supply voltage. J1, J2 QCLK_C0, nQCLK_C0 Output Differential clock output C0 (Channel C). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKC supply voltage. H1, H2 QCLK_C1, nQCLK_C1 Output Differential clock output C1 (Channel C). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKC supply voltage. A1, A2 QCLK_D0, nQCLK_D0 Output Differential clock output D0 (Channel D). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKD supply voltage. B1, B2 QCLK_D1, nQCLK_D1 Output Differential clock output D1 (Channel D). Configurable LVPECL/LVDS style and amplitude. Output levels are determined by the VDDO_QCLKD supply voltage. A4, B4 QCLK_V, nQCLK_V Output Differential VCXO-PLL clock outputs. Selectable LVPECL/LVDS/ (2x LVCMOS 1.8V) style. ©2017 Integrated Device Technology, Inc. PD/PU Device clock 0 inverting and non-inverting differential clock input. Inverting input is biased to VDD_V / 2 by default when left floating. Compatible with LVPECL, LVDS and LVCMOS signals. 4 November 20, 2017 8V19N470 Datasheet Table 1. Pin Descriptions[a] (Cont.) Type[b] Number Name C4 nINT Output Status output pin for signaling internal changed conditions. Selectable 1.8V/3.3V LVCMOS interface levels. E3 LOCK_V Output PLL lock detect status output for the VCXO-PLL. Selectable 1.8V/3.3V LVCMOS interface levels. E1 LOCK_F Output PLL lock detect status output for the FemtoClock NG PLL. Selectable 1.8V/3.3V LVCMOS interface levels. C5 SDIO Input/Output Serial Control Port SPI Mode Clock Input/Output. Selectable 1.8V/3.3V LVCMOS interface levels for output. 1.8V interface levels (with hysteresis) when input. C6 SDO Output D4 SCLK Input PD Serial Control Port SPI Clock. electable 1.8V interface levels (with hysteresis). 3.3V tolerant. C3 nCS Input PU Serial Control Port SPI Chip Select Input. 1.8V interface levels (with hysteresis). 3.3V tolerant. D3 nRESET Input PU SPI interface reset. 1.8V interface levels. 3.3V tolerant. H6 CR0 Analog Internal VCO (0) regulator bypass capacitor. Use a 4.7 µF capacitor between the CR0 and the VDD_LCF terminals. H5 CR1 Analog Internal VCO (1) regulator bypass capacitor. Use a 4.7 µF capacitor between the CR1 and the VDD_LCF terminals. A7 LFV Output VCXO-PLL charge pump output. Connect to the loop filter for the external VCXO. B6, B5 OSC, nOSC Input J6 LFF Output Loop filter/charge pump output for the FemtoClock NG PLL. Connect to the external loop filter. J5 LFFR Analog Ground return path pin for the VCO loop filter. B7 RES_CAL Analog Connect a 2.8 k (1%) resistor to GND for output current calibration. C7, D2, D7, E7, E8, E9, F1, F2, F3, F4, F5, F6, F7, G3, H3, H7, J3 GND Power Ground supply voltage (GND) and ground return path. Connect to board GND (0V). G4 CBIAS1 Analog Internal bias circuit for VCO-1. Connect a 4.7µF capacitor to GND. G5 CLDO1 Analog Internal LDO bypass for VCO-1. Connect a 10µF capacitor to GND. G6 CBIAS0 Analog Internal bias circuit for VCO-0. Connect a 4.7µF capacitor to GND. G7 CLDO0 Analog Internal LDO bypass for VCO-0. Connect a 10µF capacitor to GND. A8 VDDO_QCLKA Power Positive supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_A[2:0] outputs. ©2017 Integrated Device Technology, Inc. Description Serial Control Port SPI Mode Output. Selectable 1.8V/3.3V LVCMOS interface levels. VCXO non-inverting and inverting differential clock input. Compatible with LVPECL, LVDS and LVCMOS signals. 5 November 20, 2017 8V19N470 Datasheet Table 1. Pin Descriptions[a] (Cont.) Type[b] Number Name Description B8 VDD_QCLKA Power Positive supply voltage (3.3V) for channel A. J8 VDDO_QCLKB Power Positive supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_B[2:0] outputs. H8 VDD_QCLKB Power Positive supply voltage (3.3V) for channel B. G1 VDDO_QCLKC Power Positive supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_C[1:0] outputs. G2 VDD_QCLKC Power Positive supply voltage (3.3V) for channel C. C1 VDDO_QCLKD Power Positive supply voltage (3.3V, 2.5V or 1.8V) for the QCLK_D[1:0] outputs. C2 VDD_QCLKD Power Positive supply voltage (3.3V) for channel D. D1 VDD_LOGIC Power Positive supply voltage (3.3V). A3 VDD_SPI Power Positive supply voltage (3.3V) for the SPI interface. E4 VDD_INP Power Positive supply voltage (3.3V) for the differential inputs (CLK[1:0]). H4 VDD_LCV Power Positive supply voltage (3.3V) for the VCXO-PLL. J4 VDD_LCF Power Positive supply voltage (3.3V) for the internal oscillator of the FemtoClock NG PLL. For essential information on power supply filtering, see Power Supply Filtering. A6 VDD_CPV Power Positive supply voltage (3.3V) for internal VCXO_PLL circuits. J7 VDD_CPF Power Positive supply voltage (3.3V) for internal FemtoClock NG circuits. A5 VDD_OSC Power Positive supply voltage (3.3V) for the VCXO input. [a] For essential information on power supply filtering. See Power Supply Filtering. [b] PU (pull-up) and PD (pull-down) indicate internal input resistors. For values (see Table 46). ©2017 Integrated Device Technology, Inc. 6 November 20, 2017 8V19N470 Datasheet Principles of Operation Overview The device generates low-phase noise, synchronized clock output signals locked to an input reference frequency. The device contains two PLLs with configurable frequency dividers. The first PLL (VCXO-PLL, suffix V) uses an external VCXO as the oscillator and provides jitter attenuation. The external loop filter is used to set the VCXO-PLL bandwidth frequency in conjunction with internal parameters. The second, low-phase noise PLL (FemtoClock NG, suffix F) multiplies the VCXO-PLL frequency to one of its two selectable VCO frequencies of 2949.12MHz or 2457.6MHz. The FemtoClock NG PLL is completely internal and provides a central reference timing reference point for all output signals. From this point, fully synchronous dividers generate the output frequencies. The device has four output channels A – D, each with one integer output divider A – D. The clock outputs are configurable with support for LVPECL, LVDS formats and a variable output amplitude. In channels A – D, the clock phase can be adjusted in phase. For reduced power consumption, individual outputs, channels and unused circuit blocks support a power-down state. The register map, accessible through a selectable 3/4-wire SPI interface with read-back capability controls the main device settings and delivers device status information. For redundancy purpose, there are two selectable reference frequency inputs and a configurable switch logic with manual, auto-selection and holdover support. Phase-Locked Loop Operation Frequency Generation Table 2 displays the available frequency dividers for clock generation. The dividers must be set by the user to match input, VCXO and VCO frequency and to achieve frequency and phase lock on both PLLs. The frequency of the external VCXO is chosen by the user, the internal VCO frequency can be selected at frequencies of 2949.12MHz or 2457.6MHz. Table 3 – Table 7 shows example divider configurations for typical wireless infrastructure applications. Table 2. PLL Divider Values Operation Divider VCXO-PLL Range 1…32767: (15-bit) Pre-Divider PV[a] VCXO-PLL Feedback Divider MV 1…32767: (15-bit) Jitter Attenuation (Dual PLL, BYPV  0) Input clock frequency: 1…63: (6-bit) FemtoClock NG Feedback Dividers MF 8 …511 (9-bit) Output Divider Nx, xA–D 1…160 No external VCXO required f VCXO f CLK = P V  ---------------MV VCXO frequency: FemtoClock NG Pre-Divider PF Frequency Synthesis (VCXO-PLL bypassed, BYPV  1) Input clock frequency: PF f VCXO = --------  f VCO MF PF f CLK = --------  f VCO MF fVCO  2949.12MHz or 2457.6MHz fVCO  2949.12MHz or 2457.6MHz PF: Set PF to 0.5 in above equation if the frequency doubler is engaged by setting FDF  1 PF: Set PF to 0.5 in above equation if the frequency doubler is engaged by setting FDF  1 Output frequency f VCO f OUT = -----------NX [a] PV divider settings are in the PV0 register (for CLK_0) and in the PV1 register (for CLK_1). The device loads the PV divider from PV0 or PV1 according to the input selection. For details (see Table 13). ©2017 Integrated Device Technology, Inc. 7 November 20, 2017 8V19N470 Datasheet VCXO-PLL The prescaler PV and the VCXO-PLLs feedback divider MV require configuration to match the input frequency to the VCXO-frequency. With a MV and PV divider value range of 15 bits, the device supports a wide range of input and VCXO-frequencies. Two different input frequencies may be applied to the clock inputs CLK_0 and CLK_1. The single PV divider has two correspond divider registers, PV0 and PV1. PV0 is loaded into the PV divider when the CLK_0 input is selected and PV1 is loaded into the PV divider with the selection of the CLK_1 input. For clock selection information, see Table 13. Both CLK_0 and CLK_1 inputs may be monitored for input activity. For information, see Monitoring. In addition, the range of available input and feedback dividers allows to adjust the phase detector frequency independent of the used input and VCXO frequencies as shown in Table 3 and Table 4. The VCXO-PLL charge pump current is controllable via internal registers and can be set in 50µA steps from 50µA to 1.6mA. The VCXO-PLL may be bypassed (BYPV): when in bypass, the FemtoClock NG PLL locks to the pre-divided input frequency for frequency synthesis. Table 3. Example Configurations for fVCXO  30.72MHz VCXO-PLL Divider Settings Input Frequency (MHz) PV MV fPFD (MHz) 4 1 30.72 16 4 7.68 64 16 1.92 256 64 0.48 15625 3072 0.01 122.88 156.25 Table 4. Example Configurations for fVCXO  122.88MHz VCXO-PLL Divider Settings Input Frequency (MHz) 122.88 PV MV fPFD (MHz) 4 4 30.72 16 16 7.68 64 64 1.92 256 256 0.48 Table 5. Example Configurations for fVCXO  153.6MHz VCXO-PLL Divider Settings Input Frequency (MHz) 122.88 156.25 ©2017 Integrated Device Technology, Inc. PV MV fPFD (MHz) 4 5 30.72 16 20 7.68 64 80 1.92 256 320 0.48 3125 3072 0.05 8 November 20, 2017 8V19N470 Datasheet Table 6. Example Configurations for fVCXO  125MHz VCXO-PLL Divider Settings Input Frequency (MHz) 25 19.44 125 156.25 PV MV fPFD (MHz) 1 5 25 4 20 6.25 16 80 1.5625 64 320 0.390625 486 3125 0.04 1 1 125 5 5 25 25 25 5 125 125 1 5 4 31.25 50 40 3.125 500 400 0.3125 Table 7. Example Configurations for fVCXO  156.25MHz VCXO- PLL Divider Settings Input Frequency (MHz) PV MV fPFD (MHz) 19.44 1944 15625 0.01 4 25 6.25 40 250 0.625 400 2500 0.0625 4 5 31.25 40 50 3.125 400 500 0.3125 1 1 156.25 10 10 15.625 100 100 1.5625 25 125 156.25 ©2017 Integrated Device Technology, Inc. 9 November 20, 2017 8V19N470 Datasheet Table 8. VCXO-PLL Bypass Settings BYPV Operation 0 VCXO-PLL operation. 1 VCXO-PLL bypassed and disabled. The reference clock for the FemtoClock NG PLL is the selected input clock. Use EXT_SEL[1:0] for reference selection (00 or 01) or holdover (11). Device synthesizes an output frequency but will not attenuate input jitter. No external VCXO component and VCXO-PLL loop filter required. EXT_SEL[1:0]  10 operation modes are not defined for VCXO-PLL bypass operation. FemtoClock NG PLL The FemtoClock NG PLL is the second stage PLL and locks to the output signal of the VCXO-PLL (BYPV 0). It requires configuration of the frequency doubler FDF or the pre-divider PF and the feedback divider MF to match the VCXO-PLL frequency to the selected VCO frequency of 2949.12MHz or 2457.6MHz. Best phase noise is typically achieved by engaging the internal frequency doubler (FDF  1, 2). If engaged, the signal from the first PLL stage is doubled in frequency, increasing the phase detector frequency of the FemtoClock NG PLL. Enabling the frequency doubler disables the frequency pre-divider PF. If the frequency doubler is not used (FDF 0), the PF pre-divider has to be configured. Typically PF is set to 1 to keep the phase detector frequency as high as possible. Set PF to other divider values to achieve specific frequency ratios between first and second PLL stage. This PLL is internally configured to high-bandwidth. Table 9. Frequency Doubler FDF Operation 0 Frequency doubler off. PF divides clock signal from VCXO-PLL or input (in bypass). 1 Frequency doubler on (2). Signal from VCXO-PLL or input (in bypass) is doubled in frequency. PF divider has no effect. Table 10. Example PLL Configurations FemtoClock NG Divider Settings for VCO 2949.12MHz VCXO-Frequency (MHz) 153.6 122.88 30.72 2457.6MHz FDF PF MF FDF PF MF – 5 96 – 1 16 x2 – 8 – 1 24 – 1 20 x2 – 12 x2 – 10 – 1 96 – 1 80 x2 – 48 x2 – 40 ©2017 Integrated Device Technology, Inc. 10 November 20, 2017 8V19N470 Datasheet Channel Frequency Divider The device supports four independent output channels A – D. The channels A – D have one configurable integer frequency divider Nx, xA – D that divides the VCO frequency to the desired output frequency with very low phase noise. The integer divider values can be selected from the range of 1 to 160 as shown in Table 11. Table 11. Integer Frequency Divider Settings Output Clock Frequency (MHz) for VCO (MHz) Channel Divider Nx[a] 2949.12 2457.6 1 2949.12 2457.6 2 1474.56 1228.8 3 983.04 819.2 4 737.28 614.4 5 589.82 491.52 6 491.52 409.6 8 368.64 307.2 10 294.912 245.76 12 245.76 204.8 16 184.32 153.6 18 163.84 136.533 20 147.456 122.88 24 122.88 102.4 30 98.304 81.92 32 92.16 76.8 36 81.92 68.266 40 73.728 61.44 48 61.44 51.2 50 58.9824 49.152 60 49.152 40.96 64 46.08 38.4 72 40.96 34.133 80 36.864 30.72 96 30.72 25.6 100 29.4912 24.576 120 24.576 20.48 128 23.04 19.2 160 18.432 15.36 [a] xA – D. ©2017 Integrated Device Technology, Inc. 11 November 20, 2017 8V19N470 Datasheet Redundant Inputs The two inputs are compatible with LVDS, LVPECL signal formats and also support single-ended signals (LVCMOS, see Applications Information for applicable input interface circuits). Monitoring The two clock inputs of the device are individually and permanently monitored for activity. Inactivity is defined by a static input signal. Input frequency changes are not monitored. Loss of Input Signal (LOS) In operation, a clock input is declared invalid (LOS) with the corresponding ST_CLK_n and LS_CLK_n indicator bits set after a specified number of consecutive clock edges. If differential input signals are applied, the input will also detect an LOS condition in case of a zero differential input voltage. The device supports LOS detect circuits, one for each input. The signal detect circuits compare the signals at the CLK_0 and CLK_1 inputs to internally frequency-divided signals from the VCXO-PLL (see Figure 3 for details). For each loss detect circuit, the loss-of-signal fault condition is declared upon three or more missing clock input edges. Both loss detect circuits operate independent of each other, allowing correct LOS signaling for two different input frequencies. LOS requires configuration of the N_MON_n[14:0] frequency dividers to individually match the input frequencies CLK_n to the VCXO frequency: fVCXO  N_MON_n  fCLK_n. For instance, if one of the input frequencies is 15.36MHz and a 30.72MHz VCXO is used, set N_MON_n 2 (see Table 31 for configuration details). Then, LOS is declared after three consecutive missing clock edges. LOS is signaled through the ST_CLK_n (momentary) and LS_CLK_n (sticky, resettable) status bits and can reported as an interrupt signal on the nINT output. The LOS circuit requires the jitter attenuation mode of device (BYPV 0). LOS does not detect frequency errors. Figure 3. LOS Detect Circuit fCLK_0 fCLK_1 CLK_0 nCLK_0 CLK_1 nCLK_1 ÷PV Input Select ÷N_MON_0[14:0] LOS Detector 0 ST_CLK_0, LS_CLK_0 ÷N_MON_1[14:0] LOS Detector 1 ST_CLK_1, LS_CLK_1 fVCXO VCXO Input Re-Validation A clock input is declared valid and the corresponding ST_CLK_n bit is reset after the clock input signal returns for an user-configurable number of consecutive input periods. This re-validation of the selected input clock is controlled by the CNTV setting (verification pulse counter). ©2017 Integrated Device Technology, Inc. 12 November 20, 2017 8V19N470 Datasheet Input Clock Selection The device supports external, pin-controlled clock selection and internal, register controlled clock selection. The EXT_SEL[1:0] pins control the input selection mode. In internal mode, automatic clock selection and manual register-controlled clock selection is available. Definitions for Input Clock Selection Manual input selection The CLK_n input is selected by the user by pin (external) or register control (internal). Automatic input selection The CLK_n input is selected by an internal state machine, based on internal priorities, as response to the clock input status. External Input Selection Controls The EXT_SEL[1:0] pins select CLK_0 or CLK_1 as the reference clock, enable switch control bits nMA[1:0], or set the device to holdover mode. Table 12. Input Selection Mode Reference Selection EXT_SEL[1:0][a] EN_nMA nMA[1:0] Mode Selected Input 00 (default) X X External, Manual CLK_0 01 X X 0 x External-Controlled Holdover – No Expiration Counter — 1 00 Internal-Controlled, Manual Holdover by INT_SEL 1 01 Automatic by state machine 1 10 Short-term Holdover by INT_SEL 1 11 Automatic with Holdover by state machine X X External-Controlled Holdover – No Expiration Counter (no expiration counter) — 10 11 CLK_1 [a] Pin controlled input selection if EXT_SEL[1]  0; register controlled selection if EXT_SEL[1]  1. ©2017 Integrated Device Technology, Inc. 13 November 20, 2017 8V19N470 Datasheet Internal Input Selection Controls Definitions for Automatic Input Selection Primary clock: The CLK_n input selected by the selection logic. Secondary clock: The CLK_n input not selected by the selection logic. PLL reference clock: The CLK_n input selected as the PLL reference signal by the selection logic. In automatic switching mode, the selection can be overwritten by a state machine. Table 13. Internal Clock Selection Settings: Valid when EXT_SEL[1:0]  10 and EN_nMA  1 ST_REF Description ST_SEL Name nST_HOLD Flags ST_CLKn nMA0 nMA1 Mode Application Input selection follows user-configuration of the INT_SEL register bit. Input selection is never changed by the internal state machine. 0 0 Manual Holdover (default) LOS on the primary reference clock: Active reference stays selected and the PLLs may stall. Device will not go into holdover. Manual change of the reference clock: The device will go into holdover and the hold-off down-counter (CNTH) starts. The device initiates a clock switch after expiration of the hold-off counter. Duration of holdover is set by CNTH × CNTR / fVCXO. Holdover is terminated even if the secondary clock input is bad (LOS). See Internal-Controlled, Manual Holdover 1 LOS status 0[b] selected input selected input[c] 0[a] LOS status of selected input selection control with holdover Input selection follows LOS status. A failing input clock will cause an LOS event for that clock input. If the selected clock has an LOS event, the device will immediately initiate a clock fail-over switch, if the other clock is valid. 0 1 Automatic LOS on the primary reference clock: The device will switch to the secondary clock without holdover. Input selection is determined by a state machine and may differ from the user’s clock selection. No valid clock scenario: If no valid input clocks exist, the device will not attempt to switch and will not enter the holdover state. The PLL is not locked. Re-validation of an input clock will result in the PLL to attempt to lock on that input clock. See Revertive Switching. Both primary and secondary clock must have the same frequency for the PLL to resume lock upon transition to the secondary clock: set PV0  PV1. Manual change of the reference clock: The device will switch to the newly selected clock without holdover. If the newly selected clock is not valid, the PLL may stall. ©2017 Integrated Device Technology, Inc. 14 1 LOS status 1 selected input determined by state machine actual LOS status of selected input determined by state machine selected input actual LOS status of selected input multiple inputs with qualified clock signals November 20, 2017 8V19N470 Datasheet Table 13. Internal Clock Selection Settings: Valid when EXT_SEL[1:0]  10 and EN_nMA  1 (Cont.) ST_REF Description ST_SEL Name nST_HOLD Flags ST_CLKn nMA0 nMA1 Mode Application Input selection follows user-configuration of INT_SEL register bit. Selection is never changed by the internal state machine. 1 0 Short-term Holdover LOS on the primary reference clock: A failing reference clock will cause an LOS event. If the selected reference fails, the device will enter holdover immediately. Re-validation of the selected input clock is controlled by the CNTV setting. A successful re-validation will result in the PLL to re-lock on that input clock. 0 0 selected input LOS status Manual change of the reference clock: The device will switch to the newly selected clock without holdover. If the newly selected clock is not valid, the PLL may stall. LOS status of selected input 1 use if a single reference is occasionally interrupted Input selection follows LOS status. A failing input clock will cause an LOS event for that clock input. If the selected clock has an LOS event, the device will go into holdover and switches input clocks after the hold-off counter expires. LOS on the primary reference clock or manual change of the reference clock: 1 1 Automatic with Holdover the device will go into holdover and the hold-off down-counter (CNTH) starts. The device initiates a clock fail-over switch to a valid secondary clock input after expiration of the hold-off counter. Duration of holdover is set by CNTH × CNTR / fVCXO. The holdover is terminated prior hold-off count-down if the primary clock revalidates or is terminated by a manual change of the reference clock. See Automatic with Holdover and Revertive Switching. 0 LOS status for holdover duration selected input determined by state machine actual LOS status of selected input multiple inputs Both primary and secondary clock must have the same frequency for the PLL to resume lock upon transition to the secondary clock: set PV0  PV1. No valid clock scenario: The device remains in holdover if the secondary input clock is invalid. [a] For the duration of an invalid input signal (LOS). [b] For the duration of holdover. [c] Delayed by holdover period. ©2017 Integrated Device Technology, Inc. 15 November 20, 2017 8V19N470 Datasheet Holdover In holdover state, the output frequency and phase is derived from an internal, digital value based on previous frequency and phase information. Holdover characteristics are defined in Table 54. External-Controlled Holdover – No Expiration Counter Applying the configuration EXT_SEL[1:0]  11 or (EXT_SEL[1:0]  10 and EN_nMA 0) sets the device in holdover. No clock input is selected. Leaving holdover requires a change from either of the two configurations above. Internal-Controlled, Manual Holdover Input switch control is manual by setting the configuration to EXT_SEL[1:0]  10, EN_nMA = 1, and nM/A[1:0] 00. The INT_SEL bit determines the selected reference clock input. If the selection is changed by the user, the device will enter holdover until the CNTH[7:0] counter expires. Then, the new reference is selected (input switch). Application for this mode is external selection control. ▪ ▪ ▪ ▪ ST_REF: status of selected reference clock ST_CLK_n will both reflect the status of the corresponding input ST_SEL: the new selection after holdover nST_HOLD  0 for the duration of holdover Automatic with Holdover Configuration: EXT_SEL[1:0]  10, EN_nMA = 1, and nM/A[1:0] 11. If an LOS event is detected on the active reference clock: ▪ Holdover begins immediately ▪ Corresponding ST_REF and LS_REF go low immediately ▪ Hold-off countdown begins immediately During this time, both input clocks continue to be monitored and their respective ST_CLK, LS_CLK flags are active. LOS events will be indicated on ST_CLK, LS_CLK when they occur. If the active reference clock resumes and is validated during the hold-off countdown: ▪ its ST_CLK status flag will return high and the LS_CLK is available to be cleared by an SPI write of 1 to that register bit. ▪ No transitions will occur of the active REF clock; ST_SEL does not change ▪ Revertive bit has no effect during this time (whether 0 or 1) When the hold-off countdown reaches zero: ▪ If the active reference has resumed and has been validated during the countdown, it will maintain being the active reference clock — ST_SEL does not change — ST_REF returns to 1 — LS_REF can be cleared by an SPI write of 1 to that register — Holdover turns off and the VCXO-PLL attempts to lock to the active reference clock ▪ If the active reference has not resumed, but the other clock input CLK_n is validated, then — ST_SEL changes to the new active reference — ST_REF returns to 1 — LS_REF can be cleared by an SPI write of 1 to that register — Holdover turns off ©2017 Integrated Device Technology, Inc. 16 November 20, 2017 8V19N470 Datasheet If there is no validated CLK: ▪ ST_SEL does not change ▪ ST_REF remains low ▪ LS_REF cannot be cleared by an SPI write of 1 to that register ▪ Holdover remains active Revertive capability returns if REVS 1. Hold-off Counter A configurable down-counter applicable to the Automatic with Holdover and Manual with Holdover selection modes. The purpose of this counter is a deferred, user-configurable input switch. The counter expires when a zero-transition occurs; this triggers a new reference clock selection. The counter is clocked by the frequency-divided VCXO-PLL signal. The CNTR setting determines the hold-off counter frequency divider and the CNTH setting the start value of the hold-off counter. For instance, set CNTR to a value of 131072 to achieve 937.5Hz (or a period of 1.066ms at fVCXO 122.88MHz): the 8-bit CNTH counter is clocked by 937.5Hz and the user-configurable hold-off period range is 0ms (CNTR 0x00) to 272ms (CNTR 0xFF). After the counter expires, it reloads automatically from the CNTH SPI register. After the LOS status bit (LS_CLK_n) for the corresponding input CLK_n has been cleared by the user, the input is enabled for generating a new LOS event. The CNTR counter is only clocked if the device is configured in the clock selection modes Automatic with Holdover and the selected reference clock experiences an LOS event or in the Manual with Holdover mode with manual switching. Otherwise, the counter is automatically disabled (not clocked). Revertive Switching Revertive switching: is only applicable to the two automatic switch modes shown in Table 13. Revertive switching enabled: Re-validation of the primary clock will cause a new input selection to that clock (revertive switch). An input switch is only done if the re-validated input is the primary clock. Revertive switching disabled: Re-validation of a primary clock has no impact on the clock selection. Default setting is revertive switching disabled. VCXO-PLL Lock Detect (LOLV) The VCXO-PLL lock detect circuit uses the signal phase difference at the phase detector as loss-of-lock criteria. Loss-of-lock is reported if the actual phase difference is larger than a configurable phase detector window set by the LOCK_TH[14:0] configuration bits. A Loss-of-lock state is reported through the nST_LOLV and nLS_LOLV status bits as shown in Table 17. The VCXO-PLL lock detect function requires to set FVCV  0. FemtoClock NG Loss-of-Lock (LOLF) FemtoClock NG-PLL Loss-of-lock is signaled through the nST_LOLF (momentary) and nLS_LOLF (sticky, resettable) status bits and can reported as hardware signal on the LOCK_V output as well as an interrupt signal on the nINT output. ©2017 Integrated Device Technology, Inc. 17 November 20, 2017 8V19N470 Datasheet Differential Outputs Table 14. Output Features Output QCLK_y Style Amplitude[a] LVPECL 350mV – 850mV 4 steps Yes Yes LVDS 350mV  850mV 4 steps Yes Yes LVCMOS[c] 1.8V Yes Yes LVDS LVPECL QCLK_V Disable Power Down Termination 50 to VTT[b] 100 diff. 50 to VTT 100 diff. ― [a] Amplitudes are measured single-endedly. [b] For VTT (termination voltage) values (see Table 60). [c] LVCMOS style: nQCLK_V and QCLK_V are complementary. STYLE 1 Off X 100 differential or no termination 0 On 0 100 differential (LVDS) 1 Termination 50 to VTT[d] (LVPECL) State A[1:0] Output Power Enable PD[a] Table 15. Individual Clock Output Settings Amplitude (mV)[b] X Off X X 0 Disable[c] XX X 1 Enable 00 350 01 500 10 700 11 850 0 Disable XX X 1 Enable 00 350 01 500 10 700 11 850 [a] Power-down modes are available for the individual channels A – D and the outputs QCLK_y (A0 to D1). [b] Output amplitudes of 700mV and 850mV require a 3.3V output supply (VDDO_V). 350mV and 500mV output amplitudes support VDDO_V  2.5V and 1.8V. [c] Differential output is disabled in static low/high state. [d] For VTT (termination voltage) values (see Table 60). ©2017 Integrated Device Technology, Inc. 18 November 20, 2017 8V19N470 Datasheet Output Phase-Delay Output phase delay is supported in each channel. The selected VCO frequency sets the delay unit to 1/2  fVCO. Table 16. Delay Circuit Settings Delay Circuit Unit Steps Clock Phase CLK_x Range 512 1 --------------------2  f VCO fVCO 2949.12MHz: 169ps fVCO 2457.6MHz: 203ps 0 – 86.664ns 0  103.963ns Status Conditions and Interrupts The device has an interrupt output to signal changes in status conditions. Settings for status conditions may be accessed in the Status registers. The device has several conditions that can indicate faults and status changes in the operation of the device. These are shown in Table 17 and can be monitored directly in the status registers. Status bits (named: ST_status_condition) are read-only and reflect the momentary device status at the time of read-access. Several status bits are also copied into latched bit positions (named: LS_status_condition). The latched version is controlled by the corresponding fault and status conditions and remains set (“sticky”) until reset by the user by writing “1” to the status register bit. The reset of the status condition only has an effect if the corresponding fault condition is removed, otherwise, the status bit will set again. Setting a status bit on several latched registers can be programmed to generate an interrupt signal (nINT) via settings in the Interrupt Enable bits (named: IE_condition). A setting of “0” in any of these bits will mask the corresponding latched status bits from affecting the interrupt status pin. Setting all IE bits to 0 has the effect of disabling interrupts from the device. Table 17. Status Bit Functions Status Bit Function Status if Bit is: 1 0 Interrupt Enable Bit CLK 0 input status Active LOS IE_CLK_0 LS_CLK_1 CLK 1 input status Active LOS IE_CLK_1 nST_LOLV nLS_LOLV VCXO-PLL Loss-of-lock Locked Loss-of-lock IE_LOLV nST_LOLF nLS_LOLF FemtoClock NG PLL Loss-of-lock Locked Loss-of-lock IE_LOLF nST_HOLD nLS_HOLD Holdover Not in holdover Device in holdover IE_HOLD ST_VCOF — FemtoClock NG VCO calibration Not completed Completed — ST_SEL — Clock input selection ST_REF LS_REF PLL reference status Momentary Latched ST_CLK_0 LS_CLK_0 ST_CLK_1 Description 0  CLK_0 1  CLK_1 Valid reference[a] Reference lost — IE_REF [a] Manual and short-term holdover mode: 0 indicates if the selected reference is lost, 1 if not lost. Automatic mode: will transition to 0 while the input clock is lost and during input selection. Will transition to 1 once a new reference is selected. Automatic with holdover mode: 0 indicates the reference is lost and still in holdover. ©2017 Integrated Device Technology, Inc. 19 November 20, 2017 8V19N470 Datasheet Interrupts are cleared by resetting the appropriate bit(s) in the latched register after the underlying fault condition has been resolved. When all valid interrupt sources have been cleared in this manner, this will release the nINT output until the next unmasked fault. Table 18. Fault Indicator Outputs Status Bit (PLL) nLS_LOLV (VCXO-PLL) nLS_LOLF (FemtoClock NG) Status Reported on LOCK_V[a] Output[b] Status Reported on LOCK_F[a] Output[b] Locked Locked 1 1 Locked Not locked 1 0 Not locked Locked 0 1 Not locked Not locked 0 0 [a] Hardware interrupts on nINT require IE_LOLV 1, IE_LOLF 1 (interrupt enable). [b] SELSV[2:1] bits control the logic level (1.8V/ 3.3V) of LOCK_V, LOCK_F and nINT outputs. Device Startup, Reset and Synchronization At startup, an internal POR (power-on reset) resets the device and sets all register bits to their default value. The device forces the VCXO control voltage at the LFV pin to half of the power supply voltage to center the VCXO-frequency. In the default configuration the QCLK_y outputs are disabled at startup. Recommended configuration sequence (in order): ▪ (Optional) set the value of the CPOL register bit to define the SPI read mode supported by the SPI controller. Set the LSBIT_1ST, SDO_ACT, ACS_ON and the corresponding mirrored bits in register 0x00 as appropriate for SPI read access to the device. ▪ Configure all PLL and output divider and delay circuits as well as other device configurations, such as the charge pump currents. Set the TRANSFER bit (register 0x0F, bit D0) for PLL registers wider than then 8 bit (see double buffered registers). ▪ Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will self-clear. ▪ Set both the RELOCK bit and PB_CAL bit. This step should not be combined with the previous step (setting INIT_CLK) in a multi SPI-byte register access. Both bits will self-clear. ▪ Clear the FVCV bit to release the VCXO control voltage and VCXO-PLL will attempt to lock to the input clock signal starting from its center frequency. ▪ Clear the status flags. ▪ (Optional and recommended) Optimize the internal precision bias current calibration process: — Read the contents of the STAT_PB[5:1] register (precision bias current in register 0x4E, ignore STAT_PB[0]) — With a single-byte write access to register 0x63, apply the following bit pattern to OVERRIDE_CURR[5:0] and OVERRIDE_CAL: – OVERRIDE_CURR[5:1] (bit field location D[6:2] of register 0x63  STAT_PB[5:1] as read from above step OVERRIDE_CURR[0] (bit field location D[1] of register 0x63)  0 OVERRIDE_CAL (bit field location D[0] of register 0x63)  1 ▪ Enable the outputs by accessing the output-enable registers in a separate SPI write access. ©2017 Integrated Device Technology, Inc. 20 November 20, 2017 8V19N470 Datasheet Changing Frequency Dividers and Phase Delay Values Following procedure has to be applied for a change of a clock divider and phase delay value NA-D, and CLKA-D: ▪ (Optional) set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI read accesses. ▪ (Optional) disable the outputs whose frequency divider or delay value is changed. ▪ Configure the NA-D dividers and the delay circuits CLKA-D to the desired new values. ▪ Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit will self-clear. During this initialization step, all QCLK_y outputs are reset to the logic low state. ▪ Set the RELOCK bit. This step should not be combined with the setting INIT_CLK in a multi SPI-byte register access. Bit will self-clear. ▪ (Optional) enable the outputs whose frequency divider was changed. SPI Interface The device has a selectable 3/4-wire serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any of the internal registers for device programming or read back. The SPI interface consists of the SCLK (clock), SDIO (serial data input and output in 3-wire mode, input in 4-wire mode), SDO (output in 4-wire mode), nCS (chip select) and nRESET (SPI reset) pins. A data transfer contains 16 bit (direction  15 bit address) and any integer multiple of 8 bits (input or output data) and is always initiated by the SPI master on the bus. Internal register data is organized in SPI bytes of 8 bit each. This device supports most-significant bit (MSBit) and least-significant (LSBit) first transfer bit positions, single byte and multi-byte data streaming modes with address auto-increment and auto-decrement. For SPI logic diagrams, see Figure 4 to Figure 5.For the SPI timing diagram, see Figure 8. Chip Select. If the nCS pin is at logic high, the SDIO/SDO data output pin is in high-impedance state and the SPI interface of the device is disabled. 3/4-Wire Mode. In 3-wire mode, the SDIO pin acts as bidirectional input/output and the SDO pin is in high-impedance state. In 4-wire mode, the SDIO pin is the SPI input and the SDO pin is the SPI output. The SPI interface mode is defined by the SDO_ACT bit in the SPI device configuration register. Active Clock Edge. In a write operation, data on SDIO will be clocked in on the rising edge of SCLK. In a read operation, data on SDIO/SDO will be clocked out on the falling or rising edge of SCLK depending on the CPOL setting (CPOL 0: output data changes on the falling edge, CPOL 1: output data changes on the rising edge). Reset. By asserting the nRESET pin, the SPI engine is reset and all internal device registers reset to their default values. The SRESET bit in the device SPI configuration register resets the registers 0x02 to 0x63 to their default values. The registers 0x00 and 0x01 are not reset by asserting SRESET. Logic levels. The SPI pins SDIO and SDO have selectable 1.8V/3.3V logic levels. The SELSV0 register bit controls the logic level. SELSV0 0: 1.8V logic, and SELSV0 1: 3.3V logic. Least Significant Bit Position. The device supports LSBit (least significant bit first) and MSBit (most significant bit first) transfers between master and slave. If MSBit first is set, data is transferred in this order: transfer direction bit first, then the register address bits A14 to A0, then the data bits of the first data byte D7 to D0. If LSBit first is set, the order is: address bits A0 to A14 first, then the transfer direction bit, then the data bits of the first data byte D0 to D7. Starting a Data Transfer requires the nCS pin to set and hold at logic low level during the entire transfer. Setting nCS  0 will enable the SPI interface with the SDIO pin in data input mode. The master must initiate the first 16-bit transfer containing the transfer direction bit and the SPI register address to access. Transfer Direction Bit: Defines if the master reads data from the device or writes data to the device. R/nW (1 Read,0 Write). If MSB-first is set, the transfer bit is presented by the master as the first bit in the transfer. If LSB-first is set, the transfer bit is the 16th bit presented by the master. MSB-first is the default upon power-up: the initial data transfer must be in MSB-first order. Address: The device supports a 15 bit address A[14:0] pointing to an internal register in the address space 0 to 0x7FFF. This device implements registers at the addresses 0x00-0x63. ©2017 Integrated Device Technology, Inc. 21 November 20, 2017 8V19N470 Datasheet Read operation from an internal register: a read operation starts with a 16 bit transfer from the master to the slave: the SDIO signal is clocked on the rising edge of SCLK. The transfer direction bit R/nW must be to 1 to indicate a read transfer, the other 15 bits is the address A[14:0] to read from. After the first 16 bits are clocked into the SDIO pin, the SDIO I/O changes to output if 4-wire mode is set by SDO_ACT 0 (in 3-wire mode set by SDO_ACT 1, the pin SDO is the output). The register content addressed by A[14:0] are the presented at the SPI output at the next 8 SCLK falling (CPOL 1) or next eight SCLK rising (CPOL 1) clock cycles and transfer these to the master. Transfers must be completed with de-asserting nCS after any multiple eight of SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior is undefined. Read operation transfers multiple bytes in streaming mode with the 15 bit register address auto-increment or decrement. Single byte transfers are supported in streaming mode by de-asserting nCS after the first payload byte. Write operation to a device register: During a write transfer, an SPI master transfers one or more bytes of data into the internal registers of the device. A write transfer starts by asserting the nCS to pin low logic level. The transfer direction bit R/nW must be set to 0 to indicate a write transfer, the other 15 bits are the address A[14:0] to write to. Bits D[7:0] contain 8 bits of transfer data, which is written into the register specified by A[14:0] at the end of each 8-bit write transfer. Multiple, subsequent register transfers from the master to the slave are supported in streaming mode by holding nCS asserted at logic low level during write transfers. Transfers must be completed with de-asserting nCS after any multiple of eight SCLK cycles. If nCS is de-asserted at any other number of SCLKs, the SPI behavior is undefined. The 15 bit register address will auto-increment or decrement (streaming mode). Single byte transfers are supported in streaming mode by de-asserting nCS after the first payload byte. Register Streaming Mode. Streaming mode is the transfer of multiple data bytes back to back. The address A[14:0] specifies the register location of the first byte to transfer, for the following transfer, the address is automatically incremented or decremented. nCS must stay at logic low level and SDIO/SDO will present multiple registers, e.g. (A), (A -1), (A -2), etc. with each eight SCLK cycles. During SPI Read operations, the user may continue to hold nCS low and provide further bytes. The ASC_ON register defines if registers auto-increment (A), (A 1), (A 2), etc. or auto-decrement (A), (A -1), (A -2), etc. Address wrap-around: Applicable to streaming mode: The address will wrap-around the address range of 0x00 – 0x63. The SPI engine auto-increments to address 0x00 after 0x63 and auto-decrements to address 0x63 after 0x00. End of transfer: After nCS is de-asserted to logic 1, the SPI bus is available to transfers to other slaves on the SPI bus. The READ diagrams (Figure 5, Figure 6, and Figure 7) and WRITE diagram (Figure 4) display the transfer of a single byte of data from and into registers. Mirrored Register Bits. The register bits D7 – D4 in the device SPI configuration register (0x00) are mirrored with the bits D3 – D0 in the same register for a LSBit/MSBit First independent access. Setting a mirrored bit to the “1” state requires to set both bit and its to 1. Double Buffered Registers. PLL divider registers that are wider than 8 bit are double buffered for synchronous access. Synchronous configuration of these registers requires to write the multiple-byte setting into the SPI registers first and then transfer the content into the device registers by asserting the TRANSFER bit. The configuration only takes effect after the TRANSFER bit is asserted. Configuration data can be read-back from SPI and device registers as specified by the RB_MODE bit. Internal Debug Registers. Registers in the address range0x4F, 0x5C – 0x5D and 0x64 to 0xFF should not be used. Do not write into any registers in the 0x4F, 0x5C – 0x5D and 0x64 to 0xFF address range. Default SPI Modes: After power-up and reset by the nRESET pin, the SPI interface is in 3-wire mode with SDO in high-impedance, MSB-first mode, streaming mode on with address auto-decrement. In read transfer mode, data is output on SDIO on the falling SCLK edge. ©2017 Integrated Device Technology, Inc. 22 November 20, 2017 8V19N470 Datasheet Figure 4. Logic Diagram: Single Byte WRITE Data into Device Registers in SPI 3 or 4-wire Mode for LSB and MSB-First SCLK 0 1 2 3 4 5 6 7 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 D0 D1 D2 D3 D4 D5 D6 D7 nCS SDIO (LSB First) Hi-Imp A9 A10 A11 A12 A13 A14 Input nW=0, 15-bit Address SDIO (MSB First) Hi-Imp 0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 Hi-Imp Input Register Data (Address) A3 A2 A1 A0 D7 Input nW=0, 15-bit Address D6 D5 D4 D3 D2 D1 D0 Hi-Imp Input Register Data (Address) Figure 5. Logic Diagram: Single Byte READ Data from the Device Registers in SPI 3-wire Mode for LSB and MSB-First and CPOL 0, 1 SCLK 0 1 2 3 4 5 6 7 8 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A14 A13 A12 A11 A10 A9 A8 A7 A6 A1 A6 A7 A8 A9 A10 A11 A12 A13 A14 A14 A13 A12 A11 A10 A9 A8 A7 A6 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 1 D0 D1 D2 D3 D4 D5 D6 D7 Hi-Imp A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Imp nCS SDIO, CPOL=0, LSB First Hi-Imp A0 SDIO, CPOL=0, MSB First Hi-Imp 1 SDIO, CPOL=1, LSB First Hi-Imp A0 SDIO, CPOL=1, MSB First Hi-Imp 1 A2 A3 A4 A5 A5 A4 A5 A3 A4 A2 A3 A1 A2 A1 1 D0 D1 D2 D3 D4 D5 D6 D7 Hi-Imp A0 D7 D6 D5 D4 D3 D2 D1 D0 Hi-Imp Output Register Data (Address) Input R=1, 15-bit Address Figure 6. Logic Diagram: Single Byte READ Data from the Device Registers in SPI 4-wire Mode for LSB-First and CPOL 0, 1 SCLK 0 1 2 3 4 5 6 7 8 A0 A1 A2 A3 A4 A5 A6 A7 A8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 D0 D1 D2 D3 D4 D5 D6 D7 nCS SDIO, LSB First Hi-Imp A9 A10 A11 A12 A13 A14 1 Input R=1, 15-bit Address SDO, CPOL=0 SDO, CPOL=1 Hi-Imp Hi-Imp D0 D1 D2 D3 D4 D5 D6 D7 Hi-Imp Hi-Imp Output Register Data (Address) ©2017 Integrated Device Technology, Inc. 23 November 20, 2017 8V19N470 Datasheet Figure 7. Logic Diagram: Single Byte READ Data from the Device Registers in SPI 4-wire Mode for MSB-First and CPOL 0, 1 SCLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A8 A7 A6 A5 A4 A3 A2 A1 A0 16 17 18 19 20 21 22 23 D7 D6 D5 D4 D3 D2 D1 D0 nCS SDIO, MSB First Hi-Imp 1 A14 A13 A12 A11 A10 A9 Input R=1, 15-bit Address SDO, CPOL=0 Hi-Imp SDO, CPOL=1 D7 Hi-Imp D6 D5 D4 D3 D2 D1 D0 Hi-Imp Hi-Imp Output Register Data (Address) Table 19. SPI Read / Write Cycle Timing Parameters Symbol Parameter Test Condition Minimum Maximum Unit 20 MHz fSCLK SCLK Frequency TSCLK SCLK Clock Period 50 ns tS1 Setup Time, nCS (falling) to SCLK (rising) 10 ns tS2 Setup Time, SDIO (input) to SCLK (rising) 8 ns tH1 Hold Time, SCLK (rising) to nCS (rising) 30 ns tH2 Hold Time, SCLK (rising) to SDIO (input) 8 ns tH3 Hold Time, SCLK (falling) to nCS (rising) 8 ns tPDF Propagation Delay, SCLK (falling) to SDIO (output in 3-wire mode) or SDO (in 4-wire mode) CPOL 0 tPDR Propagation Delay, SCLK (rising) to SDIO (output in 3-wire mode) or SDO (in 4-wire mode) CPOL 1 tWRES nRESET Pulse Width ©2017 Integrated Device Technology, Inc. 100 24 10 ns 10 ns ns November 20, 2017 8V19N470 Datasheet Figure 8. SPI Timing Diagram nCS tH1 tS1 tH3 SCLK tS2 tH2 TSCLK SDIO tPDF SDO/SDIO CPOL=0 tPDR SDO/SDIO CPOL=1 High Impedance Configurable Logic Levels for LVCMOS Control Outputs Table 20. SDO, SDIO Logic Levels SELSV0 SDO, SDIO[a] Output Logic Levels 0 (default) 1.8V 1 3.3V [a] SDIO as input: set SELSV0  0 for 1.8V SPI logic levels and SELSV0 0 for 3.3V SPI logic levels. The SDIO input threshold is ~0.9V regardless of SELSV0. Table 21. nINT, LOCK_V Logic Levels SELSV1 nINT, LOCK_V Output Logic Levels 0 (default) 1.8V 1 3.3V Table 22. LOCK_F Logic Levels SELSV2 LOCK_F Output Logic Levels 0 (default) 1.8V 1 3.3V ©2017 Integrated Device Technology, Inc. 25 November 20, 2017 8V19N470 Datasheet Register Descriptions List of Registers Table 23. Configuration Registers Register Address Register Description 0x00–0x02 Device Configuration: SPI 0x03 Device Type 0x04–0x05 Device ID 0x06 Device Version 0x070x0B Reserved 0x0C0x0D Vendor ID 0x0E Reserved 0x0F Device Configuration: SPI 0x100x11 PLL Frequency Divider: PV0 0x120x13 PLL Frequency Divider: PV1 0x140x15 PLL Frequency Divider: MV 0x160x17 LOCK_TH 0x18 PLL Control: BYPV, VCO_SEL 0x19 PLL Frequency Divider: PF, FDF 0x1A0x1B PLL Frequency Divider: MF[8:0] 0x1C0x1E PLL Control 0x1F I/O Voltage Select 0x200x23 Input Selection 0x240x26 Channel A 0x27 Reserved 0x280x2A Output States QCLK_A0-A2 0x2B Reserved 0x2C0x2E Channel B 0x2F Reserved 0x300x32 Output States QCLK_B0-B2 0x33 Reserved 0x340x36 Channel C 0x37 Reserved 0x380x39 Output States QCLK_C0-C1 0x3A0x3B Reserved 0x3C-0x3E Channel D ©2017 Integrated Device Technology, Inc. 26 November 20, 2017 8V19N470 Datasheet Table 23. Configuration Registers (Cont.) Register Address Register Description 0x3F Reserved 0x400x41 Output States QCLK_D0-D1 0x420x43 Reserved 0x440x45 N_MON_0 0x460x47 N_MON_1 0x480x4A Reserved 0x4B Output States QCLK_V 0x4C Interrupt Enable 0x4D Reserved 0x4E Debug Control Status 0x4F Reserved 0x50 Status (Latched) 0x51 Status (Momentary) 0x52 Reserved 0x53 Status (Momentary) 0x54 Reserved 0x550x57 General Control 0x58 Channel Enable AD and QCLK_V 0x590x5B Reserved 0x5C0x5E Reserved 0x5F0x60 Reserved 0x610x62 Reserved 0x63 Precision Bias Control 0x640xFF Reserved ©2017 Integrated Device Technology, Inc. 27 November 20, 2017 8V19N470 Datasheet Register Descriptions This section contains all addressable registers, sorted by function, followed for a detailed description of each bit field for each register. Several functional blocks with multiple instances in this device have individual registers controlling their settings, but since the registers have an identical format and bit meaning, they are described only once, with an additional table to indicate their addresses and default values. All writable register fields will come up with the default values as indicated in the factory Default column. Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of the conditions they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are Reserved. Reserved bit fields may be used for internal debug test and debug functions. Device Configuration Registers Table 24. Device Configuration Register Bit Field Locations Bit Field Location Register Address 0x00 0x01 0x02 D7 D6 D5 D4 D3 D2 D1 D0 SRESET LSBIT_1ST ACS_ON SDO_ACT STR_OFF Reserved RB_MODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x03 DEV_TYPE[7:0] 0x04 DEV_ID[7:0] 0x05 DEV_ID[15:8] 0x06 DEV_VER[7:0] 0x0C VENDOR_ID[7:0] 0x0D 0x0F 0x1F PWR_DN[1:0] VENDOR_ID[15:8] Reserved Reserved Reserved Reserved Reserved Reserved Reserved TRANSFER Reserved Reserved Reserved Reserved Reserved SELSV2 SELSV1 SELSV0 ©2017 Integrated Device Technology, Inc. 28 November 20, 2017 8V19N470 Datasheet Table 25. Device Configuration Register Descriptions Register Description Bit Field Name Field Type Default (Binary) SRESET R/W 0 Auto-Clear Value: not reset R/W 0 LSBIT_1ST Value: MSB first ASC_ON R/W 0 Value: off, addresses auto-decrement SDO_ACT R/W 0 Value: SPI-3-wire mode ©2017 Integrated Device Technology, Inc. Description Soft Reset: 0  Normal operation. 1  Register reset. The device loads the default values into the registers 0x020xFF. The content of the register addresses 0x00 and 0x01 and the SPI engine are not reset. SRESET bit D7 is mirrored with in bit position D0. Register reset requires to set both SRESET and bits. Least Significant Bit Position: Defines the bit transmitted first in SPI transfers between slave and master. 0  The most significant bit (D7) first 1  The least significant bit (D0) first LSBIT_1ST bit D6 is mirrored with in bit position D1. Changing LSBIT_1ST to most significant bit requires to set both LSBIT_1ST and bits. Address Ascend on: 0  Address ascend is off (addresses auto-decrement in streaming SPI mode) 1  Address ascend is on (addresses auto-increment in streaming SPI mode) The ASC_ON bit specifies whether addresses are incremented or decremented in streaming SPI transfers. ASC_ON bit D5 is mirrored with in bit position D2. Changing ASC_ON to “ON” requires to set both ASC_ON and bits. SPI 3/4 Wire Mode: Selects the unidirectional or bidirectional data transfer mode for the SDIO pin. 0  SPI 3-wire mode: – SDIO is the SPI bidirectional data I/O pin – SDO pin is not used and is in high-impedance 1  SPI 4-wire mode – SDIO is the SPI data input pin – SDO is the SPI data output pin SDO_ACT bit D4 is mirrored with in bit position D3. Changing SDO_ACT to SPI 4-wire mode requires to set both SDO_ACT and bits. 29 November 20, 2017 8V19N470 Datasheet Table 25. Device Configuration Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) STR_OFF R/W 0 Value: SPI streaming mode enabled RB_MODE R/W 0 Value: read from device registers Description SPI Streaming Mode (not implemented): 0  SPI streaming mode enabled 1  SPI single byte transfer mode In SPI streaming mode, the device transfers SPI data back to back while auto-decrementing (if ASC_ON  0) or auto-incrementing (if ASC_ON  1) the SPI register address after each byte access. The device continues to read or write SPI data as long as nCS remains asserted and the SPI streaming mode remains enabled. In SPI streaming mode, single byte data transfers are supported by setting nCS to logic high state after the byte has been transferred. In SPI single byte transfer mode, one byte of SPI data is transferred regardless of nCS being de-asserted after the transfer. If this bit is set and nCS remains asserted, the SPI state machine resets after the data byte is transferred as if nCS was de-asserted and awaits the next transfer. The device does not implement STR_OFF  1. For implemented SPI single byte transfers (see Figure 4 – Figure 7). Read Back Mode: The device implements double buffered registers for frequency divider registers wider than 8 bit (registers for PV0, PV1, MV, LOCK_TH, MF, N_MON_0, and N_MON1). There are SPI registers and device registers. This bit specifies whether a read operation accesses the SPI or the device registers. 0  Read operation from PV0, PV1, MF, LOCK_TH, N_MON_0, NMON_1 and MV device registers 1  Read operation from PV0, PV1, MF, LOCK_TH, N_MON_0, NMON_1 and MV SPI registers To transmit data from the SPI to device registers, see the TRANSFER bit. PWR_DN[1:0] R/W 00 Value: DEV_TYP[7:0] R only 0000 0110 Value: RF-PLL DEV_ID[15:0] R only 0x04: 0100 0010 0x05: 0000 0000 Power-down Mode: 00, 01, 10, 10  Normal operation. Setting this PWR_DN[1:0] has no effect. Device (Chip) Type: Reads 0x06 (RF-PLL) after power-up and reset. Device ID: Device is composed of registers 0x05 (high byte) and register 0x04 (low byte). Reads 0x0042 after power-up and reset. Value: 0x0042 DEV_VER[7:0] R only 0x04 Value: 4 ©2017 Integrated Device Technology, Inc. Device Version: 0x04. Reads 0x04 (Silicon revision D) after power-up and reset. 30 November 20, 2017 8V19N470 Datasheet Table 25. Device Configuration Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) VENDOR_ID R only 0x0C: 0010 0110 0x0D: 0000 0100 Description Vendor ID: 0x0426 (Integrated Device Technology, IDT). Reads 0x0426 (IDT) after power-up and reset. Value: 0x0426 TRANSFER R/W 0 Auto-clear Value: no transfer SPI Transfer: The device implements double buffered registers for frequency divider registers wider than 8-bit (registers for PV0, PV1, MF, LOCK_TH, N_MON_0, NMON_1 and MV). There are SPI registers and device registers. Setting this bit to 1 will copy the content of the PV0, PV1, MF, LOCK_TH, N_MON_0, NMON_1 and MV SPI registers synchronously and simultaneously into the device registers where the settings will affect the device operation. For reading from SPI vs. device registers, see the RB_MODE setting. 0  No transfer 1  The SPI registers are transferred into the device registers. SELSV2 R/W 0 Value: 1.8V Selects the voltage level of the LOCK_F output: SELSV2: 0  LOCK_F interface pin is 1.8V (default) 1  LOCK_F interface pin is 3.3V SELSV1 R/W 1 Value: 3.3V Selects the voltage level of the nINT and LOCK_V outputs: SELSV1: 0  nINT and LOCK_V interface pins are 1.8V 1  nINT and LOCK_V interface pins are 3.3V (default) SELSV0 R/W 0 Value: 1.8V Selects the voltage level of the SPI interface (SDIO and SDO pins): SELSV0: 0  SPI interface pins (SDIO and SDO) are 1.8V (default) 1  SPI interface pins (SDIO and SDO) are 3.3V ©2017 Integrated Device Technology, Inc. 31 November 20, 2017 8V19N470 Datasheet PLL Frequency Divider Registers Table 26. PLL Frequency Divider Register Bit Field Locations Bit Field Location Register Address D7 D6 D5 D4 0x10 0x11 Reserved 0x19 Reserved Reserved Reserved MF8 PV1[14:8] MV[7:0] Reserved MV[14:8] LOCK_TH[7:0] Reserved FDF LOCK_TH[14:8] Reserved PF[5:0] 0x1A 0x1B D0 PV1[7:0] 0x16 0x17 D1 PV0[14:8] 0x14 0x15 D2 PV0[7:0] 0x12 0x13 D3 MF[7:0] Reserved Reserved Reserved Reserved Reserved Table 27. PLL Frequency Divider Register Descriptions Register Description Bit Field Name Field Type Default (Binary) Description PV0[14:0] R/W 000 0000 0000 1000 VCXO-PLL Input Frequency Pre-Divider Register 0: The value of the frequency divider PV (binary coding) if CLK_0 is the selected input clock. Value:8 ©2017 Integrated Device Technology, Inc. Range: 1 to 32767. PV0[14:0] is located in double-buffered registers (see the RB_MODE and TRANSFER bit settings). PV0 is loaded into the PV divider of the VCXO-PLL when CLK_0 is the selected clock input. 32 November 20, 2017 8V19N470 Datasheet Table 27. PLL Frequency Divider Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) PV1[14:0] R/W 000 0000 0000 1000 Value:8 MV[14:0] R/W 000 0000 0000 1000 Value:8 LOCK_TH[14:0] R/W 000 0000 0000 0011 Value: 3 Description VCXO-PLL Input Frequency Pre-Divider Register 1: The value of the frequency divider PV (binary coding) if CLK_1 is the selected input clock. Range: 1 to 32767. PV1[14:0] is located in double-buffered registers (see the RB_MODE and TRANSFER bit settings). PV1 is loaded into the PV divider of the VCXO-PLL when CLK_1 is the selected clock input. VCXO-PLL Feedback-Divider: The value of the frequency divider MV (binary coding). Range: 1 to 32767. MV[14:0] is located in double-buffered registers (see the RB_MODE and TRANSFER bit settings). PLL Lock Detect Phase Window Threshold: The device reports VCXO-PLL lock when the phase difference between the internal signals fREF and fVCXO_REF are lower than or equal to the phase difference set by LOCK_TH[14:0] for more than 1000 fVCXO_DIV clock cycles. Requires MV ≥ 4. Set LOCK_TH[14:0] < MV. (fREF  fCLK PV is the internal output of the PV divider, fVCXO_DIV  fVCXO MV is the internal output of the MV divider.) LOCK_TH[14:0] is located in double-buffered registers (see the RB_MODE and TRANSFER bit settings). PF[5:0] R/W 00 0001 Value: 1 FDF R/W 1 Value: fVCXO  2 MF[8:0] R/W 0 0011 0000 Value: 48 ©2017 Integrated Device Technology, Inc. FemtoClock NG Pre-Divider: The value of the frequency divider (binary coding). Range: 1 to 63. 00 0000: PF is bypassed The input frequency of the FemtoClock NG PLL (2nd stage) is: 0  the output signal of the BYPV multiplexer, divided by the PF divider. 1  the output signal of the BYPV multiplexer, doubled in frequency. Use this setting to improve phase nose. The PF divider has no effect if FDF 1. FemtoClock NG Pre-Divider: The value of the frequency divider (binary coding). Range: 8 to 511. MF is located in double-buffered registers (see the RB_MODE and TRANSFER bits settings). 33 November 20, 2017 8V19N470 Datasheet PLL Control Registers Table 28. PLL Control Register Bit Field Locations Bit Field Location Register Address 0x18 0x1C 0x1D 0x1E D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved Reserved BYPV VCO_SEL POLV FVCV Reserved Reserved Reserved CPV[4:0] Reserved OSVEN OFFSET[4:0] Reserved Reserved CPF[4:0] Table 29. PLL Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) BYPV R/W 0 VCXO-PLL enabled VCO_SEL R/W 0 Value: fVCO 2949.12MHz POLV R/W 0 Value: Positive Polarity FVCV R/W 1 Value: LFV  VDD_V / 2 ©2017 Integrated Device Technology, Inc. Description VCXO-PLL Bypass: 0  VCXO-PLL is enabled. 1  VCXO-PLL is disabled and bypassed. VCO Select: 0  Selects VCO-0. fVCO 2949.12MHz. 1  Selects VCO-1. fVCO 2400-2500MHz. VCXO Polarity: 0  Positive polarity. Use for an external VCXO with a positive f(VC) characteristics. 1  Negative polarity. Use for an external VCXO with a negative f(VC) characteristics. VCXO-PLL Force VC Control Voltage: 0  Normal operation. 1  Forces the voltage at the LFV control pin (VCXO input) to VDD_V / 2. VCXO-PLL unlocks and the VCXO is forced to its mid-point frequency. FVCV 1 is the default setting at startup to center the VCXO frequency. FVCV should be cleared after startup to enable the PLL to lock to the reference frequency. 34 November 20, 2017 8V19N470 Datasheet Table 29. PLL Control Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) CPV[4:0] R/W 0 1111 Value: 0.8mA Description VCXO-PLL Charge-Pump Current: Controls the charge pump current ICPV of the VCXO-PLL. Charge pump current is the binary value of this register plus one multiplied by 50µA. ICPV  50µA  (CPV[4:0]  1). CPV[4:0]  00000 sets ICPV to the minimum current of 50µA. Maximum charge pump current is 1.6mA. Default setting is 0.8mA: ((15  1) × 50µA). OSVEN R/W 0 VCXO-PLL Offset Enable: 0  No offset. 1  Offset enabled. A static phase offset of OFFSET[4:0] is applied to the PFD of the VCXO-PLL. OFFSETV[4:0] R/W 0 0000 Value: 0 CPF[4:0] R/W 0 0110 Value: 1.4mA VCXO-PLL Static Phase Offset: Controls the static phase detector offset of the VCXO-PLL. Phase offset is the binary value of this register multiplied by 0.9 of the PFD input signal (OFFSET [4:0]  fPFD  400). Maximum offset is 31  0.927.9 Setting OFFSET to 0.0 eliminates the thermal noise of an offset current. If the VCXO-PLL input jitter period TJIT exceeds the average input period: set OFFSET to a value larger than fPFD  TJIT  400 to achieve a better charge pump linearity and lower in-band noise of the PLL. FemtoClock NG-PLL Charge-Pump Current: Controls the charge pump current ICPF of the FemtoClock NG PLL. Charge pump current is the binary value of this register plus one multiplied by 200µA. ICPF  200µA  (CPF[4:0]  1). CPF[4:0]  00000 sets ICPF to the minimum current of 200µA. Maximum charge pump current is 5.6mA. Default setting is 1.4mA: ((6 1)  200µA). ©2017 Integrated Device Technology, Inc. 35 November 20, 2017 8V19N470 Datasheet Input Selection Mode Registers Table 30. Input Selection Mode Register Bit Field Locations Bit Field Location Register Address 0x20 0x21 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved Reserved Reserved IN_BLOCK Reserved EN_nMA Reserved Reserved Reserved REVS Reserved INT_SEL 0x22 CNTH[7:0] 0x23 CNTR[1:0] Reserved Reserved 0x44 0x45 Reserved Reserved CNTV[1:0] N_MON_0[7:0] Reserved N_MON_0[14:8] 0x46 0x47 nM/A[1:0] N_MON_1[7:0] Reserved N_MON_1[14:8] Table 31. Input Selection Mode Register Descriptions Register Description Bit Field Name Field Type N_MON_0[14:0] R/W Default (Binary) 000_0000 0000_0001 Value: 1 Description Clock frequency divider for the CLK_0 input activity monitor. The clock activity monitor compares the device input frequency (fIN) on CLK_0 to the frequency of the VCXO divided by N_MON_0. For optimal operation of the activity monitor, the frequency fVCXO  N_MON_0 should match the input frequency at CLK_0. E.g. for fIN 122.88MHz at CLK_0 and fVCXO 122.88MHz, set N_MON_0 1. The value of the frequency N_MON_0[14:0] _1 divider is binary coded. Range: 1 to 32767. N_MON_0[14:0] is located in double-buffered registers (see the RB_MODE and TRANSFER bit settings). ©2017 Integrated Device Technology, Inc. 36 November 20, 2017 8V19N470 Datasheet Table 31. Input Selection Mode Register Descriptions (Cont.) Register Description Bit Field Name Field Type N_MON_1[14:0] R/W Default (Binary) 000_0000 0000_0001 Value: 1 Description Clock frequency divider for the CLK_1 input activity monitor: The clock activity monitor compares the device input frequency (fIN) on CLK_1 to the frequency of the VCXO divided by N_MON_1. For optimal operation of the activity monitor, the frequency fVCXO  N_MON_1 should match the input frequency at CLK_1. E.g. for fIN122.88MHz at CLK_1 and fVCXO122.88MHz, set N_MON_1 1. For fIN 30.72MHz at CLK_1 and fVCXO 122.88MHz, set N_MON_1  4. The value of the frequency N_MON_1[14:0] divider is binary coded. Range: 1 to 32767. N_MON_1[14:0] is located in double-buffered registers (see the RB_MODE and TRANSFER bit settings). IN_BLOCK R/W 0 Value: not blocked EN_nMA R/W 0 Inactive Input Clock Block: 0  Both input clock signals CLK_0 and CLK_1 are routed to the input clock multiplexer and to the activity detectors. 1  The input clock that is currently not active is gated off (blocked). The blocked input is not monitored for activity. For instance, if CLK_0 is selected as the current PLL reference clock, IN_BLOCK 1 causes the CLK_1 input to be turned off in order to reduce input signal interference. IN_BLOCK should only be used with manual input reference control. Enable Internal Input Switch Controls (only valid when EXT_SEL [1:0] = 10; all other configurations ignore this bit): 0  External-Controlled Holdover – No Expiration Counter. 1  nMA[1:0] control bits set the input selection. REVS R/W 0 Value: Disabled Revertive Switching: The revertive input switching setting is only applicable to the two automatic selection modes shown in Table 13. If nM/A[1:0]  X0, the REVS setting has no meaning. 0  Disabled: Re-validation of a primary clock has no impact on the clock selection. 1  Enabled: Re-validation of the primary clock will cause a new input selection to that clock. nM/A[1:0] R/W 00 Value: Manual Selection Reference Input Selection Mode (only valid when EXT_SEL [1:0] = 10, and EN_nMA = 1): In either of the manual selection modes (nM/A[1:0]  00 or 10), the VCXO-PLL reference input is selected by INT_SEL. In any of the automatic selection modes, the VCXO-PLL reference input is selected by an internal state machine according to the input LOS states and the INT_SEL bit. 00  Manual Holdover 01  Automatic selection (no holdover) 10  Short-term holdover. 11  Automatic selection with holdover ©2017 Integrated Device Technology, Inc. 37 November 20, 2017 8V19N470 Datasheet Table 31. Input Selection Mode Register Descriptions (Cont.) Register Description Bit Field Name Field Type Default (Binary) INT_SEL R/W 0 Value: CLK_0 selected/ primary clock Description VCXO-PLL Input Reference Selection. INT_SEL 0 1 Internal and manual clock selection modes Automatic modes CLK_0  primary clock CLK_1  secondary clock CLK_0 is reference input CLK_1 is reference input If EXT_SEL[1:0] = 00 or 01: INT_SEL has no meaning. CNTH[7:0] R/W 1000 0000 Value: 136ms CNTR[1:0] R/W 10 Short-term holdover: Hold-off counter period. The device initiates a clock fail-over switch upon counter expiration (zero transition). The counters start to counts backwards after an LOS event is detected. The hold-off counter period is determined by the binary number of VCXO-PLL output pulses divided by CNTR[1:0]. With a VCXO frequency of 122.88MHz and CNTR[1:0] 10, the counter has a period of (1.066ms × binary setting). After each zero-transition, the counter automatically re-loads to the setting in this register. The default setting is 136ms (VCXO 122.88MHz: 1/122.88MHz  217  128). Short-term Holdover Reference Divider. CNTR[1:0] Value: 217 CNTV[1:0] R/W 10 Value: 32 CNTH frequency (period; range) 122.88MHz VCXO 38.4MHz VCXO 00  fVCXO  215 – 1171Hz (0.853ms; 0 – 2 17.6ms) 01  fVCXO  216 1875Hz (0.533ms; 0136ms) 10  fVCXO  217 937.5Hz (1.066ms; 0272ms) Revalidation Counter: Controls the number of required consecutive, valid input reference pulses for clock re-validation on CLK_n in number of input periods. At an LOS event, the re-validation counter loads this setting from the register and counts down by one with every valid, consecutive input signal period. Missing input edges (for one input period) will cause this counter to re-load its setting. An input is re-validated when the counter transitions to zero and the corresponding LOS flag is reset. 00  2 (shortest possible) 01  16 10  32 11  64 ©2017 Integrated Device Technology, Inc. 38 November 20, 2017 8V19N470 Datasheet Channel Registers The content of the channel registers set the channel state, the clock divider the clock phase delay and the power-down state. Table 32. Channel Register Bit Field Locations Bit Field Location Register Address D7 D6 D5 D4 0x24: Channel A 0x2C: Channel B 0x34: Channel C 0x3C: Channel D 0x58 D2 D1 D0 N_A[7:0] N_B[7:0] N_C[7:0] N_D[7:0] 0x25: Channel A 0x2D: Channel B 0x35: Channel C 0x3D: Channel D 0x26: Channel A 0x2E: Channel B 0x36: Channel C 0x3E: Channel D D3 CLK_A[8:1] CLK_B[8:1] CLK_C[8:1] CLK_D[8:1] PD_A PD_B PD_C PD_D Reserved Reserved Reserved Reserved Reserved Reserved CLK_A0 CLK_B0 CLK_C0 CLK_D0 Reserved Reserved EN_QCLK_V EN_QCLK_A EN_QCLK_B EN_QCLK_C EN_QCLK_D Reserved ©2017 Integrated Device Technology, Inc. 39 November 20, 2017 8V19N470 Datasheet Table 33. Channel Register Descriptions[a] Register Description Bit Field Name Field Type N_x[7:0] R/W Default (Binary) Description N_A, N_B: 0000 0001 Output Frequency Divider N: N_x[7:0] Divider Value Value: 3 1000 0000 1 0000 0000 0000 0001 2 3 N_C, N_D: 0000 0100 0000 0010 0000 0011 4 5 0000 0100 0000 0110 6 8 0100 0011 10 0100 0100 0100 0110 12 16 0100 1011 0100 1100 20 24 0101 0011 0100 1110 30 32 0101 0100 36 0101 1011 40 0101 0110 48 0110 0011 50 0110 0100 60 0101 1110 64 0101 1111 72 0110 0110 80 0110 1110 96 0111 1011 100 0111 1100 120 0111 0110 128 0111 1110 160 Value: 6 ©2017 Integrated Device Technology, Inc. 40 November 20, 2017 8V19N470 Datasheet Table 33. Channel Register Descriptions[a] (Cont.) Register Description Bit Field Name Field Type Default (Binary) CLK_x[8:0] R/W 0 0000 0000 Description CLK_x phase delay for fVCO 2949.12MHz: Delay in ps  CLK_x  169ps (512 steps) CLK_x[8:0] 0 0000 0000 0 0000 0001 0ps 169ps … 1 1111 1111 … 86.664ns CLK_x phase delay for fVCO2457.6MHz: Delay in ps  CLK_x  203ps (512 steps) CLK_x[8:0] PD_x R/W 0 Value: power-up EN_x R/W 0 Value: disabled EN_QCLK_V R/W 0 Value: disabled 0 0000 0000 0 0000 0001 0ps 203ps … 1 1111 1111 … 103.963ns 0  Channel x is powered-up 1  Channel x is power-down QCLK_x Channel Output Enable: 0  All outputs of channel x are disabled at the logic low state 1  All outputs of channel x are enabled QCLK_V Output Enable: 0  QCLK_V is disabled at the logic low state 1  QCLK_V is enabled [a] x A – D. ©2017 Integrated Device Technology, Inc. 41 November 20, 2017 8V19N470 Datasheet Output Registers The content of the output registers set the power-down state, the output style and amplitude. Table 34. Output Register Bit Field Locations Bit Field Location Register Address 0x28: QCLK_A0 0x29: QCLK_A1 0x2A: QCLK_A2 0x30: QCLK_B0 0x31: QCLK_B1 0x32: QCLK_B2 0x38: QCLK_C0 0x39: QCLK_C1 0x40: QCLK_D0 0x41: QCLK_D1 0x4B: QCLK_V D7 D6 D5 D4 PD_A0 PD_A1 PD_A2 Reserved Reserved STYLE_A0 STYLE_A1 STYLE_A2 PD_B0 PD_B1 PD_B2 Reserved Reserved PD_C0 PD_C1 Reserved PD_D0 PD_D1 Reserved PD_V Reserved D3 D1 D0 A_A0[1:0] A_A1[1:0] A_A2[1:0] Reserved Reserved STYLE_B0 STYLE_B1 STYLE_B2 A_B0[1:0] A_B1[1:0] A_B2[1:0] Reserved Reserved Reserved STYLE_C0 STYLE_C1 A_C0[1:0] A_C1[1:0] Reserved Reserved Reserved STYLE_D0 STYLE_D1 A_D0[1:0] A_D1[1:0] Reserved Reserved A_V[1:0] Reserved Reserved STYLE_V[1:0] D2 Table 35. Output Register Descriptions[a] Register Description Bit Field Name Field Type Default (Binary) PD_y R/W 0 Value: power-up PD_V R/W 0: Value: power-up ©2017 Integrated Device Technology, Inc. Description 0  Output QCLK_y is powered up 1  Output QCLK_y is power-down 0  Output QCLK_V is powered up 1  Output QCLK_V is power-down 42 November 20, 2017 8V19N470 Datasheet Table 35. Output Register Descriptions[a] Register Description Bit Field Name Field Type Default (Binary) A_y[1:0] R/W A_y[1:0]: 01 Setting for STYLE  1 (LVPECL) A[1:0]  00: 350mV A[1:0]  01: 500mV A[1:0]  00: 350mV A[1:0]  01: 500mV Value: 350mV A[1:0]  10: 700mV A[1:0]  11: 850mV A[1:0]  10: 700mV A[1:0]  11: 850mV A_V[1:0]: 00 R/W QCLK_y, QCLK_V Output Amplitude. Setting for STYLE  0 (LVDS) Value: 500mV A_V[1:0] Description Termination: 100 across STYLE_y R/W 0 Value: LVDS STYLE_V[1:0] R/W 10 Value: LVCMOS Termination: 50 to VTT[b] QCLK_y Output Format: 0  Output is LVDS (Requires LVDS 100 output termination.) 1  Output is LVPECL (Requires LVPECL 50 output termination of to the specified recommended termination voltage.) QCLK_V Output Format 00  Output is LVDS (Requires LVDS 100 output termination.) 01  Output is LVPECL (Requires LVPECL 50 termination to VTT[b].) 1x  Both QCLK_V and nQCLK_V are single-ended LVCMOS 1.8V outputs. QCLK_V and nQCLK_V are complementary (180º phase difference). [a] y A0, A1, A2, B0, B1, B2, C0, C1, D0, D1. [b] For VTT (Termination voltage) values (see Table 60). ©2017 Integrated Device Technology, Inc. 43 November 20, 2017 8V19N470 Datasheet Status Registers Table 36. Status Register Bit Field Locations Bit Field Location Register Address 0x4C 0x50 0x51 0x53 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved IE_LOLF IE_LOLV IE_REF IE_HOLD IE_CLK_1 IE_CLK_0 Reserved Reserved nLS_LOLF nLS_LOLV LS_REF nLS_HOLD LS_CLK_1 LS_CLK_0 Reserved ST_SEL nST_LOLF nST_LOLV ST_REF nST_HOLD ST_CLK_1 ST_CLK_0 Reserved Reserved Reserved Reserved Reserved ST_VCOF Reserved Reserved Table 37. Status Register Descriptions[a] Register Description Bit Field Name Field Type Default (Binary) IE_LOLF R/W 0 Description Interrupt Enable for FemtoClock NG-PLL Loss-of-lock: 0  Disabled: Setting nLS_LOLF will not cause an interrupt on nINT 1  Enabled: Setting nLS_LOLF will assert the nINT output (nINT 0, interrupt) IE_LOLV R/W 0 Interrupt Enable for VCXO-PLL Loss-of-lock: 0  Disabled: Setting nLS_LOLV will not cause an interrupt on nINT 1  Enabled: Setting nLS_LOLV will assert the nINT output (nINT0, interrupt) IE_CLK_n R/W 0 Interrupt Enable for CLKn Input Loss-of-signal: 0  Disabled: Setting LS_CLK_n will not cause an interrupt on nINT 1  Enabled: Setting LS_CLK_n will assert the nINT output (nINT 0, interrupt) IE_REF R/W 0 Interrupt Enable for Input Reference Loss: 0  Disabled: Setting LS_REF will not cause an interrupt on nINT 1  Enabled: Setting LS_REF will assert the nINT output (nINT 0, interrupt) IE_HOLD R/W 0 Interrupt Enable for Holdover: 0  Disabled: Setting nLS_HOLD will not cause an interrupt on nINT 1  Enabled: Setting nLS_HOLD will assert the nINT output (nINT 0, interrupt) nLS_LOLF R/W – FemtoClock NG-PLL Loss-of-lock (latched status of nST_LOLF): Read 0  1 loss-of-lock events detected after the last status latch clear Read 1  No loss-of-lock detected after the last status latch clear Write 1  Clear status latch (clears pending nLS_LOLF interrupt) ©2017 Integrated Device Technology, Inc. 44 November 20, 2017 8V19N470 Datasheet Table 37. Status Register Descriptions[a] (Cont.) Register Description Bit Field Name Field Type Default (Binary) nLS_LOLV R/W – Description VCXO-PLL Loss-of-lock (latched status of nST_LOLV): Read 0  1 loss-of-lock events detected after the last status latch clear Read 1  No loss-of-lock detected after the last nLS_LOLV clear Write 1  Clear status latch (clears pending nLS_LOLV interrupt) LS_CLK_n R/W – Input CLK_n status (latched status of ST_CLK_n): Read 0  1 LOS events detected on CLK_n after the last LS_CLK_n clear Read 1  No loss-of-signal detected on CLK_n input after the last LS_CLK_n clear Write 1  Clear LS_CLK_n status latch (clears pending LS_CLK_n interrupts on nINT) ST_SEL R – Input Selection (momentary): Reference Input Selection Status of the state machine. In any input selection mode, reflects the input selected by the state machine. 0  CLK_0 1  CLK_1 nST_LOLF R – FemtoClock NG-PLL Loss-of-lock (momentary): Read 0  Loss-of-lock event detected Read 1  No loss-of-lock detected A latched version of these status bit is available (nLS_LOLF). nST_LOLV R – VCXO-PLL Loss-of-lock (momentary): Read 0  Loss-of-lock event detected Read 1  No loss-of-lock detected A latched version of these status bits is available (nLS_LOLV). ST_CLK_n R – Input CLK_n Status (momentary): 0  LOS detected on CLK_n 1  No LOS detected; CLK_n input is active A latched version of these status bits are available (LS_CLK_n). LS_REF R/W – PLL Reference Status (latched status of ST_REF): Read 0  Reference is lost since last reset of this status bit Read 1  Reference is valid since last reset of this status bit Write 1  Clear LS_REF status latch (clears pending LS_REF interrupts on nINT). ©2017 Integrated Device Technology, Inc. 45 November 20, 2017 8V19N470 Datasheet Table 37. Status Register Descriptions[a] (Cont.) Register Description Bit Field Name Field Type Default (Binary) nLS_HOLD R/W – Description Holdover Status Indicator (latched status of ST_HOLD): Read 0  VCXO-PLL has entered holdover state 1 times after reset of this status bit Read 1  VCXO-PLL is (or attempts to) lock(ed) to an input clock Write 1  Clear status latch (clears pending nLS_HOLD interrupt) ST_VCOF R – FemtoClock NG-PLL Calibration Status (momentary): Read 0  FemtoClock NG PLL auto-calibration is completed Read 1  FemtoClock NG PLL calibration is active (not completed) ST_REF R – Input Reference Status (momentary): 0  No input reference present. 1  Input reference is present at the clock selected input clock. nST_HOLD R – Holdover Status Indicator (momentary): 0  VCXO-PLL in holdover state, not locked to any input clock 1  VCXO-PLL is (or attempts to) lock(ed) to input clock A latched version of this status bit is available (nLS_HOLD). [a] CLKn  CLK_0, CLK_1. ©2017 Integrated Device Technology, Inc. 46 November 20, 2017 8V19N470 Datasheet General Control Registers Table 38. General Control Register Bit Field Locations Bit Field Location Register Address 0x55 0x56 0x57 D7 D6 D5 D4 D3 D2 D1 D0 INIT_CLK Reserved Reserved Reserved Reserved Reserved Reserved Reserved RELOCK Reserved Reserved Reserved Reserved Reserved Reserved Reserved PB_CAL Reserved Reserved Reserved Reserved Reserved Reserved CPOL Table 39. General Control Register Descriptions Register Description Default (Binary) Bit Field Name Field Type Description INIT_CLK W only Auto-Clear X Set INIT_CLK  1 to initialize divider functions. Required as part of the startup procedure. RELOCK W only Auto-Clear X Setting this bit to 1 will force the FemtoClock NG PLL to re-lock. PB_CAL W only Auto-Clear X Precision Bias Calibration: Setting this bit to 1 will start the calibration of an internal precision bias current source. The bias current is used as a reference for outputs configured as LVDS and as a reference for the charge pump currents. This bit will auto-clear after the calibration completed. Set as part of the startup procedure. CPOL R/W 0 SPI Read Operation SCLK Polarity: 0  Data bits on SDIO/SDO are output at the falling edge of SCLK edge. 1  Data bits on SDIO/SDO are output at the rising edge of SCLK edge. ©2017 Integrated Device Technology, Inc. 47 November 20, 2017 8V19N470 Datasheet Debug Control Status Register Table 40. Debug Control Status Register Bit Field Locations Bit Field Location Register Address 0x4E D7 D6 Reserved Reserved D5 D4 D3 D2 D1 D0 D1 D0 STAT_PB[5:0] Table 41. Debug Control Register Descriptions Register Description Bit Field Name Field Type Default (Binary) STAT_PB[5:0] R only XX XXXX Description Precision bias current (result of the auto-calibration). Precision Bias Control Registers Table 42. Precision Bias Control Register Bit Field Locations Bit Field Location Register Address 0x63 D7 D6 Reserved D5 D4 D3 D2 OVERRIDE_CURR[5:0] OVERRIDE _CAL Table 43. Precision Bias Control Register Descriptions Register Description Field Type Default (Binary) OVERRIDE _CURR[5:0] R/W 00 0000 OVERRIDE_CAL R/W 0 Bit Field Name ©2017 Integrated Device Technology, Inc. Description Overwrite precision bias current. 0  no overwrite 1  bit pattern in OVERRIDE_CURR[5:0] overwrites the internal precision current auto-calibration. It is recommended to set OVERIDE_CURR[0]  0. 48 November 20, 2017 8V19N470 Datasheet Electrical Characteristics Absolute Maximum Ratings The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 8V19N470 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 44. Absolute Maximum Ratings Item Rating Supply Voltage, VDD_V 3.6V Inputs -0.5V to VDD_V 0.5V Outputs, VO (LVCMOS) -0.5V to VDDO_V 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Outputs, IO (LVDS) Continuous Current Surge Current 50mA 100mA Junction Temperature, TJ 150C Storage Temperature, TSTG -65C to 150C ESD - Human Body Model[a] 1500 ESD - Charged Device Model[a] 750 [a] According to JEDEC JS-001-2012/JESD22-C101. Recommended Operating Conditions Table 45. Recommended Operating Conditions Item Rating Supply Voltage, VDD_V 3.3V Operating Junction Temperature, TJ[a]  130C Board Temperature, TB  105C [a] 130C/10year lifetime is based on the evaluation of intrinsic wafer process technology reliability metrics. The limiting wafer level reliability factor for this technology with respect to high temperature operation is electromigration. The device is verified to the maximum operating junction temperature through simulation. ©2017 Integrated Device Technology, Inc. 49 November 20, 2017 8V19N470 Datasheet DC Characteristics Pin Characteristics Table 46. Pin Characteristics, VDD_V  3.3V ± 5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance OSC, nOSC 2 4 pF Other inputs 2 4 pF RPD Input Pull-down Resistor SCLK, EXT_SEL[1:0], CLK_n, nCLK_n 51 k RPU Input Pull-up Resistor nCLK_n, nCS, nRESET 51 k ROUT LVCMOS Output Impedance LOCK_F, LOCK_V, nINT 25  CIN Table 47. Power Supply DC Characteristics, VDD_V  3.3V ± 5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD_V Core Supply Voltage 3.135 3.3 3.465 V VDDO_V Output Supply Voltage 1.71 1.8, 2.5, 3.3 3.465 V ©2017 Integrated Device Technology, Inc. 50 November 20, 2017 8V19N470 Datasheet Table 48. Typical Power Supply DC Current Characteristics (LVDS), VDD_V  3.3V ±5%, TA  -40°C to 85°C[a] Test Case Symbol IDD_V Supply Pin Current Core 1 2 3 4 VDD_V Current through VDD_V pins IDDO_V QCLK_y 5 6 Unit 3.3 V 325 mA Style LVDS LVDS LVDS LVDS LVDS LVDS  State On On On On On On  Amplitude 350 500 700 850 350 500 mV VDDO_V 3.3 3.3 3.3 3.3 1.8 1.8 V 111 161 203 252 103 147 mA Current through VDDO_V pins PTOT Total Device Power Consumption 1.439 1.603 1.743 1.906 1.257 1.337 W PTOT, SYS Total System Power Consumption[b] 1.439 1.603 1.743 1.906 1.257 1.337 W [a] Device configuration: VCO_SEL 0 (fVCO 2949.12MHz); NA NB NC ND 2, fQCLK_y 1474.56MHz; PV0 PV1 MV0 1000, FDF 1, PF 1, MF 12, ICPV 1.1mA, ICPF 3.4mA. Supply current is independent of the output frequency configuration. QCLK_y outputs terminated 100. [b] Includes total device power consumption and the power dissipated in external output termination components. Table 49. Typical Power Supply DC Current Characteristics (LVPECL), VDD_V  3.3V ±5%, TA  -40°C to 85°C Test Case Symbol IDD_V Supply Pin Current Core PTOT PTOT, SYS 2 3 VDD_V Current through VDD_V pins IDDO_V 1 4 5 6 3.3 Unit V 325 325 326 329 334 335 mA Style LVPECL LVPECL LVPECL LVPECL LVPECL LVPECL  State On On On On On On  Amplitude 350 500 700 850 350 500 mV VDDO_V 3.3 3.3 3.3 3.3 1.8 1.8 V Current through VDDO_V pins 246 276 317 348 244 274 mA Total Device Power Consumption 1.34 1.39 1.47 1.54 1.35 1.39 W Total System Power Consumption[a] 1.88 1.98 2.12 2.23 1.54 1.60 W QCLK_y [a] Includes total device power consumption and the power dissipated in external output termination components. ©2017 Integrated Device Technology, Inc. 51 November 20, 2017 8V19N470 Datasheet Table 50. LVCMOS DC Characteristics, VDD_V  3.3V ± 5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units Control inputs EXT_SEL0, EXT_SEL1, nRESET (1.8V logic and 3.3V tolerance) VIH Input High Voltage 1.17 VDD_V V VIL Input Low Voltage -0.3 0.63 V IIH Input High Current 150 µA EXT_SEL[1:0] inputs with pull-down resistor VDD_V  3.3V, VIN  3.3V nRESET input with pull-up resistor IIL Input Low Current EXT_SEL[1:0] inputs with pull-down resistor 5 VDD_V  3.465V, VIN  0V nRESET input with pull-up resistor -5 µA -150 Control inputs nCS, SCLK and SDIO (when input) (1.8V logic, hysteresis) V T Positive-going Input Threshold Voltage 0.72 1.26 V V T- Negative-going Input Threshold Voltage 0.54 1.08 V VH Hysteresis Voltage V T  V T- 0.18 0.72 V IIH Input High Current VDD_V  3.3V, VIN  1.8V IIL Input Low Current SCLK input with pull-down resistor 150 nCS input with pull-up resistor 5 SDIO (when input) 5 SCLK input with pull-down resistor VDD_V  3.465V, VIN  0V µA -5 nCS input with pull-up resistor -150 SDIO (when input) -5 µA Control outputs configured to 3.3V VOH Output High Voltage VOL Output Low Voltage SDO, nINT, LOCK_F, LOCK_V, SDIO (when output) IOH  -4mA 2.0 IOL  4mA V 0.55 V 1.8 V 0.45 V Control outputs configured to 1.8V VOH Output High Voltage VOL Output Low Voltage SDO, nINT, LOCK_F, LOCK_V, SDIO (when output) ©2017 Integrated Device Technology, Inc. IOH  -4mA IOL  4mA 52 1.35 November 20, 2017 8V19N470 Datasheet Table 51. Differential Input DC Characteristics, VDD_V  3.3V ± 5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C Symbol IIH Parameter Input High Current Test Conditions Minimum Typical VDD_V  VIN  3.465V Input with pull-down resistor[a] Input with pull-up/pull-down resistor[b] IIL Input Low Current VDD_V  3.465V, VIN  0V Input with pull-down resistor[a] Input with pull-up/pull-down resistor[b] Maximum Units 150 µA 150 µA -150 µA -150 µA [a] Non-Inverting inputs: CLK_0, CLK_1, OSC. [b] Inverting inputs: nCLK_0, nCLK_1, nOSC. Table 52. LVPECL DC Characteristics (QCLK_y, QREF_r, STYLE 1), VDD_V  3.3V ±5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C Symbol VOH VOL Parameter Output High Voltage[a] [b] Output Low Voltage[a] [b] Test Conditions Minimum Typical Maximum Units 350mV amplitude setting VDDO_V  1.00 VDDO_V  0.88 VDDO_V  0.76 V 500mV amplitude setting VDDO_V  1.02 VDDO_V  0.90 VDDO_V  0.78 V 700mV amplitude setting VDDO_V  1.04 VDDO_V  0.94 VDDO_V  0.83 V 850mV amplitude setting VDDO_V  1.06 VDDO_V  0.96 VDDO_V  0.86 V 350mV amplitude setting VDDO_V  1.38 VDDO_V  1.25 VDDO_V  1.13 V 500mV amplitude setting VDDO_V  1.54 VDDO_V  1.42 VDDO_V  1.30 V 700mV amplitude setting VDDO_V  1.75 VDDO_V  1.62 VDDO_V  1.51 V 850mV amplitude setting VDDO_V  1.90 VDDO_V 1.79 VDDO_V  1.68 V [a] Outputs terminated with 50 to VTT. For termination voltage VTT values (see Table 60). [b] 700mV and 850mV amplitude settings are only available at VDDO_V ≥ 2.5V. Table 53. LVDS DC Characteristics (QCLK_y, QREF_r, STYLE 0), VDD_V  3.3V ± 5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C Symbol VOS VOS Parameter Offset Voltage[a] [b] Test Conditions Minimum Typical Maximum Units 350mV amplitude setting VDDO_V  1.146 VDDO_V  0.982 VDDO_V  0.809 V 500mV amplitude setting VDDO_V  1.249 VDDO_V  1.084 VDDO_V  0.928 V 700mV amplitude setting VDDO_V  1.351 VDDO_V  1.198 VDDO_V  1.026 V 850mV amplitude setting VDDO_V  1.460 VDDO_V  1.296 VDDO_V  1.131 V  18 50 mV VOS Magnitude Change [a] VOS changes with VDDO_V. [b] 750mV and 1000mV amplitude settings are only available at VDDO_V ≥ 2.5V. ©2017 Integrated Device Technology, Inc. 53 November 20, 2017 8V19N470 Datasheet AC Characteristics Table 54. AC Characteristics, VDD_V  3.3V ±5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C[a] Symbol fVCO fOUT Parameter Test Conditions VCO Frequency Range Output Frequency VCO-0 VCO-1 fOUT Minimum Typical Maximum Units VCO-0 2920 2949.12 3000 MHz VCO-1 2400 2457.6 2500 MHz QCLK_y, N 1 2949.12 MHz QCLK_y, N 2 1474.56 MHz QCLK_y, N 3 983.04 MHz QCLK_y, N 4 737.28 MHz QCLK_y, N 6 491.52 MHz QCLK_y, N 8 368.64 MHz QCLK_y, N 12 245.76 MHz QCLK_y, N 24 122.88 MHz QCLK_y, N 96 30.72 MHz QCLK_y, N 1 2457.6 MHz QCLK_y, N 2 1228.8 MHz QCLK_y, N 4 614.4 MHz QCLK_y, N 8 307.2 MHz QCLK_y, N 10 245.76 MHz QCLK_y, N 16 153.6 MHz QCLK_y, N 20 122.88 MHz Output Frequency Accuracy Integer output divider, N[A – D] fIN Input Frequency CLK_n fVCXO VCXO Frequency VIN VDIFF_IN VCMR odc tR / t F 0.008 25 122.88 0 ppb 307.2 MHz 250 MHz Input Voltage Amplitude[c] CLK_n 0.15 1.2 V Differential Input Voltage Amplitude[c], [d] CLK_n 0.3 2.4 V 1.0 VDD_V – (VIN / 2) V 50 55 % Common Mode Input Voltage Output Duty Cycle QCLK_y Output Rise/Fall Time, Differential QCLK_y (LVPECL), 20% to 80% 146 250 ps QCLK_y (LVDS), 20% to 80% 146 250 ps 1 ns Output Rise/Fall Time ©2017 Integrated Device Technology, Inc. [b] 45 LVCMOS outputs, 20% to 80% 54 November 20, 2017 8V19N470 Datasheet Table 54. AC Characteristics, VDD_V  3.3V ±5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C[a] Symbol VO(PP)[e] Parameter LVPECL Output Voltage Swing, Peak-to-peak, (see Table 58) LVPECL Differential Output Voltage Swing, Peak-to-peak, (see Table 58) VOD[f] LVDS Output Voltage Swing, Peak-to-peak, 1474.56MHz, (see Table 58) LVDS Differential Output Voltage Swing, Peak-to-peak, 1474.56MHz, (see Table 58) tsk(o)  Test Conditions [b] Minimum Typical Maximum Units 350mV amplitude 1474.56MHz 491.52MHz 366 352 384 368 402 382 mV 500mV amplitude 1474.56MHz 491.52MHz 498 485 513 500 528 515 mV 700mV amplitude 1474.56MHz 491.52MHz 692 666 714 689 735 711 mV 850mV amplitude 1474.56MHz 491.52MHz 822 802 847 825 872 849 mV 350mV amplitude 1474.56MHz 491.52MHz 713 703 768 736 800 764 mV 500mV amplitude 1474.56MHz 491.52MHz 997 970 1027 1000 1057 1031 mV 700mV amplitude 1474.56MHz 491.52MHz 1385 1333 1427 1378 1470 1422 mV 850mV amplitude 1474.56MHz 491.52MHz 1643 1604 1694 1651 1745 1698 mV 350mV amplitude 1474.56MHz 491.52MHz 250 298 275 314 301 329 mV 500mV amplitude 1474.56MHz 491.52MHz 362 430 391 446 419 462 mV 700mV amplitude 1474.56MHz 491.52MHz 496 602 571 637 646 673 mV 850mV amplitude 1474.56MHz 491.52MHz 621 743 708 781 794 819 mV 350mV amplitude 1474.56MHz 491.52MHz 500 596 550 627 601 658 mV 500mV amplitude 1474.56MHz 491.52MHz 724 861 781 892 838 924 mV 700mV amplitude 1474.56MHz 491.52MHz 993 1203 1142 1274 1291 1346 mV 850mV amplitude 1474.56MHz 491.52MHz 1243 1487 1415 1563 1588 1639 mV QCLK_y (same N divider) 41 80 65[i] ps QCLK_y (any N divider, incident rising edge) 34 80 60i ps Output Skew; NOTE[g] [h] All delays set to 0. Output Isolation between any neighboring clock output ©2017 Integrated Device Technology, Inc. fOUT  1474.56MHz[j] fOUT  368.64MHz[k] 55 70.5 74.2 dB 83 86.9 dB November 20, 2017 8V19N470 Datasheet Table 54. AC Characteristics, VDD_V  3.3V ±5%, VDDO_V  (3.3V, 2.5V or 1.8V) ±5%, TA  -40°C to 85°C[a] Symbol Parameter tD, LOS LOS State Detected (measured in input reference periods) PLL Lock Detect: 1st PLL bandwidth: PLL re-lock time after a short-term holdover scenario. Measured from LOS to both PLLs lock-detect asserted; initial frequency error < 200ppm. Measured in External-Controlled Holdover mode transition to external manual mode. 100Hz 20Hz tD, LOCK tD, RES Test Conditions Maximum Units fCLK 122.88MHz 2 TCLK fCLK 245.76MHz 3 PLL Lock Residual Time Error: Minimum Typical [b] 13.28 141 300 300 ms 0.14 20 ns 3.52 1.3 ±5.0 ±5.0 ppm 6.85 ±8.138 ns Refer to PLL lock detect tD,LOCK. Reference point: final value of clock output phase after all phase transitions settled. Measured in automatic switch mode. Measured in automatic with holdover mode. Measured in automatic with holdover mode. fHOLD tD, RES-H Holdover Accuracy: 1st PLL bandwidth: Maximum frequency deviation during a holdover duration of 200ms and after the clock re-validate event. Measured in External-Controlled Holdover mode transition to external manual modes. 100Hz 20Hz Holdover Residual Error: Measured 50ms after the reference clock re-appeared in a holdover scenario. Reference point: final value of clock output phase after all phase transitions settled. Measured in automatic with holdover mode. [a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. [b] VCXO-PLL bandwidth  100Hz. [c] VIL should not be less than -0.3V and VIH should not be greater than VDD_V. [d] Common Mode Input Voltage is defined as the cross-point voltage. [e] Outputs terminated with 50 to VTT. For termination voltage VTT values (see Table 60). [f] LVDS outputs terminated 100 across terminals. [g] This parameter is defined in accordance with JEDEC standard 65. [h] Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. [i] Excluding QCLKC0. [j] 0–2949.12MHz. [k] 0–737.28MHz. ©2017 Integrated Device Technology, Inc. 56 November 20, 2017 8V19N470 Datasheet Clock Phase Noise Characteristics Conditions for Phase Noise Characteristics: VCXO characteristics: f 30.72MHz and phase noise: -96dBc/Hz (10Hz), -127dBc/Hz (100Hz), -144dBc/Hz (1kHz),-159dBc/Hz (10kHz), -162dBc/Hz (100kHz) ▪ ▪ ▪ ▪ ▪ Input reference frequency: 30.72MHz VCXO-PLL bandwidth: 5Hz VCXO-PLL charge pump current: 1.1mA FemtoClock-NG PLL bandwidth: 139kHz VDD_V  3.3V, TA  25oC Figure 9. 1474.56MHz Output Phase Noise (fVCXO 30.72MHz) ©2017 Integrated Device Technology, Inc. 57 November 20, 2017 8V19N470 Datasheet Figure 10. 983.04MHz Output Phase Noise (fVCXO 30.72MHz) ©2017 Integrated Device Technology, Inc. 58 November 20, 2017 8V19N470 Datasheet Figure 11. 737.28MHz Output Phase Noise (fVCXO 30.72MHz) ©2017 Integrated Device Technology, Inc. 59 November 20, 2017 8V19N470 Datasheet Figure 12. 491.52MHz Output Phase Noise ©2017 Integrated Device Technology, Inc. 60 November 20, 2017 8V19N470 Datasheet Figure 13. 368.64MHz Output Phase Noise ©2017 Integrated Device Technology, Inc. 61 November 20, 2017 8V19N470 Datasheet Figure 14. 245.76MHz Output Phase Noise ©2017 Integrated Device Technology, Inc. 62 November 20, 2017 8V19N470 Datasheet Figure 15. 122.88MHz Output Phase Noise ©2017 Integrated Device Technology, Inc. 63 November 20, 2017 8V19N470 Datasheet Table 55. Clock Phase Noise Characteristics (fVCXO = 122.88MHz), VDD_V = 3.3V ±5%, VDDO_V = (3.3V, 2.5V, or 1.8V) ±5%, TA = -40°C to +85°C [a] [b] Symbol tjit(Ø) N(10) N(100) N(1k) N(10k) Parameter Clock RMS Phase Jitter (Random) Clock Single-side Band Phase Noise (integer divider) 1474.56MHz N(100k) N(1M) N(10M) N(10) N(100) N(1k) N(10k) Clock Single-side Band Phase Noise (integer divider) 983.04MHz N(100k) N(1M) N(10M) N(10) N(100) N(1k) N(10k) Clock Single-side Band Phase Noise (integer divider) 737.28MHz N(100k) N(1M) N(10M) N(10) N(1k) Clock Single-side Band Phase Noise N(10k) (integer divider) N(100) 491.52MHz N(100k) N(1M) N(10M) ©2017 Integrated Device Technology, Inc. Test Conditions Minimum Typical Maximum Units Integration Range: 1kHz ― 76.8MHz 90 150 fs Integration Range: 12kHz ― 20MHz 104 139 fs 10Hz offset (determined by VCXO) -59.9 dBc/Hz 100Hz offset (determined by VCXO) -87.6 dBc/Hz 1kHz offset from carrier -111 -105 dBc/Hz 10kHz offset from carrier -123.2 -112 dBc/Hz 100kHz offset from carrier -127.7 -118 dBc/Hz 1MHz offset from carrier -138.7 -135 dBc/Hz 10MHz offset from carrier and Noise Floor -152.8 -147 dBc/Hz 10Hz offset (determined by VCXO) -64.1 dBc/Hz 100Hz offset (determined by VCXO) -93.6 dBc/Hz 1kHz offset from carrier -114.3 -105 dBc/Hz 10kHz offset from carrier -125.4 -115 dBc/Hz 100kHz offset from carrier -130.1 -120 dBc/Hz 1MHz offset from carrier -141.4 -135 dBc/Hz 10MHz offset from carrier and Noise Floor -153.8 -150 dBc/Hz 10Hz offset (determined by VCXO) -67.5 dBc/Hz 100Hz offset (determined by VCXO) -93.9 dBc/Hz 1kHz offset from carrier -117.7 -110 dBc/Hz 10kHz offset from carrier 128.7 -118 dBc/Hz 100kHz offset from carrier 133.5 -123 dBc/Hz 1MHz offset from carrier -144.4 -138 dBc/Hz 10MHz offset from carrier and Noise Floor -155.8 -150 dBc/Hz 10Hz offset (determined by VCXO) -71 dBc/Hz 100Hz offset (determined by VCXO) -101.1 dBc/Hz 1kHz offset from carrier -119.9 -110 dBc/Hz 10kHz offset from carrier -132.2 -120 dBc/Hz 100kHz offset from carrier -137 -125 dBc/Hz 1MHz offset from carrier -146.5 -142 dBc/Hz 10MHz offset from carrier and Noise Floor -157.2 -150 dBc/Hz 64 November 20, 2017 8V19N470 Datasheet Table 55. Clock Phase Noise Characteristics (fVCXO = 122.88MHz), VDD_V = 3.3V ±5%, VDDO_V = (3.3V, 2.5V, or 1.8V) ±5%, TA = -40°C to +85°C [a] [b] (Cont.) Symbol N(10) Parameter N(1k) Clock Single-side Band Phase Noise N(10k) (integer divider) N(100) 368.64MHz N(100k) N(1M) N(100) N(1k) N(10k) Clock Single-side Band Phase Noise (integer divider) 245.76MHz N(100k) N(1M) N(10M) N(10) N(100) N(1k) N(10k) Clock Single-side Band Phase Noise (integer divider) 122.88MHz N(100k) N(1M) N(10M) Minimum Typical Maximum Units 10Hz offset (determined by VCXO) -64.6 dBc/Hz 100Hz offset (determined by VCXO) -100.6 dBc/Hz 1kHz offset from carrier -122.9 -113 dBc/Hz 10kHz offset from carrier -134.4 -123 dBc/Hz 100kHz offset from carrier -139.4 -128 dBc/Hz -150 -146 dBc/Hz 10MHz offset from carrier and noise Floor -158.1 -153 dBc/Hz 10Hz offset (determined by VCXO) -71.7 dBc/Hz 100Hz offset (determined by VCXO) -105.5 dBc/Hz 1kHz offset from carrier -128.3 -115 dBc/Hz 10kHz offset from carrier -138 -130 dBc/Hz 100kHz offset from carrier -142.7 -135 dBc/Hz 1MHz offset from carrier -153.2 -148 dBc/Hz 10MHz offset from Carrier and noise Floor -160.5 -155 dBc/Hz 10Hz offset (determined by VCXO) -83.3 dBc/Hz 100Hz offset (determined by VCXO) -114.3 dBc/Hz 1kHz offset from carrier -132.3 -120 dBc/Hz 10kHz offset from carrier -144.6 -130 dBc/Hz 100kHz offset from carrier -149.3 -135 dBc/Hz 1MHz offset from carrier -158.1 -150 dBc/Hz 10MHz offset from carrier and noise Floor -161.5 -155 dBc/Hz 1MHz offset from carrier N(10M) N(10) Test Conditions [a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. [b] Phase noise specifications are applicable for all outputs active, Nx not equal. Measured using a VCXO with the following characteristics: 122.88MHz, phase noise -145dBc/Hz at 1kHz, -155dBc/Hz at 10kHz offset, -160dBc/Hz at 100kHz offset ©2017 Integrated Device Technology, Inc. 65 November 20, 2017 8V19N470 Datasheet Table 56. 8V19N470 AC Characteristics: Typical QCLK_y Output Amplitude, VDD_V = 3.3V, TA = 85°C[a] Symbol VO(PP) [b] VOD [c] Parameter Test Conditions LVPECL Output Voltage Swing, Peak-to-peak LVDS Output Voltage Swing, Peak-to-peak QCLK_y Output Frequency in MHz Units 1474.57 1228.8 983.04 737.28 491.52 245.76 350mV Amplitude Setting 768 715 745 706 736 723 mV 500mV Amplitude Setting 1027 996 1003 968 1000 994 mV 700mV Amplitude Setting 1427 1342 1397 1321 1378 1355 mV 850mV Amplitude Setting 1694 1617 1675 1587 1651 1626 mV 350mV Amplitude Setting 550 581 604 612 627 645 mV 500mV Amplitude Setting 781 819 851 870 892 909 mV 700mV Amplitude Setting 1142 1201 1251 1240 1274 1282 mV 850mV Amplitude Setting 1415 1487 1550 1521 1563 1566 mV [a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. [b] LVPECL outputs terminated 50 to VTT. For VTT (Termination voltage) values (see Table 60). [c] LVDS outputs terminated 100 across terminals ©2017 Integrated Device Technology, Inc. 66 November 20, 2017 8V19N470 Datasheet Thermal Characteristics Table 57. Thermal Resistance for 81-FPBGA Package[a] Multi-Layer PCB, JEDEC Standard Test Board Symbol JA Thermal Parameter Junction-to-ambient Condition Value Unit 0 m/s air flow 33.4 °C/W 2 m/s air flow 28.7 °C/W JC Junction-to-case 17.8 °C/W JB Junction-to-board[b] 9.8 °C/W [a] Standard JEDEC 2S2P multilayer PCB. [b] Thermal model where the heat dissipated in the component is conducted through the board. TB is measured on or near the component lead. Temperature Considerations The device supports applications in a natural convection environment as long as the junction temperature does not exceed the specified junction temperature TJ. In applications where the heat dissipates through the PCB, JB is the correct metric to calculate the junction temperature. The following calculation uses the junction-to-board thermal characterization parameter JB to calculate the junction temperature (TJ). Care must be taken to not exceed the maximum allowed junction temperature TJ of 130 °C. The junction temperature TJ is calculated using the following equation: T J = T B + P TOT   JB where: ▪ ▪ ▪ ▪ TJ is the junction temperature at steady state conditions in °C. TB is the board temperature at steady state condition in °C, measured on or near the component lead. JB is the thermal characterization parameter to report the difference between TJ and TB. PTOT is the total device power dissipation. Application power dissipation scenarios: Applications may use device settings that result in a lower power dissipation than the maximum power scenario. The device is a multi-functional, high-speed device that targets a variety of applications. Since this device is highly programmable with a broad range of settings and configurations, the power consumption will vary as settings and configurations are changed. Table 58 shows the typical current consumption and total device power consumption along with the junction temperature for the test cases shown in Table 48 and Table 49. The table also displays the maximum board temperature for the JB model. ©2017 Integrated Device Technology, Inc. 67 November 20, 2017 8V19N470 Datasheet Reducing power consumption: The output state (on/off) and the output amplitude have the largest impact on the device power consumption and the junction temperature: setting the output amplitude to lower voltages and supplying the outputs by 1.8V reduces power consumption. Unused and periodically unused outputs and inputs should be turned off in phases of inactivity to reduce power. For any given divider setting, the clock frequency has no impact on the device power consumption of the device. Table 58. Typical Device Power Dissipation and Junction Temperature for LVDS Output Configurations JB Thermal Model Device Test Case[a] Output Configuration IDD_V IDDO_V PTOT TJ[b] TB, MAX[c] mA mA W °C °C 1 QCLK: LVDS, 350mV, VDDO 3.3V 325 111 1.439 99.1 115.9 2 QCLK: LVDS, 500mV, VDDO 3.3V 325 161 1.604 100.7 114.3 3 QCLK: LVDS, 700mV, VDDO 3.3V 325 203 1.742 102.1 112.9 4 QCLK: LVDS, 850mV, VDDO 3.3V 325 252 1.904 103.7 111.3 5 QCLK: LVDS, 350mV, VDDO 1.8V 325 103 1.258 97.3 117.7 6 QCLK: LVDS, 500mV, VDDO 1.8V 325 147 1.337 98.1 116.9 [a] For device settings (see Table 58). [b] Junction temperature at board temperature TB 85°C. [c] Maximum board temperature for junction temperature < 130°C: TB, MAX = TJ, MAX – ΘJB  PTOT. Table 59. Typical Device Power Dissipation and Junction Temperature for LVPECL Output Configurations JB Thermal Model Device Test Case[a] Output Configuration IDD_V IDDO_V PTOT TJ[b] TB, MAX[c] mA mA W °C °C 1 QCLK: LVPECL, 350mV, VDDO 3.3V 325 246 1.340 98.1 116.9 2 QCLK: LVPECL, 500mV, VDDO 3.3V 325 276 1.390 98.6 116.4 3 QCLK: LVPECL, 700mV, VDDO 3.3V 326 317 1.470 99.4 115.6 4 QCLK: LVPECL, 850mV, VDDO 3.3V 329 348 1.540 100.1 114.9 5 QCLK: LVPECL, 350mV, VDDO 1.8V 334 244 1.350 98.2 116.8 6 QCLK: LVPECL, 500mV, VDDO 1.8V 335 274 1.390 98.6 116.4 [a] For device settings (see Table 59). [b] Junction temperature at board temperature TB 85°C. [c] Maximum board temperature for junction temperature < 130°C: TB, MAX = TJ, MAX – ΘJB  PTOT. ©2017 Integrated Device Technology, Inc. 68 November 20, 2017 8V19N470 Datasheet Applications Information VCXO-PLL Loop Filter Each of the two PLLs uses a loop filter with external components. The value of the external components depend on the desired loop bandwidth for each PLL, the input clock frequency and in the case of the VCXO-PLL, on the external VCXO component. For the VCXO-PLL (first PLL stage), a 2nd or 3rd order loop filter may be used. The loop filter of the VCXO-PLL is connected to the device through the LFV charge pump input. The filter output is connected to the control voltage input of the external VCXO. The FemtoClock NG PLL (second PLL stage) may use a 2nd order loop filter. The LFF output of the device connects to filter input and LFFR to the filter output. Typical loop filters are shown in Figure 16 (2nd order) in Figure 17 (3rd order) and are discussed below. Step by step calculations to determine the value of the loop filter components values are shown. Second-Order Loop Filter Figure 16. Second-Order Loop Filter VCXO Control Input LFV Output (charge pump) CZ CP RZ Step-by-step calculation: Step 1: Determine the desired loop bandwidth fC. fC must satisfy the following condition: f PD ----- » 20 fC Where fPD is the input frequency of the VCXO-PLL phase detector frequency. Step 2: Calculate RZ by: 2  f C M V R Z = -------------------------------------I CP  K VCXO Where ICP is the VCXO-PLL charge pump current and KVCXO is the gain of the VCXO component (consult the datasheet of the external VCXO for its gain parameter). MV is the effective feedback divider: f VCXO M V = ------------------f PD fVCXO is the frequency of the external VCXO component. ©2017 Integrated Device Technology, Inc. 69 November 20, 2017 8V19N470 Datasheet Step 3: Calculate CZ by:  C Z = --------------------2f C R Z fC  = -----fZ α is ratio between the loop bandwidth and the filter zero. fZ is the filter zero. α should be greater than 3. Step 4: Calculate CP by: CZ C P = ------ fP  = ----fC fP is the pole and β is ratio between the pole and the loop bandwidth. β should be greater than 3. Step 4: Verify that the phase margin PM is greater than 50°. b–1 PM = atan -----------2 b CZ b = ------- + 1 CP Example calculation: The Block Diagram shows a 2nd order loop filter for the VCXO-PLL. In this example, the VCXO-PLL reference frequency is 122.88MHz and an external VCXO component of 122.88MHz is used. The desired VCXO-PLL loop bandwidth f C is 40 Hz. To achieve the desired loop bandwidth with small size loop filter components, set the PLL frequency pre-divider PV and the PLL feedback divider MV to 1024. According to the step 1 instruction, fPD is 120kHz. This satisfies the condition fPD/fC >> 20. RZ is calculated 32.2k. The VCXO gain KVCXO used for the device reference circuit is 10kHz/V. The charge pump current of the VCXO-PLL is configurable from 50µA to 1200µA. The charge pump current is programmed to ICP 800uA. For α 8, CZ is calculated to be 0.99µF. CZ greater than this value assures α > 12. For example, the actual chosen value is the standard capacitor value of 1µF. For β 5, CP is calculated 24.7nF. The standard capacitor value of CP  27ps ensures β > 7. ©2017 Integrated Device Technology, Inc. 70 November 20, 2017 8V19N470 Datasheet Third-Order Loop Filter Figure 17. Third Order Loop Filter VCXO Control Input LFV Output (charge pump) RP2 CZ CP CP2 RZ Figure 17 shows a third-order loop filter. The filter is equivalent to the 2nd order filter in Figure 16 with the addition components RP2 and CP2. The additional components RP2 and CP2 should be calculated as shown: CP  RZ C P2 = -------------------  R P2 R P2  R Z  1.5  is the ratio between the 1st pole and the 2nd pole.  should be greater than 3. Example calculation for the 3rd order loop filter shown in Figure 17: Equivalent to the 2nd order loop filter calculation, RZ 33k, CZ 1µF, and CP 27nF. RP2 should be in the range of 0.5 RZ < RP2 < 2.5  RZ, for instance 51k With   4, CP2 is 4.37nF (select 4.7µF). FemtoClock NG PLL Loop Filter Figure 18 shows a 2nd order loop filter for the FemtoClock NG PLL. This loop filter is equivalent to Figure 16 and uses the loop filter components RZF (RZ), CZF (CZ) and CPZ (CP). The VCO frequency of the FemtoClock NG PLL is 2949.12MHz. Figure 18. 2nd Order Loop Filter for the FemtoClock NG PLL LFFR CZF CPF RZF LFF Example calculation for the 2nd order loop filter shown in Figure 18: the FemtoClock NG receives its reference frequency from the VCXO output. With the PF pre-divider set to 1, the phase detector frequency is also 122.88MHz. The PLL feedback divider must be set to MF 24 in order to locate the VCO frequencies in its center range. A target PLL loop bandwidth fC is 80kHz satisfies the condition in step 1. The gain of the internal VCO is 30MHz/V and the charge pump current ICP is set to 3.6mA. Using the formula for RZ in step 2, RZF is calculated 103 (chose the standard value of 100; using the formula for CZ in step 3, CZF is calculated 88nF for α  4. A capacitor larger than 88nF should be used for CZF to assure that the α is greater than 4, for instance the standard component capacitor value 100nF. The recommended CPF value for the loop filter is 40pF (loop filter components are partially integrated). The selected 2nd order loop filter components for this PLL are: RZF  100CZF  100nF, and CPF  40pF. ©2017 Integrated Device Technology, Inc. 71 November 20, 2017 8V19N470 Datasheet Output Termination LVPECL-style Outputs Differential outputs configured to LVPECL-style are of open-emitter type and require a termination with a DC current path to GND. This section displays parallel and thevenin termination, Y-termination and source termination for various output supply (VDDO_V) and amplitude settings. VTT is the termination voltage. Figure 19. Parallel Termination 1 VDD_v Zo = 50 + - Zo = 50 LVPECL Dr iv er R2 R1 50 50 H igh Impedance Input N o Built- in T er mination VTT   Table 60. Termination Voltage VTT for Figure 19[a] LVPECL Amplitude (mV) VTT (V) 350 VDDO_V  1.60 500 VDDO_V  1.75 700 VDDO_V  1.95 850 VDDO_V  2.10 [a] Output power supplies supporting 3.3V, 2.5V and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and VDDO_QCLKD. ©2017 Integrated Device Technology, Inc. 72 November 20, 2017 8V19N470 Datasheet Figure 20. Parallel Termination 2 VD D_v VDD_v R1 R3 + Zo = 50 - Zo = 50 LVPECL Dr iv er R2 R4 H igh Impedance Input N o Built-in T ermination   Table 61. Termination Resistor Values for Figure 20 VDDO_V (V)[a] LVPECL Amplitude (mV) R1, R3 () R2, R4 () 3.3 350 97.1 103.1 500 106.5 94.3 700 122 84.6 850 137.5 78.6 350 138.8 78.1 500 166.7 71.4 700 227.3 64.1 850 312.5 59.5 350 450 56.3 500 – 50 2.5 1.8 [a] Output power supplies supporting 3.3V, 2.5V and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC, and VDDO_QCLKD. ©2017 Integrated Device Technology, Inc. 73 November 20, 2017 8V19N470 Datasheet Figure 21. Y-Termination VDD_v Zo = 50 + - Zo = 50 LVPECL Dr iv er R2 R1 50 50 C1 0. 1uF (opt ional) H igh Impedance Input N o Built-in T ermination R3   Table 62. Termination Resistor Values for Figure 21 VDDO_V (V)[a] LVPECL Amplitude (mV) R3 () 3.3 350, 500, 700, 850 50 2.5 350, 500, 700, 850 18 1.8 350, 500 0 [a] Output power supplies supporting 3.3V, 2.5V and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC, and VDDO_QCLKD. Figure 22. Source Termination VDD_v LVPECL Dr iv er Z o = 50 + R3 100 - Z o = 50 R2 R1 High Impedance I nput No Built-in Termination   Table 63. Termination Resistor Values for Figure 22 VDDO_V (V)[a] LVPECL Amplitude (mV) R1, R2 () 3.3 350, 500, 700, 850 100 – 200 2.5 350, 500, 700, 850 80 – 150 1.8 350 50 – 100 [a] Output power supplies supporting 3.3V, 2.5V and 1.8V are VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC and VDDO_QCLKD. ©2017 Integrated Device Technology, Inc. 74 November 20, 2017 8V19N470 Datasheet Figure 23. LVDS-Style Outputs (1) VCC =3.3V Z o = 50 + R1 100 Z o = 50 - LVDS St yle Driver High Impedance I nput No Built-in Termination   Figure 24. LVDS-Style Outputs (2) VDD_v Zo = 50 + - Zo = 50 LVDS St yle Driver R2 R1 50 50 H igh Impedance Input N o Built- in T ermination C1 0. 1uF (opt ional)   LVDS style outputs support fully differential terminations. LVDS does not require board level pull-down resistors for DC termination. Figure 23 and Figure 24 show typical termination examples with DC coupling for the LVDS style driver. In these examples, the receiver is high input impedance without built-in termination. LVDS-style with a differential termination is preferred for best common-mode rejection and lowest device power consumption. ©2017 Integrated Device Technology, Inc. 75 November 20, 2017 8V19N470 Datasheet Power Supply Filtering Please refer to the document 8V19N470 Hardware Design Guide for comprehensive information about power supply and isolation, loop filter design for VCXO and VCO, schematics, input and output interfaces/terminations and an example schematics. This document shows a recommended power supply filter schematic in which the device is operated at VDD_V  3.3V (The output supply voltages of VDDO_V  3.3V, 2.5V and 1.8V are supported). This example focuses on power supply connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set for the application. As with any high speed analog circuitry, the power supply pins are vulnerable to board supply or device generated noise. This device requires an external voltage regulator for the VDD_V pins for isolation of board supply noise. This regulator (example component: PS7A8300RGT) is indicated in the schematic by the power supply, VREG_3.3V. Consult the voltage regulator specification for details of the required performance. To achieve optimum jitter performance, power supply isolation is required to minimize device generated noise. The VDD_LCF terminal requires the cleanest power supply. The device provides separate power supplies to isolate any high switching noise from coupling into the internal PLLs and into other outputs as shown. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited the 0.1µF and 0.01µF capacitors in each power pin filter should be placed on the device side. The other components can be on the opposite side of the PCB. Pull-up and pull-down resistors to set configuration pins can all be placed on the PCB side opposite the device side to free up device side area if necessary. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for a wide range of noise frequencies. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. ©2017 Integrated Device Technology, Inc. 76 November 20, 2017 8V19N470 Datasheet Package Outline Drawings Figure 25. Package Outline Drawings – Sheet 1 ©2017 Integrated Device Technology, Inc. 77 November 20, 2017 8V19N470 Datasheet Figure 26. Package Drawings – Sheet 2 ©2017 Integrated Device Technology, Inc. 78 November 20, 2017 8V19N470 Datasheet Figure 27. Package Drawings – Sheet 3 ©2017 Integrated Device Technology, Inc. 79 November 20, 2017 8V19N470 Datasheet Marking Diagram Figure 28. Marking Diagram 1. Line 1 indicates the prefix 2. Line 2 indicates the part number. 3. Line 3 indicates the package part number code. 4. Line 4: ▪ “YYWW” is the last digit of the year and week that the part was assembled. ▪ #: denotes sequential lot number. ▪ $: denotes mark code. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8V19N470BFGI IDT8V19N470BFGI 8  8  1.35 mm, 81-FPBGA Tray -40°C to +85°C 8V19N470BFGI8 IDT8V19N470BFGI 8  8  1.35 mm, 81-FPBGA Tape and Reel -40°C to +85°C Glossary Table 64. Glossary Abbreviation Description Index n Denominates a clock input. Range: 0 to 1. Index x Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D. Index y Denominates a QCLK output and associated configuration bits. Range: A0, A1, A2, B0, B1, B2, C0, C1, D0, D1. VDD_V Denominates core voltage supply pins. Range: VDD_QCLKA, VDD_QCLKB, VDD_QCLKC, VDD_QCLKD, VDD_QCLKE, VDD_SPI, VDD_INP, VDD_LCV, VDD_LCF, VDD_CPV, VDD_CPF and VDD_OSC. VDDO_V Denominates output voltage supply pins. Range: VDDO_QCLKA, VDDO_QCLKB, VDDO_QCLKC, and VDDO_QCLKD. status_condition Status conditions are: LOLV (Loss of VCXO-PLL lock), LOLF (Loss of FemtoClock NG PLL lock) and LOS (Loss of input signal). [...] Index brackets describe a group associated with a logical function or a bank of outputs. {…} List of discrete values. Suffix V Denominates a function associated with the VCXO-PLL. Suffix F Denominates a function associated with the 2nd stage PLL (FemtoClock NG). ©2017 Integrated Device Technology, Inc. 80 November 20, 2017 8V19N470 Datasheet Revision History Revision Date November 20, 2017 Description of Change Initial release. Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT’s sole discretion. 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