FemtoClock® NG Jitter Attenuator
and Clock Synthesizer
8V19N492
Datasheet
Description
Features
The 8V19N492 is a fully integrated FemtoClock NG jitter
attenuator and clock synthesizer designed as a high-performance
clock solution for conditioning and frequency/phase management
of wireless base station radio equipment boards. The device is
optimized to deliver excellent phase noise performance as
required in GSM, WCDMA, LTE, and LTE-A radio board
implementations. The device supports JESD204B subclass 0 and
1 clocks.
▪ High-performance clock RF-PLL with support for JESD204B
▪ Optimized for low phase noise: -150dBc/Hz (800kHz offset;
245.76MHz clock)
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A two-stage PLL architecture supports both jitter attenuation and
frequency multiplication. The first stage PLL is the jitter attenuator
and uses an external VCXO for best possible phase noise
characteristics. The second stage PLL locks on the VCXO-PLL
output signal and synthesizes the target frequency.
• One clock channel with two outputs
• One VCXO output
The device supports the clock generation of high-frequency clocks
from the selected VCO and low-frequency synchronization signals
(SYSREF). SYSREF signals are internally synchronized to the
clock signals. Delay functions exist for achieving alignment and
controlled phase delay between system reference and clock
signals and to align/delay individual output signals. The four
redundant inputs are monitored for activity. Four selectable clock
switching modes are provided to handle clock input failure
scenarios. Auto-lock, individually programmable output frequency
dividers, and phase adjustment capabilities are added for
flexibility.
▪ Configurable integer clock frequency dividers
▪ Supported clock output frequencies include: 2949.12, 1474.56,
983.04, 491.52, 245.76, and 122.88MHz
▪ Low-power LVPECL/LVDS outputs support configurable signal
amplitude, DC and AC coupling and LVPECL, LVDS line
terminations techniques
▪ Phase delay circuits
• Clock phase delay with 256 steps of 339ps and a range of
0 to 86.466ns
• Individual SYSREF phase delay with 8 steps of 169ps
• Additional individual SYSREF fine phase delay with 25ps
The device is configured through a three-wire SPI interface and
reports lock and signal loss status in internal registers and via a
lock detect (LOCK) output. Internal status bit changes can also be
reported via the nINT output. The 8V19N492 is ideal for driving
converter circuits in wireless infrastructure, radar/imaging, and
instrumentation/medical applications. The device is a member of
the high-performance clock family from Renesas.
steps
• Global SYSREF signal delay with 256 steps of 339ps and a
range of 0 to 86.466 ns
▪ Redundant input clock architecture with two inputs and
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Input activity monitoring
Manual and automatic, fault-triggered clock selection modes
Priority controlled clock selection
Digital holdover and hitless switching
Differential inputs accept LVDS and LVPECL signals
▪ SYSREF generation modes include internal and external
trigger mode for JESD204B
Typical Applications
▪ Wireless infrastructure applications: GSM, WCDMA, LTE,
and LTE-A
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Ideal clock driver for jitter-sensitive ADC and DAC circuits
Low phase noise clock generation
Ethernet line cards
Radar and imaging
Instrumentation and medical
©2020 Renesas Electronics Corporation
Integrated phase noise of 80fs RMS typical (12k-20MHz).
Dual-PLL architecture
1st-PLL stage with external VCXO for clock jitter attenuation
2nd-PLL with internal FemtoClockNG PLL: 2949.12MHz
Six output channels with a total of 16 outputs, organized in:
• Four JESD204B channels (device clock and SYSREF
output) with two, four and five outputs
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1
Supply voltage: 3.3V
SPI and control I/O voltage: 1.8V/3.3V (Selectable)
Package: 10 x 10 mm 88-VFQFPN
Temperature range: -40°C to +105°C (Case)
November 5, 2020
8V19N492 Datasheet
Block Diagram
Figure 1. Block Diagram (fVCO = 2949.12MHz)
VCXO-PLL
Loop Filter
CLK_0
nCLK_0
CLK_1
nCLK_1
QCLK_V
nQCLK_V
R0
Clock
Monitor
and
Selector
C1
÷PV
C0
PFD
CP
BYPV
OSC
LFV
÷PF
VDD_LCF
FDF
nOSC
÷MV0
x2
fVCXO
CR
PFD
CP
CR
fVCO
FemtoClockNG
ICPF
LFF
BYPF
÷MF
C2
÷MV1
Femto ClockNG
PLL Loo p Fil ter
C3
R1
Holdover
LFFR
ΦCLK_A
÷NS
ΦREF_S
2
ΦREF_A0
SYSREF
Generator
EXT_SYS
÷NA
MUX_A0
ΦREF_A1
ΦREF_A2
ΦCLK_B
MUX_A1
Channel A
÷NB
2
ΦREF_B0
ΦREF_B1
ΦCLK_C
MUX_A2
MUX_B0
Channel B
MUX_B1
QCLK_A[1:0]
nQCLK_A[1:0]
QREF_A0
nQREF_A0
QREF_A1
nQREF_A1
QREF_A2
nQREF_A2
QCLK_B[1:0]
nQCLK_B[1:0]
QREF_B0
nQREF_B0
QREF_B1
nQREF_B1
QCLK_C
nQCLK_C
÷NC
QREF_C
nQREF_C
ΦREF_C
MUX_C
Channel C
ΦCLK_D
ΦREF_D
ΦCLK_E
MUX_D
÷NE
QCLK_E0
nQCLK_E0
QCLK_E1
nQCLK_E1
SPI
nINT
SCLK
nCS
QREF_D
nQREF_D
Channel D
Channel E
SDAT
QCLK_D
nQCLK_D
÷ND
Register
File
LOCK
SELSV
©2020 Renesas Electronics Corporation
2
November 5, 2020
8V19N492 Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Phase-Locked Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Frequency Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VCXO-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FemtoClockNG PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Channel Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Redundant Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Monitoring and LOS of Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input Re-Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Holdover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hold-off Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revertive Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Short-Term Holdover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Automatic with Holdover (nM/A[1:0] = 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VCXO-PLL Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FemtoClockNG Loss-of-Lock (LOLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Channel, Output, and JESD204B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output Phase Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Configuration for JESD204B Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Synchronizing SYSREF and Clock Output Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SYSREF Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Internal SYSREF Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External SYSREF Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
QCLK to QREF (SYSREF) Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Deterministic Phase Relationship and Phase Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status Conditions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device Startup, Reset, and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Recommended Configuration Sequence (In Order): . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Changing Frequency Dividers and Phase Delay Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Channel and Clock Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
QREF Output State Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PLL Frequency Divider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
VCXO-PLL Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Input Selection Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SYSREF Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
©2020 Renesas Electronics Corporation
3
November 5, 2020
8V19N492 Datasheet
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Phase Noise Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Termination for QCLK_y, QREF_r LVPECL Outputs (STYLE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Exposed Pad Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Application Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marking Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
©2020 Renesas Electronics Corporation
4
47
50
51
52
52
56
63
67
67
67
68
68
68
69
69
70
72
73
73
74
74
November 5, 2020
8V19N492 Datasheet
Pin Assignments
VDD_SPI
EXT_SYS
nCS
SCLK
SELSV
SDAT
nINT
LOCK
VDD_QCLKV
QCLK_V
nQCLK_V
OSC
nOSC
VDD_QCLKV
VDD_CPV
LFV
RES_CAL
CLK_1
nCLK_1
CLK_0
nCLK_0
VDD_INP
Figure 2. Pinout for 10 x 10 mm, 88-VFQFPN Package with Exposed Pad (Top View)
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
VDD_QREFB0
1
66
VDD_QREFA2
QREF_B0
2
65
QREF_A2
nQREF_B0
3
64
nQREF_A2
QREF_B1
4
63
VDD_QREFA2
nQREF_B1
5
62
VDD_QCLKA
VDD_QREFB1
6
61
QCLK_A1
VDD_QCLKB
7
60
nQCLK_A1
QCLK_B0
8
59
QCLK_A0
nQCLK_B0
9
58
nQCLK_A0
QCLK_B1
10
57
VDD_QCLKA
nQCLK_B1
11
56
VDD_QREFA1
VDD_QCLKB
12
55
QREF_A1
DNU
13
54
nQREF_A1
VDD_QREFC
14
53
QREF_A0
QREF_C
15
52
nQREF_A0
nQREF_C
16
51
VDD_QREFA0
VDD_QREFC
17
50
VDD_QCLKE
DNU
18
49
QCLK_E1
VDD_QCLKC
19
48
nQCLK_E1
QCLKC
20
47
QCLK_E0
nQCLK_C
21
46
nQCLK_E0
VDD_QCLKC
22
45
VDD_QCLKE
QREF_D
nQREF_D
VDD_QREFD
QCLK_D
nQCLK_D
VDD_QCLKD
VDD_SYNC
VDD_LCV1
DNU
CBIAS
©2020 Renesas Electronics Corporation
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34
35
36
37
38
39
40
41
42
43
44
ICPF
33
VDD_CPF
32
DNU
31
DNU
30
VDD_LCF
29
VDD_LCF
28
LFF
27
LFFR
26
CLDO
25
CR
24
VDD_LCV2
23
DNU
Exposed Pad
(GND)
November 5, 2020
8V19N492 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
[a]
Type[b]
Pin
Name
69
CLK_0
68
nCLK_0
71
CLK_1
70
nCLK_1
59,
58
QCLK_A0,
nQCLK_A0
Output
Differential clock output A0 (Channel A). Configurable LVPECL/LVDS style and
amplitude.
61,
60
QCLK_A1,
nQCLK_A1
Output
Differential clock output A1 (Channel A). Configurable LVPECL/LVDS style and
amplitude.
53,
52
QREF_A0,
nQREF_A0
Output
Differential SYSREF/clock output REF_A0 (Channel A). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
55,
54
QREF_A1,
nQREF_A1
Output
Differential SYSREF/clock output REF_A1 (Channel A). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
65,
64
QREF_A2,
nQREF_A2
Output
Differential SYSREF/clock output REF_A2 (Channel A). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
8,
9
QCLK_B0,
nQCLK_B0
Output
Differential clock output B0 (Channel B). Configurable LVPECL/LVDS style and
amplitude.
10,
11
QCLK_B1,
nQCLK_B1
Output
Differential clock output B1 (Channel B). Configurable LVPECL/LVDS style and
amplitude.
2,
3
QREF_B0,
nQREF_B0
Output
Differential SYSREF/clock output REF_B0 (Channel B). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
4,
5
QREF_B1,
nQREF_B1
Output
Differential SYSREF/clock output REF_B1 (Channel B). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
20,
21
QCLK_C,
nQCLK_C
Output
Differential clock output C (Channel C). Configurable LVPECL/LVDS style and
amplitude.
15,
16
QREF_C,
nQREF_C
Output
Differential SYSREF/clock output REF_C (Channel C). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
27,
28
QCLK_D,
nQCLK_D
Output
Differential clock output D (Channel D). Configurable LVPECL/LVDS style and
amplitude.
24,
25
QREF_D,
nQREF_D
Output
Differential SYSREF/clock output REF_D (Channel D). LVDS style for SYSREF
operation, configurable LVPECL/LVDS style and amplitude for clock operation.
47,
46
QCLK_E0,
nQCLK_E0
Output
Differential clock output E0. Configurable LVPECL/LVDS style and amplitude.
49,
48
QCLK_E1,
nQCLK_E1
Output
Differential clock output E1. Configurable LVPECL/LVDS style and amplitude.
79,
78
QCLK_V,
nQCLK_V
Output
Differential VCXO-PLL clock outputs. Configurable LVPECL/LVDS style and
amplitude.
82
nINT
Output
Status output pin for signaling internal changed conditions. 1.8V LVCMOS interface
levels.
81
LOCK
Output
PLL lock detect status output for both PLLs. 1.8V LVCMOS interface levels.
Input
Input
©2020 Renesas Electronics Corporation
Description
PD
PD/PU
PD
PD/PU
Device clock 0 non-inverting and inverting differential clock input. Inverting input is
biased to VDD_V/2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
Device clock 1 non-inverting and inverting differential clock input. Inverting input is
biased to VDD_V/2 by default when left floating. Compatible with LVPECL, LVDS and
LVCMOS signals.
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8V19N492 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Type[b]
Pin
Name
87
EXT_SYS
Input
PD
External SYSREF pulse trigger input. 1.8V LVCMOS interface levels.
83
SDAT
Input/
Output
PU
Serial Control Port SPI Mode Clock Input and Output. Selectable 1.8V/3.3V
LVCMOS interface levels. 3.3V tolerant when set to 1.8V and set to input.
85
SCLK
Input
PD
Serial Control Port SPI Mode Clock Input. Selectable 1.8V/3.3V LVCMOS interface
levels. 3.3V tolerant when set to 1.8V.
86
nCS
Input
PU
Serial Control Port SPI Chip Select Input. Selectable 1.8V/3.3V LVCMOS interface
levels. 3.3V tolerant when set to 1.8V.
84
SELSV
Input
PD
SPI interface voltage select. 1.8V LVCMOS interface levels (see Table 25 for SPI
interface selection).
35
CR
Analog
Internal VCO regulator bypass capacitor. Use a 1.0μF capacitor between the CR
and VDD_LCF pins.
33
CBIAS
Analog
Internal bias circuit for VCO. Connect a 4.7µF capacitor to GND.
36
CLDO
Analog
Internal LDO bypass for VCO. Connect a 10µF capacitor to GND.
73
LFV
Output
VCXO-PLL charge pump output. Connect to the loop filter for the external VCXO.
77
OSC
76
nOSC
44
ICPF
Analog
Connect to LFF pin (38) and external loop filter.
38
LFF
Output
Loop filter/charge pump output for the FemtoClockNG NG PLL. Connect to the
external loop filter.
37
LFFR
Analog
Ground return path pin for the VCO loop filter.
72
RES_CAL
Analog
Connect a 2.8 k (1%) resistor to GND for output current calibration.
13, 18, 23,
32, 41, 42
DNU
57, 62
VDD_QCLKA
Power
Positive supply voltage (3.3V) for the QCLK_A[1:0] outputs.
51
VDD_QREFA0
Power
Positive supply voltage (3.3V) for the QREF_A0 outputs.
56
VDD_QREFA1
Power
Positive supply voltage (3.3V) for the QREF_A1 outputs.
63, 66
VDD_QREFA2
Power
Positive supply voltage (3.3V) for the QREF_A2 outputs.
7, 12
VDD_QCLKB
Power
Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.
1
VDD_QREFB0
Power
Positive supply voltage (3.3V) for the QREF_B0 output.
6
VDD_QREFB1
Power
Positive supply voltage (3.3V) for the QREF_B1 output.
19, 22
VDD_QCLKC
Power
Positive supply voltage (3.3V) for the QCLK_C outputs.
14, 17
VDD_QREFC
Power
Positive supply voltage (3.3V) for the QREF_C outputs.
29
VDD_QCLKD
Power
Positive supply voltage (3.3V) for the QCLK_D outputs.
26
VDD_QREFD
Power
Positive supply voltage (3.3V) for the QREF_D outputs.
45, 50
VDD_QCLKE
Power
Positive supply voltage (3.3V) for the QCLK_E[1:0] outputs.
88
VDD_SPI
Power
Positive supply voltage (3.3V) for the SPI interface.
67
VDD_INP
Power
Positive supply voltage (3.3V) for the differential inputs (CLK0 to CLK1).
Input
Description
PD
PD/PU
VCXO non-inverting and inverting differential clock input. Inverting input is biased to
VDD_V /2 by default when left floating. Compatible with LVPECL, LVDS and LVCMOS
signals.
Do not use, do not connect.
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Table 1. Pin Descriptions (Cont.)[a]
Type[b]
Pin
Name
Description
31
VDD_LCV1
Power
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
34
VDD_LCV2
Power
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
39,40
VDD_LCF
Power
Positive supply voltage (3.3V) for the internal oscillator of the FemtoClockNG PLL.
43
VDD_CPF
Power
Positive supply voltage (3.3V) for internal FemtoClockNG circuits.
75, 80
VDD_QCLKV
Power
Positive supply voltage (3.3V) for OSC, nOSC input and QCLKV, nQCLKV output.
74
VDD_CPV
Power
Positive supply voltage (3.3V) for internal VCXO_PLL circuits.
30
VDD_SYNC
Power
Positive supply voltage (3.3V).
Exposed
Pad (EP)
GND
Power
Ground supply voltage (GND) and ground return path. Connect to board GND (0V).
[a] See Section “Application Information” on page 67 for essential information on power supply filtering.
[b] PU (pull-up) and PD (pull-down) indicate internal input resistors (see Table 46 for values).
Principles of Operation
Overview
The 8V19N492 generates low-phase noise, synchronized clock and SYSREF output signals locked to an input reference frequency. The
device contains two PLLs with configurable frequency dividers. The first PLL (VCXO-PLL, suffix V) uses an external VCXO as the
oscillator and provides jitter attenuation. The external loop filter is used to set the VCXO-PLL bandwidth frequency in conjunction with
internal parameters. The second, low-phase noise PLL (FemtoClock NG, suffix F) multiplies the VCXO-PL1L frequency to 2949.12MHz.
The FemtoClock NG PLL is completely internal and provides a central timing reference point for all output signals. From this point, fully
synchronous dividers generate the output frequencies and the internal timing references for JESD204B support.
The device supports the generation of SYSREF pulses synchronous to the clock signals. There are five channels consisting of clock
and/or SYSREF outputs. The clock outputs are configurable with support for LVPECL or LVDS formats and a variable output amplitude.
Clock and SYSREF offer adjustable phase delay functionality. Individual outputs and channels and unused circuit blocks support
powered-down states for operating at lower power consumption. The register map, accessible through SPI interface with read-back
capability controls the main device settings and delivers device status information. For redundancy purpose, there are two selectable
reference frequency inputs and a configurable switch logic with priority-controlled auto-selection and holdover support.
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Phase-Locked Loop Operation
Frequency Generation
Table 2 displays the available frequency dividers for clock generation. The dividers must be set by the user to match input, VCXO and
VCO frequency, and to achieve frequency and phase lock on both PLLs. The frequency of the external VCXO is selected by the user; the
internal VCO frequency is set to 2949.12MHz. Example divider configurations for typical wireless infrastructure applications are shown in
Table 3.
Table 2. PLL Operation and Divider Values
Operation for fVCO = 2949.12MHz
Divider
Range
VCXO-PLL
Pre-Divider P V
÷1…÷4095:(12 bit)
VCXO-PLL
Feedback Divider
MV0
÷1…÷4095:
(12 bit)
PLL Feedback
Divider[a] MV1
÷4…÷511: (9 bit)
FemtoClock NG
Pre-Divider P F
÷1…÷63: (6 bit)
FemtoClock NG
Feedback Dividers
MF
÷8 …÷511: (9 bit)
Jitter Attenuation, Dual-PLL
with Deterministic
Input-to-Output Delay
(BYPV = 0, BYPF = 1)
Input clock frequency:
Jitter Attenuation, Dual-PLL
(BYPV = 0, BYPF = 0)
Input clock frequency:
MF
f VCXO
f CLK = P V -------------------- -----------------------------------PF
M V0 M V1
PV
f CLK = f VCXO -------------M V0
MV1 setting is not applicable
to PLL operation.
VCXO frequency:
PF
f VCXO = f VCO --------MF
Frequency Synthesis
(VCXO-PLL Bypassed,
BYPV = 1)
Input clock frequency:
PV PF
f CLK = f VCO ----------------------MF
MV0 and MV1 settings are not
applicable to the PLL
operation.
PF: Set PF to 0.5 in above
equation if the frequency
doubler is engaged by setting
FDF = 1.
PF: Set PF to 0.5 in above equation if the frequency doubler is
engaged by setting FDF = 1.
Output frequency:
Output Divider Nx
(x = A, B, C, D, E)
÷1…÷160
SYSREF Divider[b]
NS
÷16…÷5120:
{2, 4} {2, 4, 8, 16}
{2, 4, 8, 16} {2,
3, 4, 5}
f VCO
f OUT = -------------NX
SYSREF frequency/rate:
f VCO
f SYSREF = -------------NS
[a] For input monitoring, configure MV1 as described in Monitoring and LOS of Input Signal.
[b] For SYSREF operation, configure SYNC[6:0] as described in Status Conditions and Interrupts.
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
VCXO-PLL
The prescaler PV and the VCXO-PLLs feedback divider MV0 and MV1 require configuration to match the input frequency to the
VCXO-frequency. The BYPF setting allows to route the VCXO-PLLs feedback path through the MV0 divider. Alternatively, the feedback
path is routed through the second PLL and both the MV0 and MV1 feedback divider. MV0 has a divider value range of 12 bit; M V1 has 9 bit.
The feedback path through the second PLL, in combination with the divider setting PF=÷1, is the preferred setting for achieving
deterministic delay from the clock input to the outputs. Multiple divider settings are available to enable support for input frequencies of
e.g. 245.76, 122.88, 61.44 and 30.72MHz and the VCXO-frequencies of 122.88MHz, 61.44, 38.4, 30.72 and 245.76 MHz. In addition, the
range of available input and feedback dividers allows to adjust the phase detector frequency independent on the input and VCXO
frequencies. In general, the phase detector may be set into the range from 120kHz to the input reference frequency. The VCXO-PLL
charge pump current is controllable via a register and can be set in 50µA steps from 50µA to 1.6mA. The VCXO-PLL may be bypassed:
the FemtoClockNG PLL locks to the pre-divider input frequency.
Table 3. Example Configurations for fVCXO = 122.88MHz[a]
Input Frequency
(MHz)
245.76
122.88
VCXO-PLL Divider Settings
PV
MV0
fPFD
(MHz)
2
1
122.88
32
16
7.68
256
128
0.96
2048
1024
0.12
1
1
122.88
16
16
7.68
128
128
0.96
1024
1024
0.12
[a] BYPF=0
Table 4. Example Configurations for fVCXO = 38.4MHz[a]
Input Frequency
(MHz)
245.76
122.88
VCXO- PLL Divider Settings
PV
MV0
fPFD
(MHz)
32
5
7.68
128
20
1.92
512
80
0.48
2048
320
0.12
16
5
7.68
64
20
1.92
256
80
0.48
1024
320
0.12
[a] BYPF=0
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Table 5. VCXO-PLL Bypass Settings
BYPV
Operation
0
VCXO-PLL operation.
1
VCXO-PLL bypassed and disabled. The reference clock for the FemtoClockNG PLL is the input clock divided by the
pre-divider PV. The input clock selection must be set to manual by the user. Clock switching and holdover are not
defined. Device will not attenuate input jitter. No external VCXO component and loop filter required.
Table 6. PLL Feedback Path Settings
Operation[a]
BYPF
0
VCXO-PLL feedback path through the MV0 divider. FemtoClockNG feedback path uses the MF divider.
1
VCXO-PLL feedback path through the M V1 MV0 dividers. FemtoClockNG feedback path uses the MF divider.
Preferred setting for achieving deterministic delay from input to the outputs.
[a] Regardless of the selected internal feedback path, the MV1 divider should be set to match its internal output frequency to the input reference
frequency: the MV1 output signal is the internal reference for input loss-of-signal detect.
FemtoClockNG PLL
This PLL locks to the output signal of the VCXO-PLL (BYPV=0). It requires configuration of the frequency doubler FDF or the pre-divider
PF and the feedback divider MF to match the VCXO-PLL frequency to the VCO frequency of 2949.12MHz. This PLL is internally
configured to high-bandwidth. Best phase noise is typically achieved by engaging the internal frequency doubler (FDF= 1, x2). If
engaged, the signal from the first PLL stage is doubled in frequency, increasing the phase detector frequency of the FemtoClockNG PLL.
Enabling the frequency doubler disables the frequency pre-divider PF. If the frequency doubler is not used (FDF=0), the PF pre-divider
has to be configured. Typically PF is set to ÷1 to keep the phase detector frequency as high as possible. Set PF to other divider values to
achieve specific frequency ratios (1 to 19.2, 1 to 76.8, etc.) between first and second PLL stage.
Table 7. Frequency Doubler
FDF
Operation
0
Frequency doubler off. PF divides clock signal from VCXO-PLL or input (in bypass)
1
Frequency doubler on (x2). Signal from VCXO-PLL or input (in bypass) is doubled in frequency. PF divider has no
effect.
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Table 8. Example PLL Configurations
FemtoClock NG Divider Settings
VCXO-Frequency
(MHz)
FDF
122.88
x2
122.88
–
PF
–
1
MF
Nx[a]
Output
Frequency
(MHz)
10
1
2
3
4
6
8
12
16
2949.12
1474.56
983.04
737.28
491.52
368.64
245.76
184.32
20
1
2
3
4
6
8
12
16
2949.12
1474.56
983.04
737.28
491.52
368.64
245.76
184.32
[a] x = A to E
Channel Frequency Divider
The device supports five independent channels A to E, each of them has an channel frequency divider Nx (x = A to E) that divides the
VCO frequency to the output frequency. Each divider be individually set to a value in the range of ÷1 to ÷160. See Table 9 for typical
divider values and Table 28 for the complete set of supported divider values
Table 9. Integer Frequency Divider Settings
Output Clock Frequency (MHz)
Channel Divider Nx[a]
fVCO = 2949.12 (MHz)
÷1
2949.12
÷2
1474.56
÷3
983.04
÷4
737.28
÷6
491.52
÷8
368.64
÷12
245.76
÷16
184.32
÷24
122.88
÷30
98.304
÷32
92.16
÷36
81.92
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Table 9. Integer Frequency Divider Settings (Cont.)
Output Clock Frequency (MHz)
Channel Divider Nx[a]
fVCO = 2949.12 (MHz)
÷48
61.44
÷60
49.152
÷64
46.08
÷72
40.96
÷96
30.72
÷120
24.576
÷128
23.04
[a] x = A to E
Redundant Inputs
The two inputs are compatible with LVDS, LVPECL signal formats and also support single-ended signals (LVCMOS, see Section
“Application Information” on page 67 for applicable input interface circuits).
Monitoring and LOS of Input Signal
The two inputs of the device are individually and permanently monitored for activity. Inactivity is defined by a static input signal.
he clock input monitors compare the device input frequency (fCLK) to the frequency of the VCO divided by MV1 (regardless of the internal
feedback path using or not using MV1). A clock input is declared invalid with the corresponding LOS (Loss-of-input-signal) indicator bit set
after three consecutive missing clock edges. For correct operation of the LOS detect circuit, MV1 must be powered-on by setting PD_MV1
= 0. The MV1 divider must be set so that the LOS detect reference frequency matches the input frequency. For instance, if the input
frequency is 245.76MHz, MV1 should be set to ÷12: The VCO frequency of 2949.12MHz divided by 12 equals the input frequency of
245.76MHz. For an input frequency of 122.88MHz, set MV1 to ÷24. Failure to set MV1 to match the input frequency will result in added
latency to the LOS circuit (if fVCO ÷ MV1 < fCLK) or false LOS indication (if fVCO ÷ MV1 > fCLK). The minimum frequency that the circuit can
monitor is fVCO / MV1(MAX) = 5.77MHz. In applications with a lower input frequency than 5.77MHz, disable the monitor to trigger the
status flags by setting BLOCK_LOR=1.
Input Re-Validation
A clock input is declared valid and the corresponding LOS bit is reset after the clock input signal returned for user-configurable number of
consecutive input periods. This re-validation of the selected input clock is controlled by the CNTV setting (verification pulse counter).
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Clock Selection
The device supports multiple input selection modes: manual, short-term holdover and two automatic switch modes.
Table 10. Clock Selection Settings
Mode
Manual
nM/A=00
Automatic
nM/A=01
Short-term Holdover
nM/A=10
Automatic with
holdover
nM/A=11
Description
Application
Input selection follows user-configuration of SEL[1:0]. Selection is never changed by the
internal state machine. A failing reference clock will cause a LOS event and the PLL will
unlock if the failing clock is selected. Re-validation of the selected input clock will result in the
PLL to re-lock on that input clock.
Startup and external
selection control
Input selection follows LOS status by user preset input switch priorities. A failing input clock
will cause a LOS event for that clock input. If the selected clock has a LOS event, the device
will immediately initiate a clock failover switch. The switch target is determined by pre-set
input priorities.
No valid clock scenario:
If no valid input clocks exist, the device will not attempt to switch and will not enter the
holdover state. The PLL is not locked. Re-validation of any input clock that is not the selected
clock will result in the PLL to attempt to lock on that input clock.
See “Revertive Switching”
Multiple inputs with
qualified clock
signals
Input selection follows user-configuration of SEL[1:0]. Selection is never changed by the
internal state machine. A failing reference clock will cause a LOS event. If the selected
reference fails, the device will enter holdover immediately. Re-validation of the selected input
clock is controlled by the CNTV setting. A successful re-validation will result in the PLL to
re-lock on that input clock.
See “Short-Term Holdover”
Single reference
Input selection follows LOS status by user preset input priorities. Each failing input clock will
cause a LOS event for that clock input. If the selected clock detects a LOS event, the device
will go into holdover and the hold-off down-counter (CNTH) starts. The device initiates a clock
failover switch after expiration of the hold-off counter. The switch target is determined by the
preset input priorities.
No valid clock scenario:
If no valid input clocks exist, the device will not attempt to switch and will remain in the
holdover state. Re-validation of any input clock will result in the PLL to attempt to lock on that
input clock.
See “Automatic with Holdover (nM/A[1:0] = 11)” and See “Revertive Switching”
Multiple inputs
Holdover
In holdover state, the output frequency and phase is derived from an internal, digital value based on previous frequency and phase
information. Holdover characteristics are defined in Table 51.
Input Priorities
Configurable settings encompass four selectable priorities with the range 0 (lowest priority) to 3 (highest priority). A user may change the
input priorities at any time. In the automatic switch modes, input priority changes may cause immediate input selection changes.
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Hold-off Counter
A configurable down-counter applicable to the “Automatic with holdover” selection mode. The purpose of this counter is a deferred,
user-configurable, input switch after a LOS event. The counter expires when a zero-transition occurs; this triggers a new reference clock
selection. The counter is clocked by the frequency-divided VCXO-PLL signal. The CNTR setting determines the hold-off counter
frequency divider and the CNTH setting the start value of the hold-off counter. For instance, set CNTR to a value of ÷131072 to achieve
937.5 Hz (or a period of 1.066 ms at fVCXO=122.88MHz): the 8-bit CNTH counter is clocked by 937.5Hz and the user-configurable
hold-off period range is 0ms (CNTR=0x00) to 272ms (CNTR=0xFF). After the counter expires, it reloads automatically from the CNTH
SPI register. After the LOS status bit (LS_CLK_n) for the corresponding input CLK_n has been cleared by the user, the input is enabled
for generating a new LOS event.
The CNTR counter is only clocked if the device is configured in the clock selection mode “Automatic with holdover” AND the selected
reference clock experiences a LOS event. Otherwise, the counter is automatically disabled (not clocked).
Revertive Switching
Revertive switching: is only applicable to the two automatic switch modes shown in Table 10. Revertive switching enabled: Re-validation
of any non-selected input clock(s) will cause a new input selection according to the user-preset input priorities (revertive switch). An input
switch is only done if the re-validated input has a higher priority than the currently selected reference clock.
Revertive switching disabled: Re-validation of a non-selected input clock has no impact on the clock selection. Default setting is revertive
switching disabled.
Short-Term Holdover
If an LOS event is detected on the reference clock designated by the SEL[1:0] bits:
▪ Holdover begins immediately
▪ ST_REF, LS_REF go low immediately
▪ No transitions will occur of the active REF clock; ST_SEL[1:0] does not change
▪ The hold-off countdown is not active
When the designated reference clock resumes and has met the programmed validation count of consecutive rising edges:
▪ Holdover turns off
▪ ST_SEL[1:0] does not change
▪ ST_REF returns to 1
LS_REF can be cleared by an SPI write of 1 to that register
Automatic with Holdover (nM/A[1:0] = 11)
If a LOS event is detected on the active reference clock:
▪ Holdover begins immediately
▪ Corresponding ST_REF and LS_REF go low immediately
▪ Hold-off countdown begins immediately.
During this time, all clocks continue to be monitored and their respective ST_CLK, LS_CLK flags are active. LOS events will be indicated
on ST_CLK, LS_CLK when they occur.
If the active reference clock (or any CLK) resumes and is validated during the hold-off countdown:
▪ Its ST_CLK status flag will return high and the LS_CLK is available to be cleared by an SPI write of 1 to that register bit.
▪ No transitions will occur of the active REF clock; ST_SEL[1:0] does not change and the ST_REF, LS_REF remain low even if active
REF clock has been validated and its ST_CLK status bit returns high
▪ Revertive bit has no effect during this time (whether 0 or 1)
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When the hold-off countdown reaches zero:
▪ If the active reference has resumed and has been validated during the countdown, it will maintain being the active reference clock
• ST_SEL1:0 does not change
• ST_REF returns to 1
• LS_REF can be cleared by an SPI write of 1 to that register
• Holdover turns off and the VCXO-PLL attempts to lock to the active reference clock
▪ If the active reference has not resumed, but another (sorted by next priority) clock input CLK_n is validated, then
• ST_SEL1:0 changes to the new active reference
• ST_REF returns to 1
• LS_REF can be cleared by an SPI write of 1 to that register
• Holdover turns off
▪ If there is no validated CLK:
• ST_SEL1:0 does not change
• ST_REF remains low
• LS_REF cannot be cleared by an SPI write of 1 to that register
• Holdover remains active
Revertive capability returns if REVS = 1.
VCXO-PLL Lock Detect
The VCXO-PLL lock detect circuit uses the signal phase difference at the phase detector as loss-of-lock criteria. Loss-of-lock is reported
if the actual phase difference is larger than a configurable phase detector window set by the MV0[2:0] and PV[2:0] configuration bits.
A loss-of-lock state is reported through the nST_LOLV and nLS_LOLV status bit, see Table 22.
Loss-of-Lock Window Description
The selected clock input signal is the reference signal (CLK) for lock detection. The rising edge of CLK defines the reference point t0.
PV configures the start of the lock window tB (which occurs before t0) and MV0 configures the end of the window tE (which occurs after
t0). The width of the lock window is defined by tE - tB. The VCXO-PLL declares lock when the rising edge of the feedback signal (FB) is
within this window, otherwise the PLL reports loss-of-lock.
Figure 3. Lock Detect Window
Input
CLK
FB
÷PV
PFD
CP
LFV
VCXO
÷MV0
CLK
FB
BYPF
VCXO
tB
0
1
÷MV1
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VCO
t0
tE
Lock detected if FB in this window
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Table 11. tB and tE Calculation
Operation
Jitter Attenuation, Dual-PLL with
deterministic Input-to-Output Delay
(BYPV = 0, BYPF = 1)
Jitter Attenuation, Dual-PLL
(BYPV = 0, BYPF = 0)
PV
2
–1
t B = – -------------------------f CLK
tB
MV0
MV0
2
– 1 M V1
t E = -------------------------------------------------------f VCO
tE
2
–1
t E = ------------------------------f VCXO
Figure 3 shows that PV configures the start and MV0 the end of the window in integer multiples of PLL input and feedback periods.
Both PV and MV0 use 3 configuration bits with valid settings from 010 to 111 (2 to 7, decimal). This range allows configuring both t S
and tE from 3 to 127 periods of the input signal (TIN) and the feedback signal (TFB), respectively, is implied.
Loss-of-Lock Window Configuration Example
With given PV, MV0 and MV1 divider values, select the corresponding PV and MV0 settings from Table 12 and apply the PV and MV0
values to the PV[1:0] and MV0[1:0] registers. Table 11 shows the lock window calculation formulas. For instance, if an input
frequency of 245.76MHz and a PV divider of 128 is desired, set PV[1:0] to a binary value of 100 (decimal 4). This results in tB =
-61.035ns (15 periods of 4.069ns). With a VCXO-PLL (BYPF=0) and a VCXO frequency of 122.88MHz and MV0=64, select 011 (decimal
3) resulting in tE = 56.96ns (7 periods of 8.138 ns) and an overall lock detect window of tE - tB = 56.96ns + 61.035ns = 118.001ns. The
user may select a smaller lock detect window. For instance, a PV divider of 128 allows to set PV[1:0] to 010, 011 or 100 (decimal 2 to 4).
Correspondingly, a MV0 divider of 64 allows MV0[1:0] settings from 010 to 011 (decimal 2 to 3). With smaller settings, the lock detect
window size is reduced exponentially.
PV[1:0]=000 will set tB to 0.5*TREF and PV[1:0]=001 will set tB to 1.5*TREF.
MV0[1:0]=000 will set tE to 0.5*TREF and MV0[1:0]=001 will set tE to 1.5*TREF.
Table 12. Recommended Lock Detector Phase Window Settings
PV Divider Value
PV[1:0] Setting
MV0 Divider Value
MV0[1:0] Setting
1 - 31
N/A
1 - 31
N/A
32 - 63
010
32 - 63
010
64-127
≤011
64-127
≤011
128-255
≤100
128-255
≤100
256-511
≤101
256-511
≤101
512-1023
≤110
512-1023
≤110
1024 and higher
≤111
1024 and higher
≤111
FemtoClockNG Loss-of-Lock (LOLF)
FemtoClockNG-PLL loss of lock is signaled through the nST_LOLF (momentary) and nLS_LOLF (sticky, resettable) status bits and can
reported as hardware signal on the LOCK output as well as an interrupt signal on the nINT output.
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Channel, Output, and JESD204B Logic
Channel
Each of the four channels A to D consists of one to two clock and associated one to three SYSREF outputs. Each SYSREF output in a
channel can be individually configured to generate JESD204B (SYSREF) signals or copy the clock signal of that channel. The fifth
channel (E) consists of two clock outputs without SYSREF support in that channel.
If JESD204B/SYSREF operation is assigned to a QREF output, the channel logic controls the outputs: outputs automatically turn on and
off in a SYSREF sequence. QREF outputs configured to clock operation can individually configure output states.
Table 13. Channel Configuration[a]
MUX
Description
QCLK_y
QREF_r
0
1
Clock configuration
JESD204B
Clock signal
Clock signal
SYSREF/JESD204B
Frequency Divider
QCLK_y and QREF_r: Nx
QCLK_y: Nx
QREF_r: NS (Global to all QREF_r)
Phase Delay
QCLK_y and QREF_r: CLK_x
REF_r settings do not apply
QCLK_y: CLK_x
QREF_r: REF_r
Power Down
Per output
Per channel
Output Enable
Per output
Per output
[a] x = A to E. y = A0, A1, B0, B1, C, D, E0, E1; r = A0, A1, A2, B0, B1, C, D
Differential Outputs
Table 14. Output Features
Output
QCLK_y, QREF_r
(Clock)
QREF_r
(SYSREF)
QOSC
Style
Amplitude[a]
Disable
Power Down
LVPECL
250–1000 mV
4 steps
Yes
Yes
LVDS
LVDS
LVPECL
LVDS
250–1000 mV
4 steps
Controlled by SYSREF[c]
250–750 mV
3 steps
Yes
Yes
Termination
50 to VT
100 differential[b]
100 differentialb
50 to VT
100 differentialb
[a] Amplitudes are measured single-endedly. Differential amplitudes supported are 500, 1000, 1500 and 2000mV
[b] AC coupling and DC coupling supported.
[c] State of SYSREF outputs is controlled by an internal SYSREF state machine.
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Table 15. Individual Clock Output Settings[a]
PD[b]
STYL
E
EN[c]
A[1:0][d]
Output
Power
Termination
State
Amplitude
(mV)
1
X
X
X
Off
100 differential or no termination
Off
X
0
XX
Disable (logic low)
X
00
0
1
01
0
1
1
100 differential (LVDS)
10
11
0
250
XX
Enable
500
750
1000
On
50 to VT (LVPECL)
00
50 to VT = VDD_V - 1.50V (LVPECL)
01
50 to VT = VDD_V - 1.75V (LVPECL)
10
50 to VT = VDD_V - 2.00V (LVPECL)
11
50 to VT = VDD_V - 2.25V (LVPECL)
X
Enable
250
500
750
Enable
1000
[a] Applicable to clock outputs: QCLK_y and QREF_r outputs in clock mode (MUX_r = 0)
[b] Power-down modes are available for the individual channels A-E and the outputs QCLK_y (A0 to E1).
[c] Output enable is supported on each individual QCLK_y and QREF_r output.
[d] Output amplitude control is supported on each individual QCLK_y and QREF_r output.
Table 16. Individual SYSREF Output Settings[a]
PD
STYLE
EN
nBIAS
A[1:0]
Output
Power
Termination
State
Amplitude
(mV)
1
X
X
X
X
Off
100 differential or no termination
Off
X
Disable (logic low)
X
Enable
250
500
750
1000
Line bias[c]
XX
Disable (logic low)
X
Enable
250
500
750
1000
0
0
0
1
X
X
0
1
0
1
1
00
01
10
11
XX
100 differential (LVDS)
On[b]
X
0
00
01
10
11
50 to VT = VDD_V - 1.50V
(LVPECL)
[a] Applicable QREF_r outputs when configured as SYSREF output (MUX_r = 1).
[b] Output amplitude should be set to a 500 mV swing (A[1:0] to 01) by SPI. SYSREF output states are controlled by an internal state machine. An
internal SYSREF event will automatically turn SYSREF outputs on. After the event, outputs are automatically turned off. Setting nBIAS = 1 will
bias powered-off outputs to the LVDS midpoint voltage.
[c] Output (both Q, and nQ) bias the line to the differential signal cross-point voltage. Available if output is AC-coupled and set to LVDS style
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Table 17. QCLK_V (VCXO-PLL) Output Settings
nPD
STYLE
A[1:0]
Output
Power
Termination
Amplitude (mV)
0
X
X
Off
100 differential (LVDS) or no termination
X
1
0
00
On
100 differential (LVDS)
250
01
500
10
11
1
750
00
50 to VT = VDD_V - 1.50V (LVPECL)
01
50 to VT = VDD_V - 1.75V (LVPECL)
10
11
50 to VT = VDD_V - 2.00V (LVPECL)
250
500
750
Table 18. QREF_r Setting for JESD204B Applications
QREF_r Outputs (LVDS)
BIAS_TYPE
nBIAS_r
Initial
During SYSREF event
SYSREF completed
Application
0
0
Static low
(QREF = L, nQREF_r = H)
Start switching for the
number of configured
SYSREF pulses
Released to static low
(QREF = L, nQREF_r = H)
QREF_r DC coupled
1
1
0
Static low (QREF = L, nQREF_r = H)
Static LVDS crosspoint
level (QREF = nQREF_r =
VOS)
1
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Start switching for the
number of configured
SYSREF pulses
Released to static LVDS
crosspoint level (QREF =
nQREF_r = VOS)
QREF_r AC coupled
Static LVDS crosspoint level (QREF = nQREF_r = VOS)
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Output Phase Delay
Output phase delay is independently supported on both clock and SYSREF outputs.
The phase delay on clock outputs ΦCLK_x, SYSREF outputs coarse delay ΦREF_r and global delay ΦREF_S is derived from the internal
VCO frequency of the second PLL (FemtoClock NG PLL). In configurations bypassing the second PLL by setting SRC = 1, the delay unit
is derived from the frequency of the external VCXO: use fVCXO instead of fVCO in Table 19.
Table 19. Delay Circuit Settings
Delay Circuit
Unit
1
--------------- = 339ps
f VCO
Clock[b] CLK_x
Steps
Range (ns)
Alignment[a]
256
0–86.466[c]
Incident rising clock edges are
aligned, independent on the divider
N_x across channels
8
0–1.187[c]
8
0–0.160[d]
256
0–86.466[c]
Coarse delay:
1
------------------- = 169ps
2f VCO
SYSREF REF_r
Fine delay:
0, 25, 50, 75, 85, 110, 135, 160 ps
SYSREF (Global)
REF_S
1
--------------- = 339ps
f VCO
SYSREF rising edge is aligned to the
incident rising clock edge across
channels
Global alignment of SYSREF signals
[a] Default configuration (all delay settings = 0). REF_r coarse delay values are exact, fine delay value vary over PVT by ±20%.
[b] Clock output inversion supported by setting phase delay to 180° setting.
[c] Exact delay value.
[d] ±20% delay variation over PVT.
Configuration for JESD204B Operation
Synchronizing SYSREF and Clock Output Dividers
The SYNC[6:0] divider controls the release of SYSREF pulses at coincident QCLK_y clock edges. For SYSREF operation, set the SYNC
divider value to the least common multiple of the clock divider values Nx (x = A to E). For instance, if NA = NB = ÷2, N C = ND = ÷3,
NE = ÷4, set the SYNC divider to ÷12.
SYSREF Generation
A SYSREF event is the generation of one or more consecutive pulses on the QREF outputs. An event can be triggered by SPI commands
or by a signal-transition on the EXT_SYS input. The number of SYSREF pulses generated is programmable from 1 to 255. The SYSREF
signal can also be programmed to be continuous. The SYSREF pulse rate is configurable to the frequencies shown in Table 20. SYSREF
output pulses are aligned to coincident rising clock edges of the clock outputs QCLK_y. Device settings for phase alignment between
QCLK_y and QREF_r outputs is detailed in the section, QCLK to QREF Phase Alignment. The following SYSREF pulse generation
modes are available and configurable by SPI:
▪ Counted pulse mode – 1 to 255 pulses are generated by the device. SYSREF activity stops automatically after the transmission of the
selected number of pulses and the QREF output powers down.
▪ Continuous mode – The SYSREF signal is a clock signal.
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The generation of SYSREF pulses is configured by SPI commands and is available after the initial setup of output clock divider and
QREF phase delay stages. A SYSREF event will automatically turn on the SYSREF outputs. After the event, SYSREF outputs are
automatically turned off (power-down). SYSREF outputs with the nBIAS bit set high will bias the outputs at the LVDS crosspoint voltage
level (requires BIAS_TYPE = 1).
Table 20. SYSREF Generation[a]
SYSREF Operation (fSYSREF)
SRO
NS
fVCO = 2949.12MHz
Counted pulse mode
(Use the SRPC register to configure the number of generated SYSREF pulses)
0
÷64
46.08
÷96
30.72
÷128
23.04
÷192
15.36
÷256
11.52
÷384
7.68
÷512
5.76
÷768
3.84
÷1024
2.88
÷2048
1.44
÷4096
0.72
÷5120
0.576
Continuous pulse mode
1
÷64
46.08
÷96
30.72
÷128
23.04
÷192
15.36
÷256
11.52
÷384
7.68
÷512
5.76
÷768
3.84
÷1024
2.88
÷2048
1.44
÷4096
0.72
÷5120
0.576
[a] SRO and SRPC are global settings.
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Internal SYSREF Generation
SYSREF generation is set to internal (SRG = 0). The SRO setting defines if SYSREF pulses are counted or continuous and the NS[6:0]
divider sets the frequency. In counted pulse mode, the SRPC register contains the number of pulses to generate. Any number from 1 to
255 pulses may be generated. SYSREF pulses are generated upon completion of the SPI command RS (SYSREF release). Setting RS
activates the SYSREF outputs, loads the number of pulses from the SRPC register and starts the generation of SYSREF pulses
synchronized to the incident edge of the clock signals. After the programmed number of pulses are generated, SYSREF outputs will go
into logic low state or bias the output voltage to the static LVDS crosspoint level (see Table 21 for settings and details). In continuous
mode, SYSREF is a clock signal and the content of the SRPC signal is ignored.
External SYSREF Generation
SYSREF generation is set to external (SRG = 1): SYSREF pulses are generated in response to the detection of a rising edge at the
EXT_SYS input. The EXT_SYS input rising edge releases SYSREF pulses. Both SRO and SRPC register settings apply as in internal
SYSREF generation mode for generating single shot and repetitive SYSREF output signals. Set RS = 1 to prepare for SYSREF
generation; the generation of SYSRE pulses is triggered by a rising edge at EXT_SYS pin.
QCLK to QREF (SYSREF) Phase Alignment
Figure 4 and Table 21 show how to achieve output phase alignment between the QCLK_y clock and the QREF_r SYSREF outputs in
internal SYSREF generation mode (SRG=0). The closest (smallest phase error) output alignment is achieved by setting the clock phase
delay register QCLK_Y to 0x00 (clock), the SYSREF output phase delay register REF_r to 0x01 and the global REF_S delay register to
0x29. With a SYSREF phase delay setting of 0x01 or less, REF_r = 0, the QREF_r output phase is in advance of the QCLK_y phase,
which is applicable in JESD204B application. Phase delay settings and propagation delays are independent on the clock and SYSREF
frequencies, but independent of the SYSREF generation mode (SRG = 0 or SRG = 1). Recommended phase delay setting several device
configurations are shown in Table 21.
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Figure 4. QCLK to QREF Phase Alignment
Output Phase
Alignment
QCLK_y
QCLK_y = 0x00
QCLK_y
QCLK_y = 0x00
QREF_r
REF_r = 0x01
REF_r_F = 1
QREF_r in advance of QCLK_y
QCLK_y
QCLK_y = 0x00
QCLK_y
QCLK_y = 0x00
QREF_r
REF_r = 0x00
REF_r_F = 1
= 169ps
QREF_r
REF_r = 0x00
REF_r_F = 1
= 338ps
Table 21. Recommended Delay Settings for Closest Clock-SYSREF Output Phase Alignment[a]
Divider Configuration
NS=÷384
NA-E=÷3
NA-E = ÷3, ÷6,÷12
NS=÷384
NS=÷384
NA-E = ÷8
CLK_y
REF_r
REF_S
0x00
0x01
0x29
0x00
0x01
0x29
0x00
0x03
0x00
[a] QCLK and QREF outputs are aligned on the incident edge.
Deterministic Phase Relationship and Phase Alignment
Input to output delay is deterministic when the device is configured as dual PLL with the BYPV = 0, BYPF = 1 (PLL feedback path through
MV0 MV1). Refer to the application note AN-952: 8V19N480/490 Design Guide for JESD204B Output Phase Alignment and Termination
for additional information on phase alignment, termination and coupling techniques.
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Status Conditions and Interrupts
The device has an interrupt output to signal changes in status conditions. Settings for status conditions may be accessed in the Status
registers. The devices has several conditions that can indicate faults and status changes in the operation of the device. These are shown
in Table 22 and can be monitored directly in the status registers. Status bits (named: ST_condition) are read-only and reflect the
momentary device status at the time of read-access. Several status bits are also copied into latched bit positions (named: LS_condition).
The latched version is controlled by the corresponding fault and status conditions and remains set (“sticky”) until reset by the user by
writing “1” to the status register bit. The reset of the status condition has only an effect if the corresponding fault condition is removed,
otherwise, the status bit will set again.
Setting a status bit on several latched registers can be programmed to generate an interrupt signal (nINT) via settings in the Interrupt
Enable bits (named: IE_condition). A setting of “0” in any of these bits will mask the corresponding latched status bit from affecting the
interrupt status pin. Setting all IE bits to 0 has the effect of disabling interrupts from the device. Interrupts are cleared by resetting the
appropriate bit(s) in the latched register after the underlying fault condition has been resolved. When all valid interrupt sources have been
cleared in this manner, this will release the nINT output until the next unmasked fault
Table 22. Status Bit Functions
Status Bit
Function
Status if Bit is:
Momentary
Latched
Description
1
0
Interrupt Enable
Bit
ST_CLK_0
LS_CLK_0
CLK 0 input status
Active
LOS
IE_CLK_0
ST_CLK_1
LS_CLK_1
CLK 1 input status
Active
LOS
IE_CLK_1
nST_LOLV
nLS_LOLV
VCXO-PLL loss of lock
Locked
Loss of lock
IE_LOLV
nST_LOLF[a]
nLS_LOLF
FemtoClockNG-PLL loss of lock
Locked
Loss of lock
IE_LOLF
nST_HOLD
nLS_HOLD
Holdover
Not in holdover
Device in holdover
IE_HOLD
ST_VCOF
—
FemtoClockNG VCO calibration
Not completed
Completed
—
ST_SEL[1:0]
—
Clock input selection in
auto-selection mode
ST_REF
LS_REF
PLL reference status
00 = CLK_0
01 = CLK_1
10, 11 - not defined
Valid reference[b]
Reference lost
—
IE_REF
[a] nST_LOLV and nLS_LOLV report 1 (PLL locked) if the VCXO-PLL is bypassed by setting BYPV = 1
[b] Manual and short-term holdover mode: 0 indicates if the reference selected by SEL[1:0] is lost, 1 if not lost
Automatic with holdover mode: 0 indicates the reference is lost and while still in holdover
Table 23. LOCK Function
Status Bit (PLL)
nLS_LOLV
(VCXO-PLL)
Locked[a]
Not locked
nLS_LOLF
(FemtoClockNG)
Status reported on LOCK
output
Locked
1
Not locked
0
Locked
0
Not locked
0
[a] nST_LOLV and nLS_LOLV report 1 (PLL locked) if the VCXO-PLL is bypassed by setting BYPV = 1
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Device Startup, Reset, and Synchronization
At startup, an internal POR (power-on reset) resets the device and sets all register bits to its default value. The device forces the VCXO
control voltage at the LFV pin to half of the power supply voltage to center the VCXO-frequency. In the default configuration the QCLK_y
and QREF_r outputs are disabled at startup.
Recommended Configuration Sequence (In Order):
1. (Optional) Set the value of the CPOL register bit to define the SPI read mode, so that SPI settings can be validated by subsequent SPI
read accesses.
2. Configure all PLL settings, output divider and delay circuits as well as other device configurations:
▪ BYPF and BYPV for the desired PLL operation mode and configure the PLL dividers PV, MV0, MV1, MF and PF as required to achieve
PLL lock. See Table 2 for details
▪
▪
▪
▪
▪
▪
▪
VCXO-PLL lock detect window by configuring the phase settings MV0 and PV
Charge pump currents for both PLLs (CPV[4:0] and CPF[4:0]) and POLV for the desired VCXO polarity
(optional) OSVEN and OFFSET[4:0] for the VCXO-PLL static phase offset
Channel dividers (see Table 8)
MUX_r for the desired operation of the QREF_r outputs
QCLK_y, QREF_r and QOSC output features such as desired output power-down state, style and amplitude
Desired input selection and monitoring modes: this involves nM/A[1:0] and SEL[1:0] for input selection. In any of the automatic
modes, configure PRIO[1:0]_n, and REVS. Configure the CNTH[7:0], CNTR[1:0] counters for the desired holdover characteristics
and DIV4_VAL, CNTV[1:0] for input revalidation if applicable to the operation mode.
▪ Individual CLK_X and REF_r registers and the global delay REF_S register for the desired phase delay between clock and
SYSREF outputs; see (link to phase alignment section).
▪ Interrupt enable configuration bits IE_status_condition, as desired for fault reporting on the nINT output
3. For SYSREF operation:
▪ Configure the NS and SYNC divider as described in the section Status Conditions and Interrupts
▪ Configure the SYSREF registers SRG, SRO and SRPC[7:0] according to the desired SYSREF operation
4. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit
will self-clear.
5. Set both the RELOCK bit and PB_CAL bit. This step should not be combined with the previous step (setting INIT_CLK) in a multi
SPI-byte register access. Both bits will self-clear.
6. Clear the FVCV bit to release the VCXO control voltage and VCXO-PLL will attempt to lock to the input clock signal starting from its
center frequency.
7. Clear the status flags.
8. At this point, the basic configuration of the registers 0x00 to 0x73 should be completed and the SPI transfer ended (set nCS to high
level).
9. In a separate SPI write access, enable the outputs as desired by accessing the output-enable registers 0x74 and 0x76.
10. For SYSREF operation: set the RS bit to start (or re-start) generating the configured number of SYSREF pulses. The RS bit will auto-clear.
• In internal SYSREF generation mode (SRG = 0) the SYSREF pulses are generated as a result of setting the RS bit.
• In external SYSREF mode the SYSREF pulses are generated at the next rising edge of the EXT_SYS input.
Reserved registers and registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to
0xFF range.
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Changing Frequency Dividers and Phase Delay Values
Clock Frequency Divider and Delay
The following procedure must be applied for a change of a clock divider and phase delay value NA-E, and CLKA-E:
1. (Optional) Set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI
read accesses.
2. (Optional) Disable the outputs whose frequency divider or delay value is changed.
3. Configure the NA-E dividers and the delay circuits CLKA-E to the desired new values.
4. (Optional) configure the SYNC divider if required for synchronization between clock and SYSREF signals.
5. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit
will self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state.
6. Set the RELOCK bit. This step should not be combined with the setting INIT_CLK in a multi SPI-byte register access. Bit will self-clear.
7. (Optional) enable the outputs whose frequency divider was changed.
SYSREF Frequency Divider, Delay and Starting/Re-Starting SYSREF Pulse Sequences
The following procedure must be applied for a change of a SYSREF divider and phase delay value N S and REF_S:
1. (Optional) Set the value of the CPOL register to define the SPI read mode, so that SPI settings can be validated by subsequent SPI
read accesses.
2. (Optional) Disable the outputs whose frequency divider or delay value is changed.
3. Configure any NS divider and any delay circuits REF_S to their desired new values.
4. Configure the SYNC divider if required for synchronization between clock and SYSREF signals.
5. Set the initialization bit INIT_CLK. This will initiate all divider and delay circuits and synchronize them to each other. The INIT_CLK bit
will self-clear. During this initialization step, all QCLK_y and QREF_r outputs are reset to the logic low state.
6. Set the RELOCK bit. This step should not be combined with the setting INIT_CLK in a multi SPI-byte register access. Bit will self-clear.
7. Set the SRO bit to counted pulse mode or to continues pulse mode, as desired
8. (Optional) enable the outputs whose frequency divider was changed.
9. For SYSREF operation: set the RS bit to start (or re-start) generating the configured number of SYSREF pulses. The RS bit will auto-clear.
▪ In internal SYSREF generation mode (SRG = 0) the SYSREF pulses are generated as a result of setting the RS bit.
▪ In external SYSREF mode the SYSREF pulses are generated at the next rising edge of the EXT_SYS input.
SPI Interface
The device has a 3-wire serial control port capable of responding as a slave in an SPI configuration to allow read and write access to any
of the internal registers for device programming or read back. The SPI interface consists of the SCLK (clock), SDAT (serial data input and
output), and nCS (chip select) pins. A data transfer consists any integer multiple of 8 bits and is always initiated by the SPI master on the
bus. Internal register data is organized in SPI bytes of 8 bit each.
If nCS is at logic high, the SDAT data I/O is in high-impedance state and the SPI interface of the device is disabled.
In a write operation, data on SDAT will be clocked in on the rising edge of SCLK. In a read operation, data on SDAT will be clocked out on
the falling or rising edge of SCLK depending on the CPOL setting (CPOL=0: output data changes on the falling edge, CPOL=1: output
data changes on the rising edge).
Starting a data transfer requires nCS to set and hold at logic low level during the entire transfer. Setting nCS = 0 will enable the SPI
interface with SDAT in data input mode. The master must initiate the first 8-bit transfer. The first bit presented by the SPI master in each
transfer is the LSB (least significant bit). The first bit presented to the slave is the direction bit R/nW (1 = Read, 0 = Write) and the
following seven bits are the address bits A[0:6] pointing to an internal register in the address space 0 to 127.
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Read operation from an internal register: a read operation starts with an 8 bit transfer from the master to the slave: SDAT is clocked on
the rising edge of SCLK. The first bit is the direction bit R/nW which must be to 1 to indicate a read transfer, followed by 7 address bits
A[0:6]. After the first 8 bits are clocked into SDAT, the SDAT I/O changes to output: The register content addressed by A[0:6] are loaded
into the shift register and the next 8 SCLK falling (CPOL=1) clock cycles will then present the loaded register data on the SDAT output
and transfer these to the master. Transfers must be completed with de-asserting nCS after any multiple 8 SCLK cycles. If nCS is
de-asserted at any other number of SCLKs, the SPI behavior is undefined. SPI byte (8 bit) and back-to-back read transfers of multiple
registers are supported with an address auto-increment. During multiple transfers, nCS must stay at logic low level and SDAT will present
multiple registers (A), (A+1), (A+2), etc. with each 8 SCLK cycles. During SPI Read operations, the user may continue to hold nCS low
and provide further bytes of data for up to a total of 127 bytes in a single block read.
Write operation to a device register: During a write transfer, a SPI master transfers one or more bytes of data into the internal registers
of the device. A write transfer starts by asserting nCS to low logic level. The first bit presented by the master must set the direction bit
R/nW to 0 (Write) and the 7 address bits A[0:6] must contain the 7-bit register address. Bits D0 to D7 contain 8 bit of payload data, which
is written into the register addressed by A[0:6] at the end of a 8-bit write transfer. Multiple, subsequent register transfers from the master
to the slave are supported by holding nCS asserted at logic low level during write transfers. The 7 bit register address will auto-increment.
Transfers must be completed with de-asserting nCS after any multiple 8 SCLK cycles. If nCS is de-asserted at any other number of
SCLKs, the SPI behavior is undefined.
End of transfer: After nCS is de-asserted to logic 1, the SPI bus is available to transfers to other slaves on the SPI bus. See also the
READ diagram (Figure 5) and WRITE (Figure 6) displaying the transfer of two bytes of data from and into registers.
Registers 0x78 to 0xFF. Registers in the address range 0x78 to 0xFF should not be used. Do not write into any registers in the 0x78 to
0xFF range.
Figure 5. Logic Diagram: READ Data from Registers for CPOL = 0 and CPOL = 1
SCLK
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
nCS
SDAT, CPOL=0
Hi-Imp
1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
SDAT, CPOL=1
Hi-Imp
1 A0 A1 A2 A3 A4 A5 A6
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Output Register Data
(Address)
Input R=1, 7-bit Address
Hi-Imp
Hi-Imp
Output Register Data
(Address+1)
Figure 6. Logic Diagram: WRITE Data into Registers
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
nCS
SDAT
Hi-Imp
0
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
Input nW=0, 7-bit Address
©2020 Renesas Electronics Corporation
Input Register Data (Address)
28
Hi-Imp
Input Register Data
(Address+1)
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8V19N492 Datasheet
Table 24. SPI Read / Write Cycle Timing Parameters
Symbol
Parameter
Test Condition
Minimum
Maximum
Unit
20
MHz
fSCLK
SCLK frequency
tS1
Setup time, nCS (falling) to SCLK (rising)
5
ns
tS2
Setup time, SDAT (input) to SCLK (rising)
5
ns
tS3
Setup time, nCS (rising) to SCLK (rising)
5
ns
tH1
Hold time, SCLK (rising) to SDAT (input)
5
ns
tH2
Hold time, SCLK (falling) to nCS (rising)
5
ns
tPD2F
Propagation delay, SCLK (falling) to SDAT
CPOL = 0
12
ns
tPD2R
Propagation delay, SCLK (rising) to SDAT
CPOL = 1
12
ns
tPD3
Propagation delay, nCS to SDAT disable
12
ns
Figure 7. SPI Timing Diagram
tH2
nCS
tS3
tS1
SCLK
tS2
tH1
SDAT
(Input)
tPD1F
tPD1R
tPD2
SDAT
(Output)
High Impedance
Table 25. Serial Interface Logic Voltage
SELSV
SPI Interface (SCLK, SDAT, nCS) Logic Voltage
0
(default)
1.8V
1
3.3V
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8V19N492 Datasheet
Configuration Registers
This section contains all addressable registers, sorted by function, followed for a detailed description of each bit field for each register.
Several functional blocks with multiple instances in this device have individual registers controlling their settings, but since the registers
have an identical format and bit meaning, they are described only once, with an additional table to indicate their addresses and default
values. All writable register fields will come up with a default values as indicated in the Factory Defaults column unless altered by values
loaded from non-volatile storage during the initialization sequence.
Fixed read-only bits will have defaults as indicated in their specific register descriptions. Read-only status bits will reflect valid status of
the conditions they are designed to monitor once the internal power-up reset has been released. Unused registers and bit positions are
Reserved. Reserved bit fields may be used for internal debug test and debug functions.
Table 26. Configuration Registers
Register Address
Register Description
0x00–0x01
PLL Frequency Divider: MV, MV0
0x02–0x03
PLL Frequency Divider: MV1, BYPF
0x04–0x05
VCXO-PLL Control: Frequency Divider, PV, PV
0x06–0x07
Reserved
0x08–0x09
PLL Frequency Divider MF
0x0A
VCXO-PLL Control BYPV
0x0B
Reserved
0x0C
PLL Frequency Divider: PF, FDF
0x0D–0x0F
Reserved
0x10–0x12
VCXO-PLL Control, output state QOSC
0x13
Reserved
0x14
Input Selection Mode Priority
0x15
Input Selection Mode Switching
0x16
Input Selection Mode CNTH
0x17
Input Selection Mode: CNTR, CNTV
0x18
SYSREF control: Divider, PD
0x19
SYSREF control SYNC
0x1A
SYSREF control SRPC
0x1B
SYSREF control REF_S
0x1C
SYSREF control SRG, SRO
0x1D–0x1F
Reserved
0x20–0x22
Channel A
0x23
Reserved
0x24
Output State QCLK_A0
0x25
Output State QCLK_A1
0x26
Reserved
0x27
Reserved
0x28
QREF_A0: Delay, MUX
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Table 26. Configuration Registers (Cont.)
Register Address
Register Description
0x29
QREF_A1: Delay, MUX
0x2A
QREF_A2: Delay, MUX
0x2B
Reserved
0x2C
Output State QREF_A0
0x2D
Output State QREF_A1
0x2E
Output State QREF_A2
0x2F
Reserved
0x30–0x32
Channel B
0x33
Reserved
0x34
Output State QCLK_B0
0x35
Output State QCLK_B1
0x36–0x37
Reserved
0x38
QREF_B0: Delay, MUX
0x39
QREF_B1: Delay, MUX
0x3A–0x3B
Reserved
0x3C
Output State QREF_B0
0x3D
Output State QREF_B1
0x3E–0x3F
Reserved
0x40–0x42
Channel C
0x43–0x44
Reserved
0x45
Output State QCLK_C
0x46–0x48
Reserved
0x49
QREF_C Delay, MUX
0x4A–0x4C
Reserved
0x4D
Output State QREF_C
0x4E–0x4F
Reserved
0x50–0x52
Channel D
0x53
Reserved
0x54
Output State QCLK_D
0x55–0x57
Reserved
0x58
QREF_D Delay, MUX
0x59–0x5B
Reserved
0x5C
Output State QREF_D
0x5D–0x5F
Reserved
0x60–0x62
Channel E
0x63
Reserved
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Table 26. Configuration Registers (Cont.)
Register Address
Register Description
0x64
Output State QCLK_E0
0x65
Output State QCLK_E1
0x66–0x67
Reserved
0x68–0x69
Interrupt Enable
0x6A–0x6B
Reserved
0x6C
Status (Latched)
0x6D
Status (Momentary)
0x6E
Status (Latched)
0x6F
Status (Momentary)
0x70
SYSREF control RS
0x71–0x73
General Control
0x74–0x75
Output State QCLK
0x76
Output State QREF
0x70
SYSREF control RS
0x77
Reserved
0x78–0x7A
Reserved
0x7B
Reserved
0x7C–0x7F
Reserved
0x80–0xFF
Reserved
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8V19N492 Datasheet
Channel and Clock Output Registers
The content of the channel register and clock output registers set the channel state, the clock divider, the QCLK output state and clock
phase delay.
Table 27. Channel and Clock Output Register Bit Field Locations
Bit Field Location
Register
Address
D7
D6
D5
D4
D3
0x20: Channel A
0x30: Channel B
0x40: Channel C
0x50: Channel D
0x60: Channel E
N_A[7:0]
N_B[7:0]
N_C[7:0]
N_D[7:0]
N_E[7:0]
0x21: Channel A
0x31: Channel B
0x41: Channel C
0x51: Channel D
0x61: Channel E
CLK_A[7:0]
CLK_B[7:0]
CLK_C[7:0]
CLK_D[7:0]
CLK_E[7:0]
D2
D1
D0
Reserved
Reserved
Reserved
0x22: Channel A
0x32: Channel B
0x42: Channel C
0x52: Channel D
0x62: Channel E
PD_A
PD_B
PD_C
PD_D
PD_E
Reserved
Reserved
Reserved
0x24: QCLK_A0
0x25: QCLK_A1
PD_A0
PD_A1
Reserved
Reserved
STYLE_A0
STYLE_A1
A_A0[1:0]
A_A1[1:0]
Reserved
0x34: QCLK_B0
0x35: QCLK_B1
PD_B0
PD_B1
Reserved
Reserved
STYLE_B0
STYLE_B1
A_B0[1:0]
A_B1[1:0]
Reserved
0x45: QCLK_C
PD_C
Reserved
Reserved
STYLE_C
A_C
Reserved
0x54: QCLK_D
PD_D
Reserved
Reserved
STYLE_D
A_D
Reserved
0x64: QCLK_E0
0x65: QCLK_E1
PD_E0
PD_E1
Reserved
Reserved
STYLE_E0
STYLE_E1
A_E0[1:0]
A_E1[1:0]
Reserved
0x74
EN_QCLK_
A0
EN_QCLK_
A1
Reserved
EN_QCLK_
B0
EN_QCLK_
B1
Reserved
EN_QCLK_
C
EN_QCLK_
D
0x75
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EN_QCLK_
E1
EN_QCLK_
E0
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Reserved
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8V19N492 Datasheet
Table 28. Channel and Clock Output Register Descriptions[a]
Bit Field Location
Bit Field Name
N_x[7:0]
Default
(Binary)
Field Type
R/W
0000 0100
Value= ÷6
Description
Output Frequency Divider N
N_x[7:0]Divider Value
1000 0000
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0110
÷1
÷2
÷3
÷4
÷5
÷6
÷8
0100 0011
0100 0100
0100 0110
0100 1011
0100 1100
÷10
÷12
÷16
÷20
÷24
0101 0011
0100 1110
0101 0100
÷30
÷32
÷36
0101 1011
0101 0110
÷40
÷48
0110 0011
÷50
0110 0100
0101 1110
÷60
÷64
0110 0110
÷80
0101 1111
÷72
0110 1110
÷96
0111 1011
÷100
0111 1100
0111 0110
÷120
÷128
0111 1110
÷160
PD_x
R/W
0
0 = Channel x is powered up
1 = Channel x is power down
PD_y
R/W
0
0 = Output QCLK_y is powered up
1 = Output QCLK_y is power down
CLK_x[7:0]
R/W
0000 0000
CLK_x phase delay
CLK_x[7:0]
Delay in ps = CLK_x 339ps (256 steps)
0000 0000 = 0 ps
…
1111 1111 = 86.466ns
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Table 28. Channel and Clock Output Register Descriptions[a]
Bit Field Location
Bit Field Name
A_y[1:0]
Default
(Binary)
Field Type
R/W
00
Description
QCLK_y Output amplitude
Setting for STYLE = 0 (LVDS)
Setting for STYLE = 1 (LVPECL)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
Termination: 100 across
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
Termination: 50 to VT
STYLE_y
R/W
0
QCLK_y Output format
0 = Output is LVDS (Requires LVDS 100 output termination)
1 = Output is LVPECL (Requires LVPECL 50 output termination of to the specified
recommended termination voltage).
EN_y
R/W
0
QCLK_y Output enable
0 = QCLK_y Output is disabled at the logic low state
1 = QCLK_y Output is enabled
[a] x = A, B, C, D, E; y=A0, A1, B0, B1, C, D, E0, E1; r=A0, A1, A2, B0, B1, C, D
QREF Output State Registers
The content of the output registers set the output frequency and divider, several output states, the power state, the output style and
amplitude.
Table 29. QREF Output State Register Bit Field Locations[a]
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
REF_F[1:0]_A0
REF_F[1:0]_A1
REF_F[1:0]_A2
MUX_A0
MUX_A1
MUX_A2
REF_A0[2:0]
REF_A1[2:0]
REF_A2[2:0]
REF_F[2]
_A0
REF_F[2]
_A1
0x38: QREF_B0
0x39: QREF_B1
Reserved
REF_F[1:0]_B0
REF_F[1:0]_B1
MUX_B0
MUX_B1
REF_B0[2:0]
REF_B1[2:0]
REF_F[2]
_B0
REF_F[2]
_B1
0x49: QREF_C
Reserved
REF_F[1:0]_C
MUX_C
REF_C[2:0]
REF_F[2]
_C
0x58: QREF_D
Reserved
REF_F[1:0]_D
MUX_D
REF_D[2:0]
REF_F[2]
_D
0x28: QREF_A0
0x29: QREF_A1
0x2A:QREF_A2
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8V19N492 Datasheet
Table 29. QREF Output State Register Bit Field Locations[a]
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
0x2C: QREF_A0
0x2D: QREF_A1
0x2E: QREF_A2
PD_A0
PD_A1
PD_A2
Reserved
nBIAS_A0
nBIAS_A1
nBIAS_A2
STYLE_A0
STYLE_A1
STYLE_A2
A_A0[1:0]
A_A1[1:0]
A_A2[1:0]
Reserved
0x3C: QREF_B0
0x3D: QREF_B1
PD_B0
PD_B1
Reserved
nBIAS_B0
nBIAS_B1
STYLE_B0
STYLE_B1
A_B0[1:0]
A_B1[1:0]
Reserved
0x4D: QREF_C
PD_C
Reserved
nBIAS_C
STYLE_C
A_C[1:0]
Reserved
0x5C: QREF_D
PD_D
Reserved
nBIAS_D
STYLE_D
A_D[1:0]
Reserved
0x76
EN_QREF_
A0
EN_QREF_
A1
EN_QREF_
A2
EN_QREF_
B0
EN_QREF_
B1
Reserved
D1
D0
EN_QREF_
C
EN_QCLK_
D
[a] x = A, B, C, D, E; y = A0, A1, B0, B1, C, D, E0, E1; r = A0, A1, A2, B0, B1, C, D
Table 30. QREF Output State Register Descriptions[a]
Bit Field Location
Bit Field Name
Default
(Binary)
Field Type
Description
MUX_r
R/W
1
0 = QREF_r output signal source is the channel’s clock signal
1 = QREF_r output signal source is the centrally generated SYSREF signal
REF_r[2:0]
R/W
000
SYSREF coarse phase delay
REF_r[2:0]
Delay in ps = REF_r[2:0] 169 ps (8 steps)
000 = 0 ps
…
111 = 1.187 ns
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8V19N492 Datasheet
Table 30. QREF Output State Register Descriptions[a]
Bit Field Location
Bit Field Name
REF_F[2:0]_r
Default
(Binary)
Field Type
R/W
000
Description
SYSREF fine phase delay
REF_F[2:0]_r
Insert a SYSREF fine phase delay in ps (8 steps) in addition to the delay value in
REF_r[2:0].
000 = 0ps
001 = 25ps
010 = 50ps
011 = 75ps
100 = 85ps
101 = 110ps
110 = 135ps
111 = 160ps
nBIAS_r
R/W
0
QREF_r Output Bias Voltage
0 = Output is not voltage biased.
1 = Output is biased to the LVDS cross-point voltage if BIAS_TYPE (register 0x19, bit
7) is set to 1. Bit has no effect if BIAS_TYPE = 0.
Output bias = 1 requires AC coupling and LVDS style on the corresponding output.
A_r[1:0]
R/W
00
QREF_r Output amplitude
Setting for STYLE_r = 0 (LVDS)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
Termination: 100 across
Setting for STYLE_r = 1 (LVPECL)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 750mV
A[1:0] = 11:1000mV
Termination: 50 to VT
PD_r
R/W
0
QREF_r Output Power Down
0 = Output is powered up
1 = Output is power down. STYLE, EN and A[1:0] settings have no effect.
STYLE_r
R/W
0
QREF_r Output format
0 = Output is LVDS (Requires LVDS 100 output termination)
1 = Output is LVPECL (Requires LVPECL 50 output termination to the specified
recommended termination voltage).
EN_r
R/W
0
QREF_r Output enable
0 = Output is disabled at the logic low state
1 = Output is enabled
[a] x = A, B, C, D, E; y=A0, A1, B0, B1, C, D, E0, E1; r=A0, A1, A2, B0, B1, C, D
©2020 Renesas Electronics Corporation
37
November 5, 2020
8V19N492 Datasheet
PLL Frequency Divider Registers
Table 31. PLL Frequency Divider Register Bit Field Locations
Bit Field Location
Register Address
D7
0x00
D6
D5
D4
D3
PD_MV1
MV0[2:0]
MV0[7:0]
0x02
MV1[7:0]
MV[8]
0x04
Reserved
Reserved
Reserved
0x05
0x08
Reserved
Reserved
Reserved
PV[2:0]
D1
D0
Reserved
BYPF
MV0[11:8]
0x01
0x03
D2
PV[11:8]
PV[7:0]
Reserved
Reserved
Reserved
Reserved
0x09
Reserved
Reserved
Reserved
MF[8]
Reserved
Reserved
BYPV
MF[7:0]
0x0A
Reserved
Reserved
0x0C
FDF
Reserved
Reserved
Reserved
Reserved
PF[5:0]
Table 32. PLL Frequency Divider Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
Description
Phase of the MV0 feedback divider. Determines the PLL lock-detect phase window in
conjunction with PV[2:0]. Sampling clock phase is relative to the VCXO-PLL phase
detector clock edge. Set MV0[2:0] in relationship to MV0:
MV0[2:0] Setting
MV0 Divider Value
MV0[2:0]
R/W
©2020 Renesas Electronics Corporation
000
1 - 31
32 - 63
64-127
128-255
256-511
512-1023
1024+
010
011
100
101
110
111
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November 5, 2020
8V19N492 Datasheet
Table 32. PLL Frequency Divider Register Descriptions
Bit Field Location
Bit Field Name
MV0[11:0]
Default
(Binary)
Field Type
1100
0000 0000
R/W
Value=÷3072
MV1[8:0]
R/W
0 0110 0000
Value = ÷96
0
PD_MV1
R/W
Value = MV1
enabled
Description
VCXO-PLL Feedback-Divider
The value of the frequency divider (binary coding)
Range: ÷1 to ÷4095
PLL Feedback-Divider.
The value of the frequency divider (binary coding)
Range: ÷4 to ÷511
PLL Feedback-Divider MV1 Power Down/Disabled.
0 = MV1 Divider is enabled
1 = MV1 Divider is powered down and disabled
Disabled MV1 to save power consumption in configurations not using the input clock
monitors.
Phase of the PV input (reference) divider. Determines the PLL lock-detect phase
window in conjunction with MV0[2:0]. Sampling clock phase is relative to the
VCXO-PLL phase detector clock edge. Set PV[2:0] in relationship to PV:
PV Divider Value
PV[2:0] Setting
PV[2:0]
PV[11:0]
R/W
000
1100
0000 0000
R/W
Value=÷3072
0 0001 1000
MF[8:0]
R/W
Value = ÷24
00 0000
PF[5:0]
R/W
Value =
Bypass
0
FDF
R/W
Value =
fVCXO ÷ PF
©2020 Renesas Electronics Corporation
1-31
32-63
64-127
128-255
256-511
512-1023
1024+
010
011
100
101
110
111
VCXO-PLL Input Frequency Pre-Divider
The value of the frequency divider (binary coding)
Range: ÷1 to ÷4095
FemtoClock NG Pre-Divider
The value of the frequency divider (binary coding)
Range: ÷8 to ÷511
FemtoClockNG Pre-Divider
The value of the frequency divider (binary coding)
Range: ÷1 to ÷63
00 0000: PF is bypassed
Frequency Doubler
The input frequency of the FemtoClockNG PLL (2nd stage) is:
0 = The output signal of the BYPV multiplexer, divided by the PF divider
1 = The output signal of the BYPV multiplexer, doubled in frequency.
Use this setting to improve phase nose. The PF divider has no effect if FDF=1.
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November 5, 2020
8V19N492 Datasheet
VCXO-PLL Control Registers
Table 33. VCXO-PLL Control Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x03
MV[8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BYPF
0x0A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BYPV
0x10
POLV
FVCV
Reserved
CPV[4:0]
0x11
nPD_QOSC
STYLE_QO
SC
OSVEN
OFFSET[4:0]
0x12
Reserved
A_QOSC[1:0]
CPF[4:0]
Table 34. VCXO-PLL Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
Description
BYPF
R/W
0
PLL feedback Bypass
0 = VCXO-PLL feedback divider: MV0
1 = VCXO-PLL feedback divider: MV0 MV1
BYPV
R/W
0
VCXO-PLL Bypass
0 = VCXO-PLL is enabled.
1 = VCXO-PLL is disabled and bypassed.
0
VCXO Polarity
0 = Positive polarity. Use for an external VCXO with a positive f(VC) characteristics
1 = Negative polarity. Use for an external VCXO with a negative f(VC) characteristics
1
VCXO-PLL Force VC control voltage
0 = Normal operation.
1 = Forces the voltage at the LFV control pin (VCXO input) to VDD_V/2. VCXO-PLL
unlocks and the VCXO is forced to its mid-point frequency. FVCV=1 is the default
setting at startup to center the VCXO frequency. FVCV should be cleared after startup
to enable the PLL to lock to the reference frequency.
POLV
FVCV
R/W
R/W
1 1000
CPV[4:0]
R/W
©2020 Renesas Electronics Corporation
Value:
1.25mA
VCXO-PLL Charge-Pump Current
Controls the charge pump current ICPV of the VCXO-PLL. Charge pump current is the
binary value of this register plus one multiplied by 50µA.
ICPV = 50µA (CPV[4:0] + 1).
CPV[4:0] = 00000 sets ICPV to the min. current of 50µA. Max. charge pump current is
1.6 mA. Default setting is 1.25mA: ((24 + 1) 50µA).
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November 5, 2020
8V19N492 Datasheet
Table 34. VCXO-PLL Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
nPD_QOSC
R/W
0
QOSC Power State
0 = Output QOSC is powered down
1 = Output QOSC is power up
0
QOSC Output format
0 = Output is LVDS (Requires LVDS 100 output termination)
1 = Output is LVPECL (Requires LVPECL 50 output termination of to the specified
recommended termination voltage).
0
VCXO-PLL Offset Enable
0 = No offset
1 = Offset enabled. A static phase offset of OFFSET[4:0] is applied to the PFD of the
VCXO-PLL
STYLE_QOSC
OSVEN
R/W
R/W
0 0000
OFFSET[4:0]
R/W
Value: 0
1 1000
CPF[4:0]
R/W
Value:
5.0mA
Description
VCXO-PLL Static Phase Offset
Controls the static phase detector offset of the VCXO-PLL. Phase offset is the binary
value of this register multiplied by 0.9 of the PFD input signal (OFFSET [4:0] fPFD ÷
400). Max. offset is 31 0.927.9 Setting OFFSET to 0.0 eliminates the thermal
noise of an offset current. If the VCXO-PLL input jitter period TJIT exceeds the average
input period: set OFFSET to a value larger than f PFD TJIT 400 to achieve a better
charge pump linearity and lower in-band noise of the PLL.
FemtoClockNG-PLL Charge-Pump Current
Controls the charge pump current ICPF of the FemtoClockNG PLL. Charge pump
current is the binary value of this register plus one multiplied by 200µA.
ICPF = 200µA (CPF[4:0] + 1).
CPV[4:0] = 00000 sets ICPF to the min. current of 200µA. Max. charge pump current is
6.4 mA. Default setting is 5.0 mA: ((24+1) 200µA)
QOSC Output amplitude
00
A_QOSC
R/W
©2020 Renesas Electronics Corporation
Value:
250mV
Setting for STYLE_r = 0 (LVDS)
Setting for STYLE_r = 1 (LVPECL)
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 500mV
A[1:0] = 11: 750mV
Termination: 100 across
A[1:0] = 00: 250mV
A[1:0] = 01: 500mV
A[1:0] = 10: 500mV
A[1:0] = 11: 750mV
Termination: 50 to VT
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November 5, 2020
8V19N492 Datasheet
Input Selection Mode Registers
Table 35. Input Selection Mode Bit Field Locations
Bit Field Location
Register Address
0x14
0x15
D7
D6
PRIO_0[1:0]
Reserved
D5
D4
PRIO_1[1:0]
BLOCK_LOR
DIV4_VAL
REVS
0x16
0x17
D3
D2
D1
D0
PRIO_2[1:0]
PRIO_3[1:0]
nM/A[1:0]
SEL[1:0]
PD_CLKn
CNTV[1:0]
CNTH[7:0]
CNTR[1:0]
Reserved
Reserved
Table 36. Input Selection Mode Register Descriptions
Bit Field Location
Bit Field Name
PRIO_n[1:0]
Field Type
R/W
Default
(Binary)
CLK_0: 11
CLK_1: 10
0
DIV4_VAL
R/W
Value: ÷1
REVS
R/W
0
(Value: off)
©2020 Renesas Electronics Corporation
Description
Controls the auto-selection priority of the clock input CLK_n (n=0…3). If multiple inputs
have equal priority, the order within that priority is from CLK0 (highest) to CLK3
(lowest).
00 = Priority 0 (lowest)
01 = Priority 1
10 = Priority 2
11 = Priority 3 (highest)
Pre-divider for CNTV[1:0]. Use the ÷4 pre-divider for input frequencies > 250MHz.
0 = ÷1
1 = ÷4
Revertive Switching.
The revertive input switching setting is only applicable to the two automatic selection
modes shown in Table 10. If nM/A[1:0] = X0, the REVS setting has not meaning.
0 = Disabled: Re-validation of a non-selected input clock has no impact on the clock
selection.
1 = Enabled: Re-validation of any non-selected input clock(s) will cause an new input
selection according to the pre-set input priorities (revertive switch). An input switch is
only done if the re-validated input has a higher priority than the current VCXO-PLL
reference clock.
Default setting is revertive switching turned off.
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November 5, 2020
8V19N492 Datasheet
Table 36. Input Selection Mode Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
00
nM/A[1:0]
R/W
Value:
Manual
Selection
00
SEL[1:0]
CNTH[7:0]
R/W
R/W
Value: CLK0
selected
1000 0000
(value:
136ms)
Description
Reference Input Selection Mode.
In any of the manual selection modes (nM/A[1:0] = 00 or 10), the VCXO-PLL reference
input is selected by SEL[1:0]. In any of the automatic selection modes, the VCXO-PLL
reference input is selected by an internal state machine according to the input LOS
states and the priorities in the input priority registers
00 = Manual selection.
01 = Automatic selection (no holdover)
10 = Short-term holdover.
11 = Automatic selection with holdover
VCXO-PLL Input Reference Selection
Controls the selection of the VCXO-PLL reference input in manual selection mode. In
automatic selection modes (nM/A[1:0]=X1), SEL[1:0] has no meaning.
00 = CLK_0
01 = CLK_1
nMA[1:0]=10 Short-term holdover: Hold-off counter period. The device initiates a clock
failover switch upon counter expiration (zero transition). The counters start to counts
backwards after a LOS event is detected. The hold-off counter period is determined by
the binary number of VCXO-PLL output pulses divided by CNTR[1:0]. With a VCXO
frequency of 122.88 MHz and CNTR[1:0]=10, the counter has a period of (1.066 ms
binary setting). After each zero-transition, the counter automatically re-loads to the
setting in this register. The default setting is 136ms (VCXO=122.88MHz: 1/122.88MHz
217 128)
Short-term holdover reference divider
CNTR[1:0]
CNTR[1:0]
R/W
10
(Value: 217)
122.88MHz VCXO
00 = f VCXO ÷ 215
1875Hz (0.533ms; 0-136ms)
10 = fVCXO ÷ 217
937.5Hz (1.066ms; 0-272ms)
43
38.4MHz VCXO
1171Hz (0.853ms; 0-217.6ms)
216
01 = fVCXO ÷
©2020 Renesas Electronics Corporation
CNTH frequency (period; range)
November 5, 2020
8V19N492 Datasheet
Table 36. Input Selection Mode Register Descriptions
Bit Field Location
Bit Field Name
CNTV[1:0]
Field Type
R/W
Default
(Binary)
Description
10
(value: 32)
Controls the number of required consecutive, valid input reference pulses for clock
re-validation on CLK_n (n=0…3), in number of input periods. At a LOS event, the
re-validation counter loads this setting from the register and counts down by one with
every valid, consecutive input signal period. Missing input edges (for one input period)
will cause this counter to re-load its setting. An input is re-validated when the counter
transitions to zero and the corresponding LOS flag is reset.
DIV4_VAL = 0
DIV4_VAL = 1
00 = 2 (shortest possible)
01 = 16
10 = 32
11 = 64
0
PD_CLK_n
R/W
BLOCK_LOR
R/W
Power
up/Enabled
0
Value: Not
blocked
©2020 Renesas Electronics Corporation
00 = 8 (shortest possible)
01 = 64
10 = 128
11 = 256
Input CLK_n Power Down/Disable.
0 = Input CLK_n is enabled
1 = Input CLK_n is power down and disabled
Disable individual Input CLK_n input to save power consumption in configurations not
using the respective input and in manual switching or short-term holdover mode.
Enable inputs CLK_n in configurations with automatic switching.
Block loss-of-reference (input activity) indicator
VCXO-PLL loss of lock signals nST_LOLV and nLS_LOLV are triggered by:
0 = VCXO-PLL loss of lock or by inactivity of the selected reference clock
1 = Only VCXO-PLL loss of lock.
BLOCK_LOR = 1 will also block loss-of-reference from triggering a failure on the LOCK
output pin.
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8V19N492 Datasheet
SYSREF Control Registers
Table 37. SYSREF Control Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
0x18
PD_S
NS[6:0]
0x19
BIAS_TYPE
SYNC[6:0]
0x1A
SRPC[7:0]
0x1B
REF_S[7:0]
D2
D1
D0
0x1C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SRG
SRO
0x70
RS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 38. SYSREF Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
PD_S
R/W
0
Description
SYSREF global power down (incl. global delay S, SYSREF frequency divider NS)
0 = SYSREF functional blocks are powered up.
1 = SYSREF functional blocks are powered down.
SYSREF Frequency Divider.
The value of the frequency divider is set by the product of NS[6] NS[5:4] NS[3:2]
NS[1:0]
NS[6]
NS[5:4]
NS[3:2]
NS[1:0]
010 11 11
NS[6:0]
BIAS_TYPE
R/W
R/W
©2020 Renesas Electronics Corporation
Value =
÷1280
1
0 = ÷2
1 = ÷4
00 = ÷2
01 = ÷4
10 = ÷8
11 = ÷16
00 = ÷2
01 = ÷4
10 = ÷8
11 = ÷16
00 = ÷2
01 = ÷3
10 = ÷4
11 = ÷5
The SYSREF contains four serial dividers that can be individually controlled by NS[6],
NS[5:4], NS[3:2] and NS[1:0], respectively. The total NS divider is the product of the
four serial dividers. Example: to achieve a SYSREF divider value of ÷384 = {2} {4}
{16} {3}, set NS[6]=0, NS[5:4]=01, NS[3:2]=11 and NS[1:0]=01.
If a given output divider can be achieved by multiple NS[6:0] settings, use the highest
possible divider in NS[1:0], then in NS[3:2], followed by NS[5:4]=11 and then NS[6]
SYSREF output voltage bias
0 = QREF_r outputs are in a low/high state when nBIAS_r is set to 1 or during a
SYSREF event
1 = QREF_r outputs are in a cross-point biased state when nBIAS_r is set to 1 or
during a SYSREF event.
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November 5, 2020
8V19N492 Datasheet
Table 38. SYSREF Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
Description
SYSREF Synchronizer divider value. This divider controls the release of SYSREF
pulses at coincident QCLK clock edges. For SYSREF operation, set this divider value
to the least common multiple of the clock divider values Nx (x = A to E). For instance, if
NA=NB=÷2, NC=ND=÷3, NE=÷4 set the SYNC divider to ÷12.
SYNC6 Description
0 = SYNC[6] = 0: output frequency divider set by SYNC[2:0]
1 = SYNC[6] = 1: output frequency divider set by the product of SYNC[5:3]
SYNC[2:0].
SYNC[6:0]
R/W
00 00 001
SYNC[5:3]
SYNC[2:0]
000 = ÷2
001 = ÷4
010 = ÷6
011 = ÷8
100 = ÷4
101 = ÷8
110 = ÷12
111 = ÷16
000 = ÷2
001 = ÷3
010 = ÷4
011 = ÷5
100 = ÷6
101 = ÷7
110 = ÷8
111 = ÷9
The frequency divider SYNC is composed of 2 serial dividers that can be individually
controlled by the bit fields SYNC[5:3] and SYNC[2:0].
Set SYNC[6] = 0 to achieve an output divider in the range of {2,3,4,5,6,7,8,9}
Set SYNC[6] = 1 to achieve an output divider value of {2,4,6,8,12,16}
{2,3,4,5,6,7,8,9}.
For instance, the output divider of ÷32 = {4} {8} is set by SYNC[6:0] = 1001110.
If a given output divider can be achieved by multiple SYNC[6:0] settings, a setting with
SYNC[6]=0 is preferred. If SNYC[6]=1, the higher divider value should be configured
with SYNC[2:0].
SRPC[7:0]
R/W
0000 0010
(value: 2)
SYSREF pulse count
Binary value of the SYSREF pulses generated and output at all enabled QREF outputs.
Allows to generate 1 to 255 pulses after each write access. Requires to set SRG = 0
and SRO = 0.
REF_S global SYSREF phase delay. This setting affects all QREF_r outputs
configured as SYSREF.
REF_S[7:0]
REF_S[7:0]
R/W
©2020 Renesas Electronics Corporation
00000
Delay in ps = REF_S 339ps (256 steps)
0000 0000 = 0ps
…
1111 1111 = 86.466ns
46
November 5, 2020
8V19N492 Datasheet
Table 38. SYSREF Control Register Descriptions
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
SRG
R/W
0
SYSREF pulse generation
0 = Internal, SPI controlled SYSREF generation using the RS bit.
1 = External controlled SYSREF generation using the EXT_SYS pin.
0
SYSREF pulse mode
0 = Counted SYSREF pulse generation mode.
Number of pulses is controlled by SRPC[7:0].
1 = Continuous SYSREF pulse generation.
X
Set RS = 1 to initiate the SYSREF pulse generation of SRPC-number of pulses.
Powers up the SYSREF circuitry and releases the SYSREF pulse(s) as configured.
Requires SRG=0 and SRO=0, otherwise no function.
RS = 1 also phase-aligns the QREF outputs to the QCLK outputs and adds the
programmed delay values into the QREF paths.
SRO
RS
R/W
W only
Auto-Clear
Description
Status Registers
Table 39. Status Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x68
Reserved
Reserved
IE_LOLF
IE_LOLV
Reserved
Reserved
IE_CLK_1
IE_CLK_0
0x69
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IE_REF
IE_HOLD
0x6C
Reserved
Reserved
nLS_LOLF
nLS_LOLV
Reserved
Reserved
LS_CLK_1
LS_CLK_0
nST_LOLF
nST_LOLV
Reserved
Reserved
ST_CLK_1
ST_CLK_0
0x6D
ST_SEL[1:0]
0x6E
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LS_REF
nLS_HOLD
0x6F
Reserved
Reserved
Reserved
Reserved
Reserved
ST_VCOF
ST_REF
nST_HOLD
©2020 Renesas Electronics Corporation
47
November 5, 2020
8V19N492 Datasheet
Table 40. Status Register Descriptions[a]
Bit Field Location
Bit Field Name
Field Type
Default
(Binary)
IE_LOLF
R/W
0
Interrupt Enable for FemtoClockNG-PLL loss of lock
0 = Disabled: Setting LS_LOLF will not cause an interrupt on nINT
1 = Enabled: Setting LS_LOLF will assert the nINT output (nINT=0, interrupt)
0
Interrupt Enable for VCXO-PLL loss of lock
0 = Disabled: Setting LS_LOLV will not cause an interrupt on nINT
1 = Enabled: Setting LS_LOLV will assert the nINT output (nINT=0, interrupt)
IE_LOLV
R/W
Description
IE_CLK_n
R/W
0
Interrupt Enable for CLKn input loss-of-signal
0 = Disabled: Setting LS_CLK_n will not cause an interrupt on nINT
1 = Enabled: Setting LS_CLK_n will assert the nINT output (nINT=0, interrupt)
IE_REF
R/W
0
Interrupt Enable for LS_REF
0 = Disabled: any changes to LS_REF will not cause an interrupt on nINT
1 = Enabled: any changes to LS_REF will assert the nINT output (nINT=0, interrupt)
0
Interrupt Enable for holdover
0 = Disabled: Setting LS_HOLD will not cause an interrupt on nINT
1 = Enabled: Setting LS_HOLD will assert the nINT output (nINT=0, interrupt)
-
FemtoClockNG-PLL loss of lock (latched status of nST_LOLF)
Read 0 = 1 loss-of-lock events detected after the last status latch clear
Read 1 = No loss-of-lock detected after the last status latch clear
Write 1 = Clear status latch (clears pending nLS_LOLF interrupt)
-
VCXO-PLL loss of lock (latched status of nST_LOLV)
Read 0 = 1 loss-of-lock events detected after the last status latch clear.
Read 1 = No loss-of-lock detected after the last nLS_LOLV clear
Write 1 = Clear status latch (clears pending nLS_LOLV interrupt)
-
Input CLK_n status (latched status of ST_CLK_n)
Read 0 = 1 LOS events detected on CLK_n after the last LS_CLK_n clear
Read 1 = No loss-of-signal detected on CLK_n input after the last LS_CLK_n clear
Write 1 = Clear LS_CLK_n status latch (clears pending LS_CLK_n interrupts on nINT)
-
Input selection (momentary status)
Reference Input Selection Status of the state machine. In any input selection mode,
reflects the input selected by the state machine.
00 = CLK_0
01 = CLK_1
-
FemtoClockNG-PLL loss of lock (momentary status)
Read 0 = 1 loss-of-lock events detected
Read 1 = No loss-of-lock detected
A latched version of these status bit is available (nLS_LOLF)
IE_HOLD
nLS_LOLF
nLS_LOLV
LS_CLK_n
ST_SEL[1:0]
nST_LOLF
R/W
R/W
R/W
R/W
R
R
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Table 40. Status Register Descriptions[a]
Bit Field Location
Bit Field Name
nST_LOLV
ST_CLK_n
LS_REF
Field Type
R
R
R/W
nLS_HOLD
R/W
ST_VCOF
R
ST_REF
nST_HOLD
R
R
Default
(Binary)
Description
-
VCXO-PLL loss of lock (momentary status bit)
Read 0 = 1 loss-of-lock events detected
Read 1 = No loss-of-lock detected
A latched version of these status bits is available (nLS_LOLV)
-
Input CLK_n status (momentary)
0 = LOS detected on CLK_n
1 = No LOS detected, CLK_n input is active
A latched version of these status bits are available (LS_CLK_n)
-
PLL reference status (latched status of ST_REF)
Read 0 = Reference is lost since last reset of this status bit.
Read 1 = Reference is valid since last reset of this status bit.
Write 1 = Clear LS_REF status latch (clears pending IE_REF interrupts on nINT)
Holdover status indicator (latched status of ST_HOLD)
Read 0 = VCXO-PLL has entered holdover state 1 times after reset of this status bit
Read 1 = VCXO-PLL is (or attempts to) lock(ed) to an input clock
Write 1 = Clear status latch (clears pending nLS_HOLD interrupt)
-
FemtoClockNG-PLL calibration status (momentary)
Read 0 = FemtoClockNG PLL auto-calibration is completed
Read 1 = FemtoClockNG PLL calibration is active (not completed)
-
Input reference status
0 = No input reference present
1 = Input reference is present at the clock input selected by SEL[1:0]
-
Holdover status indicator (momentary)
0 = VCXO-PLL in holdover state, not locked to any input clock
1 = VCXO-PLL is (or attempts to) lock(ed) to input clock
A latched version of this status bit is available (nLS_HOLD)
[a] CLKn = CLK0, CLK1, CLK2, CLK3.
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8V19N492 Datasheet
General Control Registers
Table 41. General Control Register Bit Field Locations
Bit Field Location
Register Address
D7
D6
D5
D4
D3
D2
D1
D0
0x71
INIT_CLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x72
RELOCK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x73
PB_CAL
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CPOL
Table 42. General Control Register Descriptions
Bit Field Location
Default
(Binary)
Bit Field Name
Field Type
INIT_CLK
W only
Auto-Clear
X
RELOCK
W only
Auto-Clear
X
Description
Set INIT_CLK = 1 to initialize divider functions. Required as part of the startup
procedure.
Setting this bit to 1 will force the FemtoClockNG PLL to re-lock.
PB_CAL
W only
Auto-Clear
X
Precision Bias Calibration
Setting this bit to 1 will start the calibration of an internal precision bias current source.
The bias current is used as reference for outputs configured as LVDS and for as
reference for the charge pump currents. This bit will auto-clear after the calibration
completed. Set as part of the startup procedure.
CPOL
R/W
0
SPI Read Operation SCLK Polarity
0 = Data bits on SDAT are output at the falling edge of SCLK edge.
1 = Data bits on SDAT are output at the rising edge of SCLK edge.
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8V19N492 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the
device. Functional operation of the 8V19N492 at absolute maximum ratings is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Table 43. Absolute Maximum Ratings
Item
Rating
Supply Voltage, VDD_V
3.6V
Inputs
-0.5V to VDD_V + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VDD_V + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Outputs, IO (LVDS)
Continuous Current
Surge Current
50mA
100mA
Input termination current, IVT
±35mA
Operating Junction Temperature, TJ
125C
Storage Temperature, T STG
-65C to 150C
ESD - Human Body Model[a]
ESD - Charged Device Model
2000V
a
500V
[a] According to JEDEC JS-001-2012/JESD22-C101
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Pin Characteristics
Table 44. Pin Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)[a]
Symbol
Parameter
CIN[b]
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
Units
OSC, nOSC
2
4
pF
Other inputs
2
4
pF
RPU
Input Pull-Up Resistor
SDAT, nCS, nCLK_0, nCLK_1
51
kΩ
RPU
Input Pull-Down Resistor
EXT_SYS, SCLK, CLK_0, CLK_1
51
kΩ
ROUT
LVCMOS Output Impedance
nINT, LOCK
25
Ω
[a] Design target specifications.
[b] Guaranteed by design
DC Characteristics
Table 45. Power Supply DC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)[a][b]
Symbol
Parameter
VDD_V
Core Supply Voltage
IDD_V
Power Supply Current
Test Conditions
[c]
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
845.5
943.85
mA
[a] Design target specifications.
[b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[c] Test Case 2 of Table 46 with QREFs-On at 7.68MHz and 500mV LVDS.
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Table 46. Typical Power Supply DC Current Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)[a]
Test Case
Symbol
Supply Pin Current
QCLK_y
QREF_r
1
2
3
4
5
6
Style
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
State
On
On
On
On
On
On
Amplitude
500
750
1000
250
500
750
Style
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
State
On
On
Off
On
Off
Off
Amplitude
500
500
250
Unit
mV
mV
IDD_CA
Current through VDD_QCLKA pin
85
101
113
75
69
85
mA
IDD_CB
Current through VDD_QCLKB pin
89
101
112
79
69
85
mA
IDD_CC
Current through VDD_QCLKC pin
64
69
75
58
53
61
mA
IDD_CD
Current through VDD_QCLKD pin
60
66
72
55
49
57
mA
IDD_CE
Current through VDD_QCLKE pin
91
102
113
80
69
85
mA
IDD_RA
Current through VDD_QREFA pin
77.3
77.1
0
55.7
0
0
mA
IDD_RB
Current through VDD_QREFB pin
51.3
51.3
0
36.9
0
0
mA
IDD_RC
Current through VDD_QREFC pin
27.3
25.3
0
20.9
0
0
mA
IDD_RD
Current through VDD_QREFD pin
26.1
25.9
0
18.7
0
0
mA
IDD_INP
Current through VDD_INP pin
60.50
61
61.8
60.1
62.6
63.3
mA
IDD_SPI
Current through VDD_SPI pin
6.0
6.5
6.4
4.4
5.9
6.0
mA
IDD_OSC +
IDD_CP
Current through VDD_OSC and
VDD_CP pins
38.7
38.8
38.9
38.6
39.3
39.0
mA
IDD_SYNC
Current through VDD_SYNC pin
82.6
82.6
1.9
82.8
1.9
1.9
mA
IDD_CPF
Current through VDD_CPF pin
59.4
59.5
59.4
59.4
59.4
60.2
mA
IDD_LCV
Current through VDD_LCV pin
72.3
72.3
72.2
72.3
74.4
76.9
mA
IDD_LCF
Current through VDD_LCF pin
52.2
52.0
52.5
52.5
52.4
52.4
mA
2.7
2.8
2.0
2.5
2.0
2.2
W
3.1
3.3
2.6
2.8
2.0
2.2
W
PTOT
Total Device Power Consumption
PTOT, SYS
Total System Power Consumption
[b]
[a] Configuration: fCLK (input) = 122.88MHz, fSYSREF=7.68MHz, internal SYSREF generation (continuous), QA[2:0] = 1474.56MHz, QB[1:0] =
245.76MHz, QC[1:0] = 245.76MHz, QD = 491.52MHz, QE[1:0] = 122.88MHz). QCLK_y outputs terminated according to amplitude settings.
QREF_r outputs unterminated when SYSREF is turned off.
[b] Includes total device power consumption and the power dissipated in external output termination components.
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Table 47. LVCMOS DC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Control Input SELSV (3.3V Logic)
VIH
Input High Voltage
2.0
VDD_V
V
VIL
Input Low Voltage
-0.3
0.8
V
IIH
Input High Current
VDD_V = 3.3V, V IN = 3.3V
150
µA
IIL
Input Low Current
VDD_V = 3.3V, V IN = 0V
-5
µA
SYSREF Trigger Input EXT_SYS (1.8V/3.3V Selectable Logic)
1.8V logic (SELSV = 0)
1.17
VDD_V
V
3.3V logic (SELSV = 1)
2.0
VDD_V
V
1.8V logic (SELSV = 0)
-0.3
0.63
V
3.3V logic (SELSV = 1)
-0.3
0.8
V
150
µA
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input High Current
VDD_V = 3.3V, V IN = 1.8V or
IIL
Input Low Current
VDD_V = 3.3V, V IN = 0V
3.3V
-5
µA
SPI Inputs SDAT (when input), SCLK, nCS (1.8V/3.3V Selectable Logic with Input Hysteresis)
VI
Input Voltage
VT+
Positive-going Input Threshold Voltage
VT-
Negative-going Input Threshold Voltage
VH
Hysteresis Voltage
IIH
Input
High Current
IIL
Input
Low Current
1.8V logic (SELSV = 0)
Inputs with
pull-up resistor[b]
Inputs with
pull-down resistor[a]
Inputs with
pull-up resistor[b]
VDD_V
V
0.660
1.350
V
3.3V logic (SELSV = 1)
1.8V logic (SELSV = 0)
1.8–2.1
0.495
3.3V logic (SELSV = 1)
VT+ – VT-
Inputs with
pull-down resistor[a]
-0.3
V
1.170
0.75–0.97
0.165
V
V
0.780
V
150
VDD_V = 3.3V, V IH = 1.8V
µA
5
-5
VDD_V = 3.465V, VIL = 0V
µA
-150
SPI output DAT (when output), nINT, LOCK (1.8V/3.3V selectable logic)
VOH
VOL
Output High Voltage
Output Low Voltage
1.8V logic (SELSV = 0)
IOH = -4mA
1.35
V
3.3V logic (SELSV = 1)
IOH = -4mA
2.4
V
1.8V logic (SELSV = 0)
IOL = 4mA
0.45
V
3.3V logic (SELSV = 1)
IOL = 4mA
0.4
V
[a] SCLK, EXT_SYS.
[b] nCS, SDAT (when input)
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8V19N492 Datasheet
Table 48. Differential Input DC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +85°C[a][b]
Symbol
IIH
IIL
Parameter
Input
High Current
Input
Low Current
Test Conditions
Inputs with pull-down
resistor[c]
Pull-down/pull-up
inputs[d]
Inputs with pull-down
resistor
Pull-down/pull-up
inputs[d]
Minimum
Typical
Maximum
Units
150
µA
150
µA
VDD_V = VIN = 3.465V
VDD_V = 3.465V, VIN = 0V
-150
µA
-150
µA
[a] Design target specifications.
[b] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[c] Non-Inverting inputs: CLK_n, OSC
[d] Inverting inputs: nCLK_n, nOSC
Table 49. LVPECL DC Characteristics (QCLK_y, QREF_r, STYLE = 1), VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)
Symbol
VOH
VOL
Parameter
Output High Voltage[a]
Output Low Voltage
Test Conditions
Minimum
Typical
Maximum
Units
250mV amplitude setting
VDD_V – 0.975
VDD_V – 0.875
VDD_V – 0.774
V
500mV amplitude setting
VDD_V – 1.000
VDD_V – 0.904
VDD_V – 0.805
V
750mV amplitude setting
VDD_V – 1.100
VDD_V – 0.937
VDD_V – 0.829
V
1000mV amplitude setting
VDD_V – 1.100
VDD_V – 0.962
VDD_V – 0.861
V
250mV amplitude setting
VDD_V – 1.250
VDD_V – 1.150
VDD_V – 1.040
V
500mV amplitude setting
VDD_V – 1.540
VDD_V – 1.420
VDD_V – 1.131
V
750mV amplitude setting
VDD_V – 1.810
VDD_V – 1.690
VDD_V – 1.580
V
1000mV amplitude setting
VDD_V – 2.090
VDD_V – 1.960
VDD_V – 1.840
V
[a] Outputs terminated with 50 to VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting), VDD_V – 2.0V (750mV
amplitude setting), VDD_V – 2.25V (1000mV amplitude setting).
Table 50. LVDS DC Characteristics (QCLK_y, QREF_r, STYLE = 0), VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)
Symbol
VOS
VOS
Parameter
Offset Voltage[a]
Test Conditions
Minimum
Typical
Maximum
Units
250mV amplitude setting
2.10
2.40
2.70
V
500mV amplitude setting
1.90
2.23
2.60
V
750mV amplitude setting
1.80
2.08
2.4
V
1000mV amplitude setting
1.60
1.93
2.20
V
80
mV
VOS Magnitude Change
[a] VOS changes with VDD_V.
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8V19N492 Datasheet
AC Characteristics
Table 51. AC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)[a][b][c]
Symbol
fVCO
fOUT
Parameter
VCO Frequency
Output Frequency
fCLK
Input Frequency
fVCXO
VCXO Frequency
Δfp
Test Conditions
Minimum
Typical
Maximum
Units
2920
2949.12
3000
MHz
QCLK_y, QREF_r (Clock), N=÷1
2949.12
MHz
QCLK_y, QREF_r (Clock), N=÷2
1474.56
MHz
QCLK_y, QREF_r (Clock), N=÷3
983.04
MHz
QCLK_y, QREF_r (Clock), N=÷6
491.52
MHz
QCLK_y, QREF_r (Clock), N=÷12
245.76
MHz
QCLK_y, QREF_r (Clock), N=÷24
122.88
MHz
QREF_r (SYSREF)
0.576
CLK_n
1.92[d]
30.72
30.72
MHz
245.76
2000
MHz
122.88
500
MHz
Static Frequency Error
fCLK = 0pbb frequency deviation
0
ppb
Δfrms
Dynamic Frequency Error
RMS[e]
fCLK = 0ppb frequency deviation
0.5
ppb
VIN
Input Voltage Amplitude[f]
CLK_n, nCLK_n
0.15
1.2
V
VDIFF_IN
Differential Input Voltage
Amplitude[f][g]
CLK_n - nCLK_n
0.3
2.4
V
1.0
VDD_V –
V
55
%
QCLK_y, QREF_r (LVPECL), 20–80%
250
ps
QCLK_y, QREF_r (LVDS), 20–80%
250
ps
QREF_r (SYSREF, LVDS), 20–80%
250
ps
1
ns
VCMR
odc
tR / t F
Common Mode Input Voltage
Output Duty Cycle
Output Rise/Fall Time,
Differential
Output Rise/Fall Time
LVPECL Output Voltage
Swing, Peak-to-peak,
1474.56MHz
VO(PP)[h]
LVPECL Differential Output
Voltage Swing, Peak-to-peak,
1474.56MHz
©2020 Renesas Electronics Corporation
QCLK_y, QREF_r (Clock)
45
(VIN / 2)
50
LVCMOS outputs, 20%-80%
250mV Amplitude Setting
190
272
367
mV
500mV Amplitude Setting
394
505
634
mV
750mV Amplitude Setting
598
733
875
mV
1000mV Amplitude Setting
784
946
1090
mV
250mV Amplitude Setting
380
544
734
mV
500mV Amplitude Setting
788
1010
1268
mV
750mV Amplitude Setting
1196
1466
1750
mV
1000mV Amplitude Setting
1585
1892
2180
mV
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8V19N492 Datasheet
Table 51. AC Characteristics, VDD_V = 3.3V ±5%, TA = -40°C to +105°C (Case)[a][b][c]
Symbol
Parameter
LVDS Output Voltage Swing,
Peak-to-peak, 1474.56MHz
VOD[i]
LVDS Differential Output
Voltage Swing, Peak-to-peak,
1474.56MHz
ΔtPD
tsk(o)
ΔΦ
Output Skew[j][k]
All delays set to 0
Output isolation between any
neighboring clock output
Output isolation between any
QCLK_y, QREF_r (SYSREF[l])
output
tD, LOS
LOS state detected (Measured
in input reference periods)
tD, RES
Minimum
Typical
Maximum
Units
250mV Amplitude Setting
128
193
273
mV
500mV Amplitude Setting
312
404
512
mV
750mV Amplitude Setting
490
615
757
mV
1000mV Amplitude Setting
676
822
992
mV
250mV Amplitude Setting
256
386
546
mV
500mV Amplitude Setting
624
808
1024
mV
750mV Amplitude Setting
980
1230
1514
mV
1000mV Amplitude Setting
1352
1644
1984
mV
+200
ps
QCLK_y (same N divider)
100
ps
QCLK_y (any N divider, incident rising
edge)
100
ps
QREF_r (Clock)
100
ps
QREF_r (SYSREF)
100
ps
QREF_r (Clock) to QCLK_y (any
divider, incident rising QCLK edge)
150
QREF_r (SYSREF) to QCLK_y (any
divider, incident rising QCLK edge)
150
Propagation delay variation
between reference input and
any QCLK_y output
ΔΦ
tD, LOCK
Test Conditions
PLL lock detect
PLL lock residual time error
©2020 Renesas Electronics Corporation
-200
fOUT = 983.04MHz
ps
ps
77
dB
fOUT = 491.52MHz
65
83
dB
fOUT = 245.76MHz
70
86
dB
Both SYSREF and clock signals
active
50
60
dB
fIN = 122.88MHz
2
fIN = 245.76MHz
3
TIN
PLL re-lock time after a short-term
holdover scenario. Measured from
LOS to both PLLs lock-detect
asserted; hold-off timer = 200ms,
initial frequency error 500Hz
-60
-56
dBc
15.36MHz
> 500Hz
-60
-56
dBc
7.68MHz
> 500Hz
-60
-56
dBc
[a] Design target specifications.
[b] Phase noise is measured as additive phase noise contribution by the device on all SYSREF outputs, dividers and channel logic. SYSREF signals
measured as continued clock signal. Clock signals (QCLK) are turned on.
[c] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[d] Measured as sum of all spurious amplitudes in one side band in the offset frequency range above 500Hz, excluding the harmonics of the
fundamental frequency of n*fSYSREF (e.g., n*7.68MHz)).
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Table 55. AC Characteristics: Typical QCLK_y Output Amplitude, VDD_V = 3.3V, TA = 85°C[a]
QCLK_y Output Frequency in MHz
Symbol
VO(PP)[b]
VOD[c]
Parameter
LVPECL Output
Voltage Swing,
Peak-to-peak
LVDS Output
Voltage Swing,
Peak-to-peak
Test Conditions
2949.12
1474.56
983.04
737.28
491.52
245.76
Units
250mV Amplitude Setting
214
283
260
262
264
281
mV
500mV Amplitude Setting
376
520
492
484
508
520
mV
750mV Amplitude Setting
512
748
740
716
730
768
mV
1000mV Amplitude Setting
628
960
984
944
968
1008
mV
250mV Amplitude Setting
120
190
200
210
215
225
mV
500mV Amplitude Setting
250
390
410
430
440
470
mV
750mV Amplitude Setting
370
592
650
670
682
710
mV
1000mV Amplitude Setting
475
790
870
900
920
980
mV
[a] Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted
in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been
reached under these conditions.
[b] LVPECL outputs terminated with 50 to VDD_V – 1.5V (250mV amplitude setting), VDD_V – 1.75V (500mV amplitude setting), VDD_V – 2.0V
(750mV amplitude setting), VCCO – 2.25V (1000mV amplitude setting)
[c] LVDS outputs terminated 100 across terminals
Figure 8. EXT_SYS Input Timing Diagram
CLK_n
tS
EXT_SYS
QREF_r
tH
tW
Valid EXT_SYS
High Impedance
Clock Phase Noise Characteristics
Conditions for Phase Noise Characteristics:
VCXO characteristics: f=122.88 MHz and phase noise: -85dBc/Hz(10Hz), -115dBc/Hz(100Hz), -145dBc/Hz(1kHz),
-155dBc/Hz(10kHz), -160dBc/Hz(100kHz)
▪
▪
▪
▪
▪
Input reference frequency: 122.88MHz
VCXO-PLL bandwidth: 27Hz
VCXO-PLL charge pump current: 0.75mA
FemtoClock-NG PLL bandwidth: 139kHz
VDD_V = 3.3V, T A = 25oC
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8V19N492 Datasheet
Figure 9. 1474.56MHz Output Phase Noise
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8V19N492 Datasheet
Figure 10. 491.52MHz Output Phase Noise
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8V19N492 Datasheet
Figure 11. 245.76MHz Output Phase Noise
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8V19N492 Datasheet
Application Information
Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0)
Figure 12 shows an example termination for the QCLK_y, QREF_r LVDS outputs. In this example, the characteristic transmission line
impedance is 50. The termination resistor R (100) is matched to the line impedance. The termination resistor must be placed at the
line end. No external termination resistor is required if R is an internal part of the receiver circuit. The LVDS termination in Figure 12 is
applicable for any output amplitude setting specified in Table 15.
Figure 12. LVDS (SYLE=0) Output Termination
VDD_V
T=50
R=100
LVDS
AC Termination for QCLK_y, QREF_r LVDS Outputs (STYLE = 0)
Figure 13 and Figure 14 show example AC terminations for the QCLK_y, QREF_r LVDS outputs. In the examples, the characteristic
transmission line impedance is 50. In Figure 13, the termination resistor R (100) is placed at the line end. No external termination
resistor is required if R is an internal part of the receiver circuit, which is shown in Figure 14. The LVDS terminations in both Figure 13 and
Figure 14 are applicable for any output amplitude setting specified in Table 15. The receiver input should be re-biased according to its
common mode range specifications.
Figure 13. LVDS (STYLE = 0) AC Output Termination
VDD_V
VBIAS
0.1µF
T=50
0.1µF
R=100
LVDS
Figure 14. LVDS (STYLE = 0) AC Output Termination
VDD_V
0.1µF
T=50
0.1µF
LVDS
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Termination for QCLK_y, QREF_r LVPECL Outputs (STYLE = 1)
Figure 15 shows an example termination for the QCLK_y, QREF_r LVPECL outputs. In this example, the characteristic transmission line
impedance is 50. The R1 (50) and R2 (50)resistors are matched load terminations. The output is terminated to the termination
voltage VT. The VT must be set according to the output amplitude setting defined in Table 15. The termination resistors must be placed
close at the line end.
Figure 15. LVPECL (STYLE = 1) Output Termination
VT = VDD_V - 1.50V (250 mV Amplitude)
VT = VDD_V - 1.75V (500 mV Amplitude)
VDD_V
VT
R1=50
R2=50
T=50
LVPECL
Thermal Characteristics
Package Exposed Pad Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 16. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed
on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.
Figure 16. Assembly for Exposed Pad Thermal Release Path – Side View (Drawing not to Scale)
While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat pipes.” The number of vias (i.e., “heat pipes”) are application-specific
and are dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12 to 13 mils (0.30 to 0.33 mm) with 1oz copper via barrel plating. This
is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and
the land pattern.
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
Note: These recommendations are to be used as a guideline only. For more information, refer to the Application Note on the Surface
Mount Assembly of Amkor’s Thermally/Electrically Enhance Lead-frame Base Package, Amkor Technology.
Thermal Characteristics
The 8V19N492 is a multi-functional, high-speed device that targets a wide variety of clock frequencies and applications. Since this device
is highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and
functions is enabled. The device was designed and characterized to operate within the industrial temperature range of -40°C to +105°C
(Case). The ambient temperature represents the temperature around the device, not the junction temperature. When using the device in
extreme cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a
safe and reliable junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature. For any concerns on
calculating the power dissipation for your own specific configuration, please contact Renesas technical support.
Table 56. Thermal Resistance[a]
Symbol
JA
Thermal Parameter
Junction to Ambient
Condition
Value
Unit
0 m/s air flow
17.2
°C/W
1 m/s air flow
16.1
°C/W
2 m/s air flow
15.6
°C/W
JC
Junction to Case
22.6
°C/W
JB
Junction to Board
0.9
°C/W
[a] Standard JEDEC 2S2P multilayer PCB.
Case Temperature Considerations
The 8V19N492 supports applications in a natural convection environment that does not have any thermal conductivity through ambient
air. The PCB is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific temperature. The
device package design incorporates an exposed pad (ePad) with enhanced thermal parameters that is soldered to the PCB where most
of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the junction-to-board thermal
characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not exceed the maximum allowed
junction temperature in Absolute Maximum Ratings.
The junction-to-board thermal characterization parameter, JB , is calculated using the following equation:
TJ = TCB + JB x PD, where
TJ = Junction temperature at steady state condition in (oC).
TCB = Case temperature (Bottom) at steady state condition in (oC).
JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board
measured at the top surface of the board.
PD = Power dissipation (W) in desired operating configuration.
TJ
TCB
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
The ePad provides a low thermal resistance path for heat transfer to the PCB and represents the key pathway to transfer heat away from
the IC to the PCB. It is critical that the connection of the exposed pad to the PCB is properly constructed to maintain the desired IC case
temperature (TCB). A good connection ensures that temperature at the exposed pad (TCB) and the board temperature (TB) are relatively
the same. An improper connection can lead to increased junction temperature, increased power consumption, and decreased electrical
performance. In addition, there could be long-term reliability issues and increased failure rate.
Example Calculation for Junction Temperature (TJ): TJ = TCB + JB x PD
PD = 3.27W (PD is calculated from Table 45)
TJ = 105°C + 0.7°C/W 3.27W = 107.3°C < 125°C
Table 57. Thermal Resistance for 88-VFQFPN Package
Package Type
88-VFQFPN
Body size (mm)
10 10 mm
ePad size (mm)
8 8 mm2
Thermal Via
8 8 Matrix
JB
0.7°C/W
TCB
105°C
Recommended Application Schematics
Figure 17 and Figure 18 show an 8V19N492 application schematic example in which the device is operated from a 3.3V power supply. To
ensure the logic control inputs are properly set for the application, see Pin Descriptions.
©2020 Renesas Electronics Corporation
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November 5, 2020
8V19N492 Datasheet
Figure 17. Application Schematics – Page 1
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November 5, 2020
71
©2020 Renesas Electronics Corporation
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8V19N492 Datasheet
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Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information
is the most current data available.
www.idt.com/document/psc/88-vfqfpn-package-outline-drawing-100-x-100-x-085-mm-body-04mm-pitchepad-810-x-810-mm-nlg88p2
©2020 Renesas Electronics Corporation
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November 5, 2020
8V19N492 Datasheet
Marking Diagram
▪ Line 1 is the part number.
▪ Line 2 indicates the following:
• “#” denotes stepping.
• “YY” is the last two digits of the year and “WW” is a work week number
that the part was assembled.
• “$” denotes the mark code.
▪ Line 3 is the assembly lot number.
Ordering Information
Orderable Part Number
8V19N492NLGI
8V19N492NLGI8
8V19N492NLGI/W
Package
Carrier Type
Temperature
Tray
10 x 10 mm, 88-VFQFPN
RoHS 6/6
ePad option P2:
8.1 x 8.1mm nominal
Tape and Reel,
Pin 1 Orientation: EIA-481-C
-40°C to +105°C (Case)
Tape and Reel,
Pin 1 Orientation: EIA-481-D/E
Table 58. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
8
Quadrant 1
(EIA-481-C)
/W
Quadrant 2
(EIA-481-D/E)
©2020 Renesas Electronics Corporation
Illustration
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November 5, 2020
8V19N492 Datasheet
Glossary
Abbreviation
Description
Index n
Denominates a clock input CLK_n. Range: 0 to 1
Index x
Denominates a channel, channel frequency divider and the associated configuration bits. Range: A, B, C, D, E.
Index y
Denominates a QCLK output and associated configuration bits. Range: A0, A1, B0, B1, C, D, E0, E1
Index r
Denominates a QREF output and associated configuration bits. Range: A0, A1, A2, B0, B1, C, D
VDD_V
Denominates voltage supply pins. Range: VDD_QCLKA, VDD_QCLKB, VDD_QCLKC, VDD_QCLKD, VDD_QCLKE,
VDD_QREFA0, VDD_QREFA1, VDD_QREFA2, VDD_QREFB0, VDD_QREFB1, VDD_QREFC, VDD_QREFD,
VDD_SPI, VDD_QCLKV, VDD_CPV, VDD_INP, VDD_CPF, VDD_LCF, VDD_LCV1, VDD_LCV2, VDD_SYNC
[...]
Index brackets describe a group associated with a logical function or a bank of outputs.
{…}
List of discrete values
Suffix V
Denominates a function associated with the VCXO-PLL
Suffix F
Denominates a function associated with the 2nd stage PLL (FemtoClock NG)
Revision History
Revision Date
November 5, 2020
Description of Change
Updated Output Phase Delay
April 20, 2020
Updated the description of pin 85 in Table 1.
December 17, 2019
Updated the description of pin 35 in Table 1.
September 19, 2018
Initial release.
©2020 Renesas Electronics Corporation
74
November 5, 2020
88-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.85 mm Body, 0.4mm Pitch,Epad 8.10 x 8.10 mm
NLG88P2, PSC-4451-02, Rev 02, Page 1
88-VFQFPN, Package Outline Drawing
10.0 x 10.0 x 0.85 mm Body, 0.4mm Pitch,Epad 8.10 x 8.10 mm
NLG88P2, PSC-4451-02, Rev 02, Page 2
Package Revision History
Date Created
Rev No. Description
March 8, 2018
Rev 02 Change QFN to VFQFPN, Change Pin 1 Identifier
Dec 4, 2017
Rev 01 New Format
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