8V79S674NLGI

Differential-to-3.3V, 2.5V LVPECL Clock Divider and Fanout Buffer 8V79S674 DATA SHEET General Description Features The 8V79S674 is a clock divider and fanout buffer. The device has been designed for clock signal division in wireless base station radio equipment boards. The device is optimized to deliver excellent additive phase jitter performance. The 8V79S674 uses SiGe technology for an optimum of high clock frequency and low phase noise performance, combined with high power supply noise rejection. The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four low-skew LVPECL outputs are available and support clock output frequencies up to 2500MHz (÷1 frequency division). Outputs can be disabled to save power consumption if not used. The device is packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The extended temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. • • • • • • • • • • • Maximum frequency: 2500MHz Maximum output skew: 50ps (maximum) Maximum LVPECL output rise/fall time: 200ps (maximum) 3.3V or 2.5V core and output supply mode Supports 1.8V I/O logic levels for all control pins -40°C to 85°C ambient operating temperature Available in lead-free (RoHS 6) package Q1 nQ1 nQ2 Q2 VCC Q0 nQ0 2x 50 15 14 13 12 11 VCC 16 10 Q0 17 9 nQ3 nQ0 18 8 nOEB nOEA 19 7 N1 VEE 20 6 VEE Q3 Reference Voltage 1 2 3 4 5 N0 Q3 nQ3 IN Pulldown 8V79S674 VT Q2 nQ2 VREFAC Pulldown Pulldown nIN N[1:0] nOEA nOEB Supports frequency division of ÷1, ÷2, ÷4 and ÷8 Pin Assignment ÷N VT VREFAC Four low-skew LVPECL clock outputs Q1 IN nIN SiGe technology for high-frequency and fast signal rise/fall times nQ1 Block Diagram Clock signal division and distribution 20-pin, 4mm x 4mm VFQFN Package . 8V79S674 REVISION 2 04/10/15 1 ©2015 Integrated Device Technology, Inc. 8V79S674 DATA SHEET Pin Description and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1 nIN Input 2 VREFAC Output 3 VT 4 IN Input 5, 7 N0, N1 Input 6, 20 VEE Power 8 nOEB Input 9, 10 nQ3, Q3 Output Differential clock output pair. LVPECL output levels. 11, 16 VCC Power Power supply voltage. 12, 13 Q2, nQ2 Output Differential clock output pair. LVPECL output levels 14, 15 Q1, nQ1 Output Differential clock output pair. LVPECL output levels 17, 18 Q0, nQ0 Output Differential clock output pair. LVPECL output levels 19 nOEA Input — VEE_EP Power Inverting differential clock signal input. Internal termination 50 to VT. Reference voltage for AC-coupled applications of IN, nIN. Leave open if IN, nIN is used with LVDS signals. Connect 50 to VEE if IN, nIN is used with LVPECL signals. Non-inverting differential clock signal input. Internal termination 50 to VT. Pulldown Frequency divider controls. 1.8V LVCMOS/LVTTL interface levels. Negative power supply voltage (ground). Pulldown Pulldown Output enable control for the Q1, Q2 and Q3 outputs. 1.8V LVCMOS/LVTTL interface levels. Output enable control for the Q0 output. 1.8V LVCMOS/LVTTL interface levels. Exposed package pad negative supply voltage (ground). Return current path for the Q0, Q1, Q2 and Q3 outputs. This pin must be connected to ground. NOTE: Pulldown refers to an internal input resistor. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 2 pF RPULLDOWN Input Pulldown Resistor 51 k DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units REVISION 2 04/10/15 8V79S674 DATA SHEET Truth Tables Table 3A. Nx Clock Divider Function Table Input N1 N0 Divider Value 0 (default) 0 (default) ÷1 0 1 ÷2 1 0 ÷4 1 1 ÷8 Table 3B. nOEA Output Enable Function Table Input nOEA 0 (default) 1 Output Operation Q0 is enabled Q0 is disabled in logic Low state Table 3C. nOEB Output Enable Function Table Input nOEB 0 (default) 1 REVISION 2 04/10/15 Output Operation Q1, Q2 and Q3 are enabled Q1, Q2 and Q3 are disabled in logic Low state 3 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO  Continuous Current Surge Current  50mA 100mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA Input Sink/Source, IREF_AC ±2mA TJ 125C Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 80 90 mA Outputs Unloaded Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions VCC Power Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 75 85 mA Outputs Unloaded Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current N[1:0], nOEA, nOEB VCC = VIN = 3.465V or 2.625V IIL Input Low Current N[1:0], nOEA, nOEB VCC = 3.465V or 2.625V, VIN = 0V DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER Test Conditions Minimum VCC = 3.3V Maximum Units 1.2 VCC V VCC = 2.5V 1.2 VCC V 1.8V logic -0.3 0.3 V 150 µA 4 -10 Typical uA REVISION 2 04/10/15 8V79S674 DATA SHEET Table 4D. Differential DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter RIN Input Resistance IN, nIN IIN Input Current IN, nIN VREFAC Bias Voltage Test Conditions Minimum Typical Maximum Units IN to VT, nIN to VT 40 50 60  30 mA VCC – 1.28 VCC – 1.0 V Typical Maximum Units VCC = 2.5V or 3.3V IREFAC = ± 1mA VCC – 1.5 Table 4E. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions 1 Minimum VOH Output High Voltage VCC – 1.1 VCC – 0.7 V VOL Output Low Voltage; NOTE 1 VCC – 1.8 VCC – 1.4 V VOUT Output Voltage Swing 0.5 1 V VDIFF_OUT Differential Output Voltage Swing 1 2 V NOTE 1. Outputs terminated with 50 to VCC – 2V. Table 4F. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C Symbol Parameter Test Conditions Output High Voltage1 VOL Output Low Voltage1 VOUT Output Voltage Swing VDIFF_OUT Differential Output Voltage Swing VOH Minimum Typical Maximum Units VCC – 1.1 VCC – 0.7 V VCC – 1.8 VCC – 1.4 V 0.5 1.0 V 1 2 V NOTE 1. Outputs terminated with 50 to VCC – 2V. REVISION 2 04/10/15 5 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET AC Electrical Characteristics Table 5. AC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C1 Symbol fOUT Parameter Test Conditions Output Frequency Minimum Typical Maximum Units N=÷1 2500 MHz N=÷2 1250 MHz N=÷4 625 MHz N=÷8 312.5 MHz 2500 MHz 1.0 VCC – VPP/2 V fIN Input Frequency VCMR Common Mode Input Voltage2 VPP Input Voltage Swing 0.15 1.3 V VDIFF_IN Differential Input Voltage Swing 0.3 2.6 V tsk(o) Output Skew3, 4 50 ps 200 ps tsk(pp) 22 3, 5 Part-to-Part Skew Noise Floor tjit() IN, nIN 6 Buffer Additive Phase Jitter Output Isolation 100kHz Offset, fOUT = 1228.8MHz -146 fREF = fOUT = 156.25MHz, Integration Range: 12kHz to 20MHz 42 fOUT = 1228.8MHz 90 dBc fOUT = 614.4MHz 90 dBc fOUT = 307.2MHz 90 dBc fOUT = 153.6MHz odc Output Duty Cycle tR / tF Output Rise/Fall Time tPD Propagation Delay 50% Input Duty Cycle dBc/Hz 60 95 44 20% to 80% 200 50 fs dBc 56 % 200 ps 550 ps NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 2. Common mode input voltage is defined as the signal cross point. NOTE 3. This parameter is defined in accordance with JEDEC Standard 65. NOTE 4. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 5. Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6. The phase noise at 100kHz offset of the applied input clock is -146 dBc/Hz. DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 6 REVISION 2 04/10/15 8V79S674 DATA SHEET Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio SSB Phase Noise dBc/Hz of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements have issues relating to the limitations of the measurement equipment. The noise floor of the equipment can be higher or lower than the noise floor of the device. Additive phase noise is dependent on both the noise floor of the input source and measurement equipment. REVISION 2 04/10/15 The additive phase jitter for this device was measured using a 156.25 MHz Wenzel oscillator as input clock source and an Agilent E5052 Phase noise analyzer. 7 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC Qx nQx SCOPE nQx VEE VEE -0.5V ± 0.125V -1.3V ± 0.165V 3.3V Output Load AC Test Circuit 2.5V Output Load AC Test Circuit VCC nIN nIN IN V Cross Points PP nQx IN V Qx CMR tPD VEE Propagation Delay Input Levels nQx 80% VPP, VOUT 80% VDIFF_IN, VDIFF_OUT VOUT 20% 20% Qx tF Output Rise/Fall Time Single-Ended & Differential Input Swing DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER tR 8 REVISION 2 04/10/15 8V79S674 DATA SHEET Parameter Measurement Information, continued Par t 1 nQx nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(pp) Output Skew REVISION 2 04/10/15 Part-to-Part Skew 9 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET Applications Information Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Select Pins LVPECL Outputs All control pins have internal pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 2.5V LVPECL Input with Built-In 50 Termination Interface The IN /nIN with built-in 50 terminations accept LVDS, LVPECL, CML and other differential signals. Both VOH and VOL must meet the VIN and VIH input requirements. Figures 1A to 1D show interface examples for the IN/nIN with built-in 50 termination input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 1A. IN/nIN Input with Built-In 50 Driven by an LVDS Driver Figure 1B. IN/nIN Input with Built-In 50 Driven by an LVPECL Driver Figure 1C. IN/nIN Input with Built-In 50 Driven by a CML Driver Figure 1D. IN/nIN Input with Built-In 50 Driven by a CML Driver with Built-In 50 Pullup DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 10 REVISION 2 04/10/15 8V79S674 DATA SHEET 3.3V LVPECL Input with Built-In 50 Termination Interface The IN /nIN with built-in 50 terminations accept LVDS, LVPECL, CML and other differential signals. Both VOH and VOL must meet the VIN and VIH input requirements. Figures 2A to 2D show interface examples for the IN /nIN input with built-in 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. Figure 2A. IN/nIN Input with Built-In 50 Driven by an LVDS Driver Figure 2B. IN/nIN Input with Built-In 50 Driven by an LVPECL Driver 3.3V 3.3V 3.3V CML with Built-In Pullup Zo = 50Ω C1 IN 50Ω VT Zo = 50Ω C2 50Ω nIN V_REF_AC Receiver with Built-In 50Ω Figure 2D. IN/nIN Input with Built-In 50 Driven by a CML Driver with Built-In 50 Pullup Figure 2C. IN/nIN Input with Built-In 50 Driven by a CML Driver with Open Collector REVISION 2 04/10/15 11 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET Termination for 2.5V LVPECL Outputs level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250Ω 50Ω R3 250Ω + 50Ω + 50Ω – 50Ω 2.5V LVPECL Driver – R1 50Ω 2.5V LVPECL Driver R2 62.5Ω R2 50Ω R4 62.5Ω R3 18Ω Figure 3A. 2.5V LVPECL Driver Termination Example Figure 3B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50Ω + 50Ω – 2.5V LVPECL Driver R1 50Ω R2 50Ω Figure 3C. 2.5V LVPECL Driver Termination Example DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 12 REVISION 2 04/10/15 8V79S674 DATA SHEET Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V R4 125 3.3V 3.3V Zo = 50 + _ Input Zo = 50 R1 84 Figure 4A. 3.3V LVPECL Output Termination REVISION 2 04/10/15 R2 84 Figure 4B. 3.3V LVPECL Output Termination 13 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET VFQFN EPAD Thermal Release Path In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE THERMAL VIA SOLDER LAND PATTERN (GROUND PAD) PIN PIN PAD Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale) DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 14 REVISION 2 04/10/15 8V79S674 DATA SHEET Power Considerations 1. Power Dissipation The total power dissipation for the 8V79S674 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. Core • The maximum current at 85°C, Imax = 90mA • Power(core) = VCC_MAX * (IEE) = 3.465V * 90mA = 311.9mW  LVPECL Output LVPECL driver power dissipation is 35mW/Loaded output pair, total LVPECL output dissipation: • Power (outputs)MAX = 35mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 35mW = 140mW  Total Power Dissipation • Total Power = Power (core) + Power(LVPECL) = 311.9mW + 140mW = 451.9mW  2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 70.7°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.452W * 70.7°C/W = 117°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resistance JA for for a 20-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards REVISION 2 04/10/15 0 1 2 70.7°C/W 67.0°C/W 65.3°C/W 15 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pairs. LVPECL output driver circuit and termination are shown in Figure 7. VCC Q1 VOUT RL VCC - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC – 2V. • For logic high, VOUT = VOH_MAX = VCC_MAX – 0.7V (VCC_MAX – VOH_MAX) = 0.7V • For logic low, VOUT = VOL_MAX = VCC_MAX – 1.4V (VCC_MAX – VOL_MAX) = 1.4V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX)  = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX)  =[(2V – 0.7V)/50] * 0.7V = 18.2mW Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX)  = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX)  =[(2V – 1.4V)/50] * 1.4V = 16.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 35mW DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 16 REVISION 2 04/10/15 8V79S674 DATA SHEET Reliability Information Table 7. JA vs. Air Flow Table for a 20-Lead VFQFN JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2 70.7°C/W 67.0°C/W 65.3°C/W Transistor Count The transistor count for 8V79S674: 1255 REVISION 2 04/10/15 17 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET 20-Lead VFQFN Package Outline and Package Dimensions DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 18 REVISION 2 04/10/15 8V79S674 DATA SHEET Ordering Information Table 8. Ordering Information Part/Order Number Marking Package Shipping Packaging Temperature 8V79S674NLGI 8V79S674NLGI “Lead-Free” 20-Lead VFQFN Tray -40C to 85C 8V79S674NLGI8 8V79S674NLGI “Lead-Free” 20-Lead VFQFN Tape & Reel -40C to 85C NOTE: Parts that are ordered with an “G” suffix to the part number are the Pb-Free configuration and are RoHS compliant. REVISION 2 04/10/15 19 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 8V79S674 DATA SHEET Revision History Sheet Rev 2 Table Page T5 6 Description of Change Date AC Characteristics Table - corrected frequencies for FOUT N÷2, N÷4, N÷8. fIN changed from 2.5GHz to 2500MHz. DIFFERENTIAL-TO-3.3V, 2.5V LVPECL CLOCK DIVIDER AND FANOUT BUFFER 20 4/10/15 REVISION 2 04/10/15 Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com email: clocks@idt.com DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. 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